1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1.	Redistributions of source code must retain the above copyright
10 *	notice, this list of conditions and the following disclaimer.
11 * 2.	Redistributions in binary form must reproduce the above copyright
12 *	notice, this list of conditions and the following disclaimer in the
13 *	documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD$");
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/kernel.h>
35#include <sys/module.h>
36#include <sys/rman.h>
37#include <sys/proc.h>
38#include <sys/lock.h>
39#include <sys/mutex.h>
40
41#include <machine/bus.h>
42#include <machine/intr.h>
43
44#include <dev/ofw/openfirm.h>
45#include <dev/ofw/ofw_bus.h>
46#include <dev/ofw/ofw_bus_subr.h>
47
48#include "pic_if.h"
49
50struct imx7gpc_softc {
51	device_t		dev;
52	struct resource		*memres;
53	device_t		parent;
54};
55
56static struct ofw_compat_data compat_data[] = {
57	{ "fsl,imx7gpc",		1},
58	{ "fsl,imx8mq-gpc",		1},
59	{ NULL,				0}
60};
61
62static int
63imx7gpc_activate_intr(device_t dev, struct intr_irqsrc *isrc,
64    struct resource *res, struct intr_map_data *data)
65{
66	struct imx7gpc_softc *sc = device_get_softc(dev);
67
68	return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
69}
70
71static void
72imx7gpc_disable_intr(device_t dev, struct intr_irqsrc *isrc)
73{
74	struct imx7gpc_softc *sc = device_get_softc(dev);
75
76	PIC_DISABLE_INTR(sc->parent, isrc);
77}
78
79static void
80imx7gpc_enable_intr(device_t dev, struct intr_irqsrc *isrc)
81{
82	struct imx7gpc_softc *sc = device_get_softc(dev);
83
84	PIC_ENABLE_INTR(sc->parent, isrc);
85}
86
87static int
88imx7gpc_map_intr(device_t dev, struct intr_map_data *data,
89    struct intr_irqsrc **isrcp)
90{
91	struct imx7gpc_softc *sc = device_get_softc(dev);
92
93	return (PIC_MAP_INTR(sc->parent, data, isrcp));
94}
95
96static int
97imx7gpc_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
98    struct resource *res, struct intr_map_data *data)
99{
100	struct imx7gpc_softc *sc = device_get_softc(dev);
101
102	return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data));
103}
104
105static int
106imx7gpc_setup_intr(device_t dev, struct intr_irqsrc *isrc,
107    struct resource *res, struct intr_map_data *data)
108{
109	struct imx7gpc_softc *sc = device_get_softc(dev);
110
111	return (PIC_SETUP_INTR(sc->parent, isrc, res, data));
112}
113
114static int
115imx7gpc_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
116    struct resource *res, struct intr_map_data *data)
117{
118	struct imx7gpc_softc *sc = device_get_softc(dev);
119
120	return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data));
121}
122
123static void
124imx7gpc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
125{
126	struct imx7gpc_softc *sc = device_get_softc(dev);
127
128	PIC_PRE_ITHREAD(sc->parent, isrc);
129}
130
131static void
132imx7gpc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
133{
134	struct imx7gpc_softc *sc = device_get_softc(dev);
135
136	PIC_POST_ITHREAD(sc->parent, isrc);
137}
138
139static void
140imx7gpc_post_filter(device_t dev, struct intr_irqsrc *isrc)
141{
142	struct imx7gpc_softc *sc = device_get_softc(dev);
143
144	PIC_POST_FILTER(sc->parent, isrc);
145}
146
147#ifdef SMP
148static int
149imx7gpc_bind_intr(device_t dev, struct intr_irqsrc *isrc)
150{
151	struct imx7gpc_softc *sc = device_get_softc(dev);
152
153	return (PIC_BIND_INTR(sc->parent, isrc));
154}
155#endif
156
157static int
158imx7gpc_probe(device_t dev)
159{
160
161	if (!ofw_bus_status_okay(dev))
162		return (ENXIO);
163
164	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
165		return (ENXIO);
166
167	device_set_desc(dev, "General Power Controller");
168	return (BUS_PROBE_DEFAULT);
169}
170
171static int
172imx7gpc_attach(device_t dev)
173{
174	struct imx7gpc_softc *sc = device_get_softc(dev);
175	phandle_t node;
176	phandle_t parent_xref;
177	int i, rv;
178
179	sc->dev = dev;
180
181	node = ofw_bus_get_node(dev);
182
183	rv = OF_getencprop(node, "interrupt-parent", &parent_xref,
184	    sizeof(parent_xref));
185	if (rv <= 0) {
186		device_printf(dev, "Can't read parent node property\n");
187		return (ENXIO);
188	}
189	sc->parent = OF_device_from_xref(parent_xref);
190	if (sc->parent == NULL) {
191		device_printf(dev, "Can't find parent controller\n");
192		return (ENXIO);
193	}
194
195	i = 0;
196	sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
197	    RF_ACTIVE);
198	if (sc->memres == NULL) {
199		device_printf(dev, "could not allocate resources\n");
200		return (ENXIO);
201	}
202
203	/* TODO: power up OTG domain and unmask all interrupts */
204
205	if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
206		bus_release_resource(dev, SYS_RES_MEMORY, i, sc->memres);
207		device_printf(dev, "Cannot register PIC\n");
208		return (ENXIO);
209	}
210
211	return (0);
212}
213
214static device_method_t imx7gpc_methods[] = {
215	DEVMETHOD(device_probe,		imx7gpc_probe),
216	DEVMETHOD(device_attach,	imx7gpc_attach),
217
218	/* Interrupt controller interface */
219	DEVMETHOD(pic_activate_intr,	imx7gpc_activate_intr),
220	DEVMETHOD(pic_disable_intr,	imx7gpc_disable_intr),
221	DEVMETHOD(pic_enable_intr,	imx7gpc_enable_intr),
222	DEVMETHOD(pic_map_intr,		imx7gpc_map_intr),
223	DEVMETHOD(pic_deactivate_intr,	imx7gpc_deactivate_intr),
224	DEVMETHOD(pic_setup_intr,	imx7gpc_setup_intr),
225	DEVMETHOD(pic_teardown_intr,	imx7gpc_teardown_intr),
226	DEVMETHOD(pic_pre_ithread,	imx7gpc_pre_ithread),
227	DEVMETHOD(pic_post_ithread,	imx7gpc_post_ithread),
228	DEVMETHOD(pic_post_filter,	imx7gpc_post_filter),
229#ifdef SMP
230	DEVMETHOD(pic_bind_intr,	imx7gpc_bind_intr),
231#endif
232
233	DEVMETHOD_END
234};
235
236static driver_t imx7gpc_driver = {
237	"imx7gpc",
238	imx7gpc_methods,
239	sizeof(struct imx7gpc_softc),
240};
241
242static devclass_t imx7gpc_devclass;
243
244EARLY_DRIVER_MODULE(imx7gpc, ofwbus, imx7gpc_driver, imx7gpc_devclass, 0, 0,
245    BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
246EARLY_DRIVER_MODULE(imx7gpc, simplebus, imx7gpc_driver, imx7gpc_devclass, 0, 0,
247    BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
248