1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>. 5 * Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/** 31 * Driver for the I2C module on the TI SoC. 32 * 33 * This driver is heavily based on the TWI driver for the AT91 (at91_twi.c). 34 * 35 * CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses, 36 * 32 bit data access is not allowed and can corrupt register content. 37 * 38 * This driver currently doesn't use DMA for the transfer, although I hope to 39 * incorporate that sometime in the future. The idea being that for transaction 40 * larger than a certain size the DMA engine is used, for anything less the 41 * normal interrupt/fifo driven option is used. 42 */ 43 44#include <sys/cdefs.h> 45__FBSDID("$FreeBSD$"); 46 47#include <sys/param.h> 48#include <sys/systm.h> 49#include <sys/bus.h> 50#include <sys/conf.h> 51#include <sys/kernel.h> 52#include <sys/lock.h> 53#include <sys/mbuf.h> 54#include <sys/malloc.h> 55#include <sys/module.h> 56#include <sys/mutex.h> 57#include <sys/rman.h> 58#include <sys/sysctl.h> 59#include <machine/bus.h> 60 61#include <dev/ofw/openfirm.h> 62#include <dev/ofw/ofw_bus.h> 63#include <dev/ofw/ofw_bus_subr.h> 64 65#include <arm/ti/ti_cpuid.h> 66#include <arm/ti/ti_sysc.h> 67#include <arm/ti/ti_i2c.h> 68 69#include <dev/iicbus/iiconf.h> 70#include <dev/iicbus/iicbus.h> 71 72#include "iicbus_if.h" 73 74/** 75 * I2C device driver context, a pointer to this is stored in the device 76 * driver structure. 77 */ 78struct ti_i2c_softc 79{ 80 device_t sc_dev; 81 struct resource* sc_irq_res; 82 struct resource* sc_mem_res; 83 device_t sc_iicbus; 84 85 void* sc_irq_h; 86 87 struct mtx sc_mtx; 88 89 struct iic_msg* sc_buffer; 90 int sc_bus_inuse; 91 int sc_buffer_pos; 92 int sc_error; 93 int sc_fifo_trsh; 94 int sc_timeout; 95 96 uint16_t sc_con_reg; 97 uint16_t sc_rev; 98}; 99 100struct ti_i2c_clock_config 101{ 102 u_int frequency; /* Bus frequency in Hz */ 103 uint8_t psc; /* Fast/Standard mode prescale divider */ 104 uint8_t scll; /* Fast/Standard mode SCL low time */ 105 uint8_t sclh; /* Fast/Standard mode SCL high time */ 106 uint8_t hsscll; /* High Speed mode SCL low time */ 107 uint8_t hssclh; /* High Speed mode SCL high time */ 108}; 109 110#if defined(SOC_OMAP4) 111/* 112 * OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)). 113 * The prescaler values for 100KHz and 400KHz modes come from the table in the 114 * OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed. 115 */ 116static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = { 117 { 100000, 23, 13, 15, 0, 0}, 118 { 400000, 9, 5, 7, 0, 0}, 119 { 1000000, 3, 5, 7, 0, 0}, 120/* { 3200000, 1, 113, 115, 7, 10}, - HS mode */ 121 { 0 /* Table terminator */ } 122}; 123#endif 124 125#if defined(SOC_TI_AM335X) 126/* 127 * AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5)) 128 * In all cases we prescale the clock to 24MHz as recommended in the manual. 129 */ 130static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = { 131 { 100000, 1, 111, 117, 0, 0}, 132 { 400000, 1, 23, 25, 0, 0}, 133 { 1000000, 1, 5, 7, 0, 0}, 134 { 0 /* Table terminator */ } 135}; 136#endif 137 138/** 139 * Locking macros used throughout the driver 140 */ 141#define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 142#define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 143#define TI_I2C_LOCK_INIT(_sc) \ 144 mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \ 145 "ti_i2c", MTX_DEF) 146#define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx) 147#define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED) 148#define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED) 149 150#ifdef DEBUG 151#define ti_i2c_dbg(_sc, fmt, args...) \ 152 device_printf((_sc)->sc_dev, fmt, ##args) 153#else 154#define ti_i2c_dbg(_sc, fmt, args...) 155#endif 156 157/** 158 * ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers 159 * @sc: I2C device context 160 * @off: the byte offset within the register bank to read from. 161 * 162 * 163 * LOCKING: 164 * No locking required 165 * 166 * RETURNS: 167 * 16-bit value read from the register. 168 */ 169static inline uint16_t 170ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off) 171{ 172 173 return (bus_read_2(sc->sc_mem_res, off)); 174} 175 176/** 177 * ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers 178 * @sc: I2C device context 179 * @off: the byte offset within the register bank to read from. 180 * @val: the value to write into the register 181 * 182 * LOCKING: 183 * No locking required 184 * 185 * RETURNS: 186 * 16-bit value read from the register. 187 */ 188static inline void 189ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val) 190{ 191 192 bus_write_2(sc->sc_mem_res, off, val); 193} 194 195static int 196ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status) 197{ 198 int amount, done, i; 199 200 done = 0; 201 amount = 0; 202 /* Check for the error conditions. */ 203 if (status & I2C_STAT_NACK) { 204 /* No ACK from slave. */ 205 ti_i2c_dbg(sc, "NACK\n"); 206 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK); 207 sc->sc_error = ENXIO; 208 } else if (status & I2C_STAT_AL) { 209 /* Arbitration lost. */ 210 ti_i2c_dbg(sc, "Arbitration lost\n"); 211 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL); 212 sc->sc_error = ENXIO; 213 } 214 215 /* Check if we have finished. */ 216 if (status & I2C_STAT_ARDY) { 217 /* Register access ready - transaction complete basically. */ 218 ti_i2c_dbg(sc, "ARDY transaction complete\n"); 219 if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) { 220 ti_i2c_write_2(sc, I2C_REG_CON, 221 sc->sc_con_reg | I2C_CON_STP); 222 } 223 ti_i2c_write_2(sc, I2C_REG_STATUS, 224 I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY | 225 I2C_STAT_XDR | I2C_STAT_XRDY); 226 return (1); 227 } 228 229 if (sc->sc_buffer->flags & IIC_M_RD) { 230 /* Read some data. */ 231 if (status & I2C_STAT_RDR) { 232 /* 233 * Receive draining interrupt - last data received. 234 * The set FIFO threshold won't be reached to trigger 235 * RRDY. 236 */ 237 ti_i2c_dbg(sc, "Receive draining interrupt\n"); 238 239 /* 240 * Drain the FIFO. Read the pending data in the FIFO. 241 */ 242 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 243 } else if (status & I2C_STAT_RRDY) { 244 /* 245 * Receive data ready interrupt - FIFO has reached the 246 * set threshold. 247 */ 248 ti_i2c_dbg(sc, "Receive data ready interrupt\n"); 249 250 amount = min(sc->sc_fifo_trsh, 251 sc->sc_buffer->len - sc->sc_buffer_pos); 252 } 253 254 /* Read the bytes from the fifo. */ 255 for (i = 0; i < amount; i++) 256 sc->sc_buffer->buf[sc->sc_buffer_pos++] = 257 (uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff); 258 259 if (status & I2C_STAT_RDR) 260 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR); 261 if (status & I2C_STAT_RRDY) 262 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY); 263 264 } else { 265 /* Write some data. */ 266 if (status & I2C_STAT_XDR) { 267 /* 268 * Transmit draining interrupt - FIFO level is below 269 * the set threshold and the amount of data still to 270 * be transferred won't reach the set FIFO threshold. 271 */ 272 ti_i2c_dbg(sc, "Transmit draining interrupt\n"); 273 274 /* 275 * Drain the TX data. Write the pending data in the 276 * FIFO. 277 */ 278 amount = sc->sc_buffer->len - sc->sc_buffer_pos; 279 } else if (status & I2C_STAT_XRDY) { 280 /* 281 * Transmit data ready interrupt - the FIFO level 282 * is below the set threshold. 283 */ 284 ti_i2c_dbg(sc, "Transmit data ready interrupt\n"); 285 286 amount = min(sc->sc_fifo_trsh, 287 sc->sc_buffer->len - sc->sc_buffer_pos); 288 } 289 290 /* Write the bytes from the fifo. */ 291 for (i = 0; i < amount; i++) 292 ti_i2c_write_2(sc, I2C_REG_DATA, 293 sc->sc_buffer->buf[sc->sc_buffer_pos++]); 294 295 if (status & I2C_STAT_XDR) 296 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR); 297 if (status & I2C_STAT_XRDY) 298 ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY); 299 } 300 301 return (done); 302} 303 304/** 305 * ti_i2c_intr - interrupt handler for the I2C module 306 * @dev: i2c device handle 307 * 308 * 309 * 310 * LOCKING: 311 * Called from timer context 312 * 313 * RETURNS: 314 * EH_HANDLED or EH_NOT_HANDLED 315 */ 316static void 317ti_i2c_intr(void *arg) 318{ 319 int done; 320 struct ti_i2c_softc *sc; 321 uint16_t events, status; 322 323 sc = (struct ti_i2c_softc *)arg; 324 325 TI_I2C_LOCK(sc); 326 327 status = ti_i2c_read_2(sc, I2C_REG_STATUS); 328 if (status == 0) { 329 TI_I2C_UNLOCK(sc); 330 return; 331 } 332 333 /* Save enabled interrupts. */ 334 events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET); 335 336 /* We only care about enabled interrupts. */ 337 status &= events; 338 339 done = 0; 340 341 if (sc->sc_buffer != NULL) 342 done = ti_i2c_transfer_intr(sc, status); 343 else { 344 ti_i2c_dbg(sc, "Transfer interrupt without buffer\n"); 345 sc->sc_error = EINVAL; 346 done = 1; 347 } 348 349 if (done) 350 /* Wakeup the process that started the transaction. */ 351 wakeup(sc); 352 353 TI_I2C_UNLOCK(sc); 354} 355 356/** 357 * ti_i2c_transfer - called to perform the transfer 358 * @dev: i2c device handle 359 * @msgs: the messages to send/receive 360 * @nmsgs: the number of messages in the msgs array 361 * 362 * 363 * LOCKING: 364 * Internally locked 365 * 366 * RETURNS: 367 * 0 on function succeeded 368 * EINVAL if invalid message is passed as an arg 369 */ 370static int 371ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs) 372{ 373 int err, i, repstart, timeout; 374 struct ti_i2c_softc *sc; 375 uint16_t reg; 376 377 sc = device_get_softc(dev); 378 TI_I2C_LOCK(sc); 379 380 /* If the controller is busy wait until it is available. */ 381 while (sc->sc_bus_inuse == 1) 382 mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0); 383 384 /* Now we have control over the I2C controller. */ 385 sc->sc_bus_inuse = 1; 386 387 err = 0; 388 repstart = 0; 389 for (i = 0; i < nmsgs; i++) { 390 sc->sc_buffer = &msgs[i]; 391 sc->sc_buffer_pos = 0; 392 sc->sc_error = 0; 393 394 /* Zero byte transfers aren't allowed. */ 395 if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL || 396 sc->sc_buffer->len == 0) { 397 err = EINVAL; 398 break; 399 } 400 401 /* Check if the i2c bus is free. */ 402 if (repstart == 0) { 403 /* 404 * On repeated start we send the START condition while 405 * the bus _is_ busy. 406 */ 407 timeout = 0; 408 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 409 if (timeout++ > 100) { 410 err = EBUSY; 411 goto out; 412 } 413 DELAY(1000); 414 } 415 timeout = 0; 416 } else 417 repstart = 0; 418 419 if (sc->sc_buffer->flags & IIC_M_NOSTOP) 420 repstart = 1; 421 422 /* Set the slave address. */ 423 ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1); 424 425 /* Write the data length. */ 426 ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len); 427 428 /* Clear the RX and the TX FIFO. */ 429 reg = ti_i2c_read_2(sc, I2C_REG_BUF); 430 reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR; 431 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 432 433 reg = sc->sc_con_reg | I2C_CON_STT; 434 if (repstart == 0) 435 reg |= I2C_CON_STP; 436 if ((sc->sc_buffer->flags & IIC_M_RD) == 0) 437 reg |= I2C_CON_TRX; 438 ti_i2c_write_2(sc, I2C_REG_CON, reg); 439 440 /* Wait for an event. */ 441 err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout); 442 if (err == 0) 443 err = sc->sc_error; 444 445 if (err) 446 break; 447 } 448 449out: 450 if (timeout == 0) { 451 while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) { 452 if (timeout++ > 100) 453 break; 454 DELAY(1000); 455 } 456 } 457 /* Put the controller in master mode again. */ 458 if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0) 459 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 460 461 sc->sc_buffer = NULL; 462 sc->sc_bus_inuse = 0; 463 464 /* Wake up the processes that are waiting for the bus. */ 465 wakeup(sc); 466 467 TI_I2C_UNLOCK(sc); 468 469 return (err); 470} 471 472static int 473ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed) 474{ 475 int timeout; 476 struct ti_i2c_clock_config *clkcfg; 477 u_int busfreq; 478 uint16_t fifo_trsh, reg, scll, sclh; 479 480 switch (ti_chip()) { 481#ifdef SOC_OMAP4 482 case CHIP_OMAP_4: 483 clkcfg = ti_omap4_i2c_clock_configs; 484 break; 485#endif 486#ifdef SOC_TI_AM335X 487 case CHIP_AM335X: 488 clkcfg = ti_am335x_i2c_clock_configs; 489 break; 490#endif 491 default: 492 panic("Unknown TI SoC, unable to reset the i2c"); 493 } 494 495 /* 496 * If we haven't attached the bus yet, just init at the default slow 497 * speed. This lets us get the hardware initialized enough to attach 498 * the bus which is where the real speed configuration is handled. After 499 * the bus is attached, get the configured speed from it. Search the 500 * configuration table for the best speed we can do that doesn't exceed 501 * the requested speed. 502 */ 503 if (sc->sc_iicbus == NULL) 504 busfreq = 100000; 505 else 506 busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed); 507 for (;;) { 508 if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq) 509 break; 510 clkcfg++; 511 } 512 513 /* 514 * 23.1.4.3 - HS I2C Software Reset 515 * From OMAP4 TRM at page 4068. 516 * 517 * 1. Ensure that the module is disabled. 518 */ 519 sc->sc_con_reg = 0; 520 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 521 522 /* 2. Issue a softreset to the controller. */ 523 bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST); 524 525 /* 526 * 3. Enable the module. 527 * The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module 528 * is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1. 529 */ 530 ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN); 531 532 /* 4. Wait for the software reset to complete. */ 533 timeout = 0; 534 while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) { 535 if (timeout++ > 100) 536 return (EBUSY); 537 DELAY(100); 538 } 539 540 /* 541 * Disable the I2C controller once again, now that the reset has 542 * finished. 543 */ 544 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 545 546 /* 547 * The following sequence is taken from the OMAP4 TRM at page 4077. 548 * 549 * 1. Enable the functional and interface clocks (see Section 550 * 23.1.5.1.1.1.1). Done at ti_i2c_activate(). 551 * 552 * 2. Program the prescaler to obtain an approximately 12MHz internal 553 * sampling clock (I2Ci_INTERNAL_CLK) by programming the 554 * corresponding value in the I2Ci.I2C_PSC[3:0] PSC field. 555 * This value depends on the frequency of the functional clock 556 * (I2Ci_FCLK). Because this frequency is 96MHz, the 557 * I2Ci.I2C_PSC[7:0] PSC field value is 0x7. 558 */ 559 ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc); 560 561 /* 562 * 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH 563 * bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps. 564 * These values depend on the internal sampling clock frequency 565 * (see Table 23-8). 566 */ 567 scll = clkcfg->scll & I2C_SCLL_MASK; 568 sclh = clkcfg->sclh & I2C_SCLH_MASK; 569 570 /* 571 * 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and 572 * I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of 573 * 400K bps or 3.4M bps (for the second phase of HS mode). These 574 * values depend on the internal sampling clock frequency (see 575 * Table 23-8). 576 * 577 * 5. (Optional) If a bit rate of 3.4M bps is used and the bus line 578 * capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional 579 * Multiplexing and Configuration). 580 */ 581 switch (ti_chip()) { 582#ifdef SOC_OMAP4 583 case CHIP_OMAP_4: 584 if ((clkcfg->hsscll + clkcfg->hssclh) > 0) { 585 scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT; 586 sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT; 587 sc->sc_con_reg |= I2C_CON_OPMODE_HS; 588 } 589 break; 590#endif 591 } 592 593 /* Write the selected bit rate. */ 594 ti_i2c_write_2(sc, I2C_REG_SCLL, scll); 595 ti_i2c_write_2(sc, I2C_REG_SCLH, sclh); 596 597 /* 598 * 6. Configure the Own Address of the I2C controller by storing it in 599 * the I2Ci.I2C_OA0 register. Up to four Own Addresses can be 600 * programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3) 601 * for each I2C controller. 602 * 603 * Note: For a 10-bit address, set the corresponding expand Own Address 604 * bit in the I2Ci.I2C_CON register. 605 * 606 * Driver currently always in single master mode so ignore this step. 607 */ 608 609 /* 610 * 7. Set the TX threshold (in transmitter mode) and the RX threshold 611 * (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to 612 * (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX 613 * threshold - 1), where the TX and RX thresholds are greater than 614 * or equal to 1. 615 * 616 * The threshold is set to 5 for now. 617 */ 618 fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK; 619 reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT); 620 ti_i2c_write_2(sc, I2C_REG_BUF, reg); 621 622 /* 623 * 8. Take the I2C controller out of reset by setting the 624 * I2Ci.I2C_CON[15] I2C_EN bit to 1. 625 * 626 * 23.1.5.1.1.1.2 - Initialize the I2C Controller 627 * 628 * To initialize the I2C controller, perform the following steps: 629 * 630 * 1. Configure the I2Ci.I2C_CON register: 631 * . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit 632 * (0: slave, 1: master). 633 * . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX 634 * bit (0: receiver, 1: transmitter). 635 */ 636 637 /* Enable the I2C controller in master mode. */ 638 sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST; 639 ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg); 640 641 /* 642 * 2. If using an interrupt to transmit/receive data, set the 643 * corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4] 644 * XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY 645 * bit for the receive interrupt). 646 */ 647 648 /* Set the interrupts we want to be notified. */ 649 reg = I2C_IE_XDR | /* Transmit draining interrupt. */ 650 I2C_IE_XRDY | /* Transmit Data Ready interrupt. */ 651 I2C_IE_RDR | /* Receive draining interrupt. */ 652 I2C_IE_RRDY | /* Receive Data Ready interrupt. */ 653 I2C_IE_ARDY | /* Register Access Ready interrupt. */ 654 I2C_IE_NACK | /* No Acknowledgment interrupt. */ 655 I2C_IE_AL; /* Arbitration lost interrupt. */ 656 657 /* Enable the interrupts. */ 658 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg); 659 660 /* 661 * 3. If using DMA to receive/transmit data, set to 1 the corresponding 662 * bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN 663 * bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit 664 * for the transmit DMA channel). 665 * 666 * Not using DMA for now, so ignore this. 667 */ 668 669 return (0); 670} 671 672static int 673ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr) 674{ 675 struct ti_i2c_softc *sc; 676 int err; 677 678 sc = device_get_softc(dev); 679 TI_I2C_LOCK(sc); 680 err = ti_i2c_reset(sc, speed); 681 TI_I2C_UNLOCK(sc); 682 if (err) 683 return (err); 684 685 return (IIC_ENOADDR); 686} 687 688static int 689ti_i2c_activate(device_t dev) 690{ 691 int err; 692 struct ti_i2c_softc *sc; 693 694 sc = (struct ti_i2c_softc*)device_get_softc(dev); 695 696 /* 697 * 1. Enable the functional and interface clocks (see Section 698 * 23.1.5.1.1.1.1). 699 */ 700 err = ti_sysc_clock_enable(device_get_parent(dev)); 701 if (err) 702 return (err); 703 704 return (ti_i2c_reset(sc, IIC_UNKNOWN)); 705} 706 707/** 708 * ti_i2c_deactivate - deactivates the controller and releases resources 709 * @dev: i2c device handle 710 * 711 * 712 * 713 * LOCKING: 714 * Assumed called in an atomic context. 715 * 716 * RETURNS: 717 * nothing 718 */ 719static void 720ti_i2c_deactivate(device_t dev) 721{ 722 struct ti_i2c_softc *sc = device_get_softc(dev); 723 724 /* Disable the controller - cancel all transactions. */ 725 ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff); 726 ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff); 727 ti_i2c_write_2(sc, I2C_REG_CON, 0); 728 729 /* Release the interrupt handler. */ 730 if (sc->sc_irq_h != NULL) { 731 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h); 732 sc->sc_irq_h = NULL; 733 } 734 735 /* Unmap the I2C controller registers. */ 736 if (sc->sc_mem_res != NULL) { 737 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 738 sc->sc_mem_res = NULL; 739 } 740 741 /* Release the IRQ resource. */ 742 if (sc->sc_irq_res != NULL) { 743 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res); 744 sc->sc_irq_res = NULL; 745 } 746 747 /* Finally disable the functional and interface clocks. */ 748 ti_sysc_clock_disable(device_get_parent(dev)); 749} 750 751static int 752ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS) 753{ 754 int clk, psc, sclh, scll; 755 struct ti_i2c_softc *sc; 756 757 sc = arg1; 758 759 TI_I2C_LOCK(sc); 760 /* Get the system prescaler value. */ 761 psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1; 762 763 /* Get the bitrate. */ 764 scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK; 765 sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK; 766 767 clk = I2C_CLK / psc / (scll + 7 + sclh + 5); 768 TI_I2C_UNLOCK(sc); 769 770 return (sysctl_handle_int(oidp, &clk, 0, req)); 771} 772 773static int 774ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS) 775{ 776 struct ti_i2c_softc *sc; 777 unsigned int val; 778 int err; 779 780 sc = arg1; 781 782 /* 783 * MTX_DEF lock can't be held while doing uimove in 784 * sysctl_handle_int 785 */ 786 TI_I2C_LOCK(sc); 787 val = sc->sc_timeout; 788 TI_I2C_UNLOCK(sc); 789 790 err = sysctl_handle_int(oidp, &val, 0, req); 791 /* Write request? */ 792 if ((err == 0) && (req->newptr != NULL)) { 793 TI_I2C_LOCK(sc); 794 sc->sc_timeout = val; 795 TI_I2C_UNLOCK(sc); 796 } 797 798 return (err); 799} 800 801static int 802ti_i2c_probe(device_t dev) 803{ 804 805 if (!ofw_bus_status_okay(dev)) 806 return (ENXIO); 807 if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c")) 808 return (ENXIO); 809 device_set_desc(dev, "TI I2C Controller"); 810 811 return (0); 812} 813 814static int 815ti_i2c_attach(device_t dev) 816{ 817 int err, rid; 818 struct ti_i2c_softc *sc; 819 struct sysctl_ctx_list *ctx; 820 struct sysctl_oid_list *tree; 821 uint16_t fifosz; 822 823 sc = device_get_softc(dev); 824 sc->sc_dev = dev; 825 826 /* Get the memory resource for the register mapping. */ 827 rid = 0; 828 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 829 RF_ACTIVE); 830 if (sc->sc_mem_res == NULL) { 831 device_printf(dev, "Cannot map registers.\n"); 832 return (ENXIO); 833 } 834 835 /* Allocate our IRQ resource. */ 836 rid = 0; 837 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 838 RF_ACTIVE | RF_SHAREABLE); 839 if (sc->sc_irq_res == NULL) { 840 bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res); 841 device_printf(dev, "Cannot allocate interrupt.\n"); 842 return (ENXIO); 843 } 844 845 TI_I2C_LOCK_INIT(sc); 846 847 /* First of all, we _must_ activate the H/W. */ 848 err = ti_i2c_activate(dev); 849 if (err) { 850 device_printf(dev, "ti_i2c_activate failed\n"); 851 goto out; 852 } 853 854 /* Read the version number of the I2C module */ 855 sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff; 856 857 /* Get the fifo size. */ 858 fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT); 859 fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT; 860 fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK; 861 862 device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n", 863 sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz); 864 865 /* Set the FIFO threshold to 5 for now. */ 866 sc->sc_fifo_trsh = 5; 867 868 /* Set I2C bus timeout */ 869 sc->sc_timeout = 5*hz; 870 871 ctx = device_get_sysctl_ctx(dev); 872 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 873 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock", 874 CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0, 875 ti_i2c_sysctl_clk, "IU", "I2C bus clock"); 876 877 SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout", 878 CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0, 879 ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)"); 880 881 /* Activate the interrupt. */ 882 err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 883 NULL, ti_i2c_intr, sc, &sc->sc_irq_h); 884 if (err) 885 goto out; 886 887 /* Attach the iicbus. */ 888 if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) { 889 device_printf(dev, "could not allocate iicbus instance\n"); 890 err = ENXIO; 891 goto out; 892 } 893 894 /* Probe and attach the iicbus when interrupts are available. */ 895 err = bus_delayed_attach_children(dev); 896 897out: 898 if (err) { 899 ti_i2c_deactivate(dev); 900 TI_I2C_LOCK_DESTROY(sc); 901 } 902 903 return (err); 904} 905 906static int 907ti_i2c_detach(device_t dev) 908{ 909 struct ti_i2c_softc *sc; 910 int rv; 911 912 sc = device_get_softc(dev); 913 914 if ((rv = bus_generic_detach(dev)) != 0) { 915 device_printf(dev, "cannot detach child devices\n"); 916 return (rv); 917 } 918 919 if (sc->sc_iicbus && 920 (rv = device_delete_child(dev, sc->sc_iicbus)) != 0) 921 return (rv); 922 923 ti_i2c_deactivate(dev); 924 TI_I2C_LOCK_DESTROY(sc); 925 926 return (0); 927} 928 929static phandle_t 930ti_i2c_get_node(device_t bus, device_t dev) 931{ 932 933 /* Share controller node with iibus device. */ 934 return (ofw_bus_get_node(bus)); 935} 936 937static device_method_t ti_i2c_methods[] = { 938 /* Device interface */ 939 DEVMETHOD(device_probe, ti_i2c_probe), 940 DEVMETHOD(device_attach, ti_i2c_attach), 941 DEVMETHOD(device_detach, ti_i2c_detach), 942 943 /* Bus interface */ 944 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 945 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 946 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 947 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 948 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 949 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 950 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 951 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 952 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 953 954 /* OFW methods */ 955 DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node), 956 957 /* iicbus interface */ 958 DEVMETHOD(iicbus_callback, iicbus_null_callback), 959 DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset), 960 DEVMETHOD(iicbus_transfer, ti_i2c_transfer), 961 962 DEVMETHOD_END 963}; 964 965static driver_t ti_i2c_driver = { 966 "iichb", 967 ti_i2c_methods, 968 sizeof(struct ti_i2c_softc), 969}; 970 971static devclass_t ti_i2c_devclass; 972 973DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, ti_i2c_devclass, 0, 0); 974DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, iicbus_devclass, 0, 0); 975 976MODULE_DEPEND(ti_iic, ti_sysc, 1, 1, 1); 977MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1); 978