1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Rubicon Communications, LLC (Netgate) 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36 37#include <sys/kernel.h> 38#include <sys/module.h> 39#include <sys/rman.h> 40#include <sys/lock.h> 41#include <sys/mutex.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45#include <machine/intr.h> 46 47#include <dev/fdt/simplebus.h> 48 49#include <dev/ofw/ofw_bus.h> 50#include <dev/ofw/ofw_bus_subr.h> 51 52#include <dt-bindings/interrupt-controller/irq.h> 53#include "pic_if.h" 54 55#define ICU_GRP_NSR 0x0 56#define ICU_GRP_SR 0x1 57#define ICU_GRP_SEI 0x4 58#define ICU_GRP_REI 0x5 59 60#define ICU_SETSPI_NSR_AL 0x10 61#define ICU_SETSPI_NSR_AH 0x14 62#define ICU_CLRSPI_NSR_AL 0x18 63#define ICU_CLRSPI_NSR_AH 0x1c 64#define ICU_INT_CFG(x) (0x100 + (x) * 4) 65#define ICU_INT_ENABLE (1 << 24) 66#define ICU_INT_EDGE (1 << 28) 67#define ICU_INT_GROUP_SHIFT 29 68#define ICU_INT_MASK 0x3ff 69 70#define MV_CP110_ICU_MAX_NIRQS 207 71 72struct mv_cp110_icu_softc { 73 device_t dev; 74 device_t parent; 75 struct resource *res; 76 struct intr_map_data_fdt *parent_map_data; 77}; 78 79static struct resource_spec mv_cp110_icu_res_spec[] = { 80 { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE }, 81 { -1, 0 } 82}; 83 84static struct ofw_compat_data compat_data[] = { 85 {"marvell,cp110-icu-nsr", 1}, 86 {"marvell,cp110-icu-sei", 2}, 87 {NULL, 0} 88}; 89 90#define RD4(sc, reg) bus_read_4((sc)->res, (reg)) 91#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val)) 92 93static int 94mv_cp110_icu_probe(device_t dev) 95{ 96 97 if (!ofw_bus_status_okay(dev)) 98 return (ENXIO); 99 100 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 101 return (ENXIO); 102 103 device_set_desc(dev, "Marvell Interrupt Consolidation Unit"); 104 return (BUS_PROBE_DEFAULT); 105} 106 107static int 108mv_cp110_icu_attach(device_t dev) 109{ 110 struct mv_cp110_icu_softc *sc; 111 phandle_t node, msi_parent; 112 113 sc = device_get_softc(dev); 114 sc->dev = dev; 115 node = ofw_bus_get_node(dev); 116 117 if (OF_getencprop(node, "msi-parent", &msi_parent, 118 sizeof(phandle_t)) <= 0) { 119 device_printf(dev, "cannot find msi-parent property\n"); 120 return (ENXIO); 121 } 122 123 if ((sc->parent = OF_device_from_xref(msi_parent)) == NULL) { 124 device_printf(dev, "cannot find msi-parent device\n"); 125 return (ENXIO); 126 } 127 if (bus_alloc_resources(dev, mv_cp110_icu_res_spec, &sc->res) != 0) { 128 device_printf(dev, "cannot allocate resources for device\n"); 129 return (ENXIO); 130 } 131 132 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 133 device_printf(dev, "Cannot register ICU\n"); 134 goto fail; 135 } 136 137 /* Allocate GICP compatible mapping entry (2 cells) */ 138 sc->parent_map_data = (struct intr_map_data_fdt *)intr_alloc_map_data( 139 INTR_MAP_DATA_FDT, sizeof(struct intr_map_data_fdt) + 140 + 3 * sizeof(phandle_t), M_WAITOK | M_ZERO); 141 return (0); 142 143fail: 144 bus_release_resources(dev, mv_cp110_icu_res_spec, &sc->res); 145 return (ENXIO); 146} 147 148static struct intr_map_data * 149mv_cp110_icu_convert_map_data(struct mv_cp110_icu_softc *sc, struct intr_map_data *data) 150{ 151 struct intr_map_data_fdt *daf; 152 uint32_t reg, irq_no, irq_type; 153 154 daf = (struct intr_map_data_fdt *)data; 155 if (daf->ncells != 2) 156 return (NULL); 157 irq_no = daf->cells[0]; 158 irq_type = daf->cells[1]; 159 if (irq_no >= MV_CP110_ICU_MAX_NIRQS) 160 return (NULL); 161 if (irq_type != IRQ_TYPE_LEVEL_HIGH && 162 irq_type != IRQ_TYPE_EDGE_RISING) 163 return (NULL); 164 165 /* We rely on fact that ICU->GIC mapping is preset by bootstrap. */ 166 reg = RD4(sc, ICU_INT_CFG(irq_no)); 167 168 /* Construct GICP compatible mapping. */ 169 sc->parent_map_data->ncells = 2; 170 sc->parent_map_data->cells[0] = reg & ICU_INT_MASK; 171 sc->parent_map_data->cells[1] = irq_type; 172 173 return ((struct intr_map_data *)sc->parent_map_data); 174} 175 176static int 177mv_cp110_icu_detach(device_t dev) 178{ 179 180 return (EBUSY); 181} 182 183static int 184mv_cp110_icu_activate_intr(device_t dev, struct intr_irqsrc *isrc, 185 struct resource *res, struct intr_map_data *data) 186{ 187 struct mv_cp110_icu_softc *sc; 188 189 sc = device_get_softc(dev); 190 data = mv_cp110_icu_convert_map_data(sc, data); 191 if (data == NULL) 192 return (EINVAL); 193 return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data)); 194} 195 196static void 197mv_cp110_icu_enable_intr(device_t dev, struct intr_irqsrc *isrc) 198{ 199 struct mv_cp110_icu_softc *sc; 200 sc = device_get_softc(dev); 201 202 PIC_ENABLE_INTR(sc->parent, isrc); 203} 204 205static void 206mv_cp110_icu_disable_intr(device_t dev, struct intr_irqsrc *isrc) 207{ 208 struct mv_cp110_icu_softc *sc; 209 210 sc = device_get_softc(dev); 211 212 PIC_DISABLE_INTR(sc->parent, isrc); 213} 214 215static int 216mv_cp110_icu_map_intr(device_t dev, struct intr_map_data *data, 217 struct intr_irqsrc **isrcp) 218{ 219 struct mv_cp110_icu_softc *sc; 220 struct intr_map_data_fdt *daf; 221 uint32_t reg, irq_no, irq_type; 222 int ret; 223 224 sc = device_get_softc(dev); 225 226 if (data->type != INTR_MAP_DATA_FDT) 227 return (ENOTSUP); 228 229 /* Parse original */ 230 daf = (struct intr_map_data_fdt *)data; 231 if (daf->ncells != 2) 232 return (EINVAL); 233 irq_no = daf->cells[0]; 234 irq_type = daf->cells[1]; 235 data = mv_cp110_icu_convert_map_data(sc, data); 236 if (data == NULL) 237 return (EINVAL); 238 239 reg = RD4(sc, ICU_INT_CFG(irq_no)); 240 reg |= ICU_INT_ENABLE; 241 if (irq_type == IRQ_TYPE_LEVEL_HIGH) 242 reg &= ~ICU_INT_EDGE; 243 else 244 reg |= ICU_INT_EDGE; 245 WR4(sc, ICU_INT_CFG(irq_no), reg); 246 247 ret = PIC_MAP_INTR(sc->parent, data, isrcp); 248 (*isrcp)->isrc_dev = sc->dev; 249 return (ret); 250} 251 252static int 253mv_cp110_icu_deactivate_intr(device_t dev, struct intr_irqsrc *isrc, 254 struct resource *res, struct intr_map_data *data) 255{ 256 struct mv_cp110_icu_softc *sc; 257 258 sc = device_get_softc(dev); 259 data = mv_cp110_icu_convert_map_data(sc, data); 260 if (data == NULL) 261 return (EINVAL); 262 263 return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data)); 264} 265 266static int 267mv_cp110_icu_setup_intr(device_t dev, struct intr_irqsrc *isrc, 268 struct resource *res, struct intr_map_data *data) 269{ 270 struct mv_cp110_icu_softc *sc; 271 272 sc = device_get_softc(dev); 273 data = mv_cp110_icu_convert_map_data(sc, data); 274 if (data == NULL) 275 return (EINVAL); 276 277 return (PIC_SETUP_INTR(sc->parent, isrc, res, data)); 278} 279 280static int 281mv_cp110_icu_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 282 struct resource *res, struct intr_map_data *data) 283{ 284 struct mv_cp110_icu_softc *sc; 285 286 sc = device_get_softc(dev); 287 data = mv_cp110_icu_convert_map_data(sc, data); 288 if (data == NULL) 289 return (EINVAL); 290 291 return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data)); 292} 293 294static void 295mv_cp110_icu_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 296{ 297 struct mv_cp110_icu_softc *sc; 298 299 sc = device_get_softc(dev); 300 301 PIC_PRE_ITHREAD(sc->parent, isrc); 302} 303 304static void 305mv_cp110_icu_post_ithread(device_t dev, struct intr_irqsrc *isrc) 306{ 307 struct mv_cp110_icu_softc *sc; 308 309 sc = device_get_softc(dev); 310 311 PIC_POST_ITHREAD(sc->parent, isrc); 312} 313 314static void 315mv_cp110_icu_post_filter(device_t dev, struct intr_irqsrc *isrc) 316{ 317 struct mv_cp110_icu_softc *sc; 318 319 sc = device_get_softc(dev); 320 321 PIC_POST_FILTER(sc->parent, isrc); 322} 323 324static device_method_t mv_cp110_icu_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, mv_cp110_icu_probe), 327 DEVMETHOD(device_attach, mv_cp110_icu_attach), 328 DEVMETHOD(device_detach, mv_cp110_icu_detach), 329 330 /* Interrupt controller interface */ 331 DEVMETHOD(pic_activate_intr, mv_cp110_icu_activate_intr), 332 DEVMETHOD(pic_disable_intr, mv_cp110_icu_disable_intr), 333 DEVMETHOD(pic_enable_intr, mv_cp110_icu_enable_intr), 334 DEVMETHOD(pic_map_intr, mv_cp110_icu_map_intr), 335 DEVMETHOD(pic_deactivate_intr, mv_cp110_icu_deactivate_intr), 336 DEVMETHOD(pic_setup_intr, mv_cp110_icu_setup_intr), 337 DEVMETHOD(pic_teardown_intr, mv_cp110_icu_teardown_intr), 338 DEVMETHOD(pic_post_filter, mv_cp110_icu_post_filter), 339 DEVMETHOD(pic_post_ithread, mv_cp110_icu_post_ithread), 340 DEVMETHOD(pic_pre_ithread, mv_cp110_icu_pre_ithread), 341 342 DEVMETHOD_END 343}; 344 345static devclass_t mv_cp110_icu_devclass; 346 347static driver_t mv_cp110_icu_driver = { 348 "mv_cp110_icu", 349 mv_cp110_icu_methods, 350 sizeof(struct mv_cp110_icu_softc), 351}; 352 353EARLY_DRIVER_MODULE(mv_cp110_icu, mv_cp110_icu_bus, mv_cp110_icu_driver, 354 mv_cp110_icu_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LAST); 355