1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2011 Semihalf.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/bus.h>
34#include <sys/lock.h>
35#include <sys/mutex.h>
36#include <sys/smp.h>
37
38#include <vm/vm.h>
39#include <vm/vm_kern.h>
40#include <vm/vm_extern.h>
41#include <vm/pmap.h>
42
43#include <dev/fdt/fdt_common.h>
44
45#include <machine/cpu.h>
46#include <machine/smp.h>
47#include <machine/fdt.h>
48#include <machine/armreg.h>
49
50#include <arm/mv/mvwin.h>
51
52#include <machine/platformvar.h>
53
54#define MV_AXP_CPU_DIVCLK_BASE		(MV_BASE + 0x18700)
55#define CPU_DIVCLK_CTRL0		0x00
56#define CPU_DIVCLK_CTRL2_RATIO_FULL0	0x08
57#define CPU_DIVCLK_CTRL2_RATIO_FULL1	0x0c
58#define CPU_DIVCLK_MASK(x)		(~(0xff << (8 * (x))))
59
60#define CPU_PMU(x)			(MV_BASE + 0x22100 + (0x100 * (x)))
61#define CPU_PMU_BOOT			0x24
62
63#define MP				(MV_BASE + 0x20800)
64#define MP_SW_RESET(x)			((x) * 8)
65
66#define CPU_RESUME_CONTROL		(0x20988)
67
68void armadaxp_init_coher_fabric(void);
69int platform_get_ncpus(void);
70
71void mv_axp_platform_mp_setmaxid(platform_t plat);
72void mv_axp_platform_mp_start_ap(platform_t plat);
73
74/* Coherency Fabric registers */
75static uint32_t
76read_cpu_clkdiv(uint32_t reg)
77{
78
79	return (bus_space_read_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg));
80}
81
82static void
83write_cpu_clkdiv(uint32_t reg, uint32_t val)
84{
85
86	bus_space_write_4(fdtbus_bs_tag, MV_AXP_CPU_DIVCLK_BASE, reg, val);
87}
88
89void
90mv_axp_platform_mp_setmaxid(platform_t plat)
91{
92
93	mp_ncpus = platform_get_ncpus();
94	mp_maxid = mp_ncpus - 1;
95}
96
97void mptramp(void);
98void mptramp_end(void);
99extern vm_offset_t mptramp_pmu_boot;
100
101void
102mv_axp_platform_mp_start_ap(platform_t plat)
103{
104	uint32_t reg, *src, *dst, cpu_num, div_val, cputype;
105	vm_offset_t pmu_boot_off;
106	/*
107	 * Initialization procedure depends on core revision,
108	 * in this step CHIP ID is checked to choose proper procedure
109	 */
110	cputype = cp15_midr_get();
111	cputype &= CPU_ID_CPU_MASK;
112
113	/*
114	 * Set the PA of CPU0 Boot Address Redirect register used in
115	 * mptramp according to the actual SoC registers' base address.
116	 */
117	pmu_boot_off = (CPU_PMU(0) - MV_BASE) + CPU_PMU_BOOT;
118	mptramp_pmu_boot = fdt_immr_pa + pmu_boot_off;
119	dst = pmap_mapdev(0xffff0000, PAGE_SIZE);
120	for (src = (uint32_t *)mptramp; src < (uint32_t *)mptramp_end;
121	    src++, dst++) {
122		*dst = *src;
123	}
124	pmap_unmapdev((vm_offset_t)dst, PAGE_SIZE);
125	if (cputype == CPU_ID_MV88SV584X_V7) {
126		/* Core rev A0 */
127		div_val = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
128		div_val &= 0x3f;
129
130		for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ ) {
131			reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
132			reg &= CPU_DIVCLK_MASK(cpu_num);
133			reg |= div_val << (cpu_num * 8);
134			write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
135		}
136	} else {
137		/* Core rev Z1 */
138		div_val = 0x01;
139
140		if (mp_ncpus > 1) {
141			reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0);
142			reg &= CPU_DIVCLK_MASK(3);
143			reg |= div_val << 24;
144			write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL0, reg);
145		}
146
147		for (cpu_num = 2; cpu_num < mp_ncpus; cpu_num++ ) {
148			reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1);
149			reg &= CPU_DIVCLK_MASK(cpu_num);
150			reg |= div_val << (cpu_num * 8);
151			write_cpu_clkdiv(CPU_DIVCLK_CTRL2_RATIO_FULL1, reg);
152		}
153	}
154
155	reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
156	reg |= ((0x1 << (mp_ncpus - 1)) - 1) << 21;
157	write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
158	reg = read_cpu_clkdiv(CPU_DIVCLK_CTRL0);
159	reg |= 0x01000000;
160	write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
161
162	DELAY(100);
163	reg &= ~(0xf << 21);
164	write_cpu_clkdiv(CPU_DIVCLK_CTRL0, reg);
165	DELAY(100);
166
167	bus_space_write_4(fdtbus_bs_tag, MV_BASE, CPU_RESUME_CONTROL, 0);
168
169	for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
170		bus_space_write_4(fdtbus_bs_tag, CPU_PMU(cpu_num), CPU_PMU_BOOT,
171		    pmap_kextract((vm_offset_t)mpentry));
172
173	dcache_wbinv_poc_all();
174
175	for (cpu_num = 1; cpu_num < mp_ncpus; cpu_num++ )
176		bus_space_write_4(fdtbus_bs_tag, MP, MP_SW_RESET(cpu_num), 0);
177
178	/* XXX: Temporary workaround for hangup after releasing AP's */
179	wmb();
180	DELAY(10);
181
182	armadaxp_init_coher_fabric();
183}
184