1/*-
2 * Copyright (c) 2015 Semihalf.
3 * Copyright (c) 2015 Stormshield.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/smp.h>
34
35#include <machine/smp.h>
36#include <machine/fdt.h>
37#include <machine/intr.h>
38#include <machine/platformvar.h>
39
40#include <dev/ofw/ofw_bus.h>
41#include <dev/ofw/ofw_bus_subr.h>
42
43#include <arm/mv/mvreg.h>
44
45#include "pmsu.h"
46
47static int cpu_reset_deassert(void);
48void mv_a38x_platform_mp_setmaxid(platform_t plate);
49void mv_a38x_platform_mp_start_ap(platform_t plate);
50
51static int
52cpu_reset_deassert(void)
53{
54	bus_space_handle_t vaddr;
55	uint32_t reg;
56	int rv;
57
58	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_CPU_RESET_BASE,
59	    MV_CPU_RESET_REGS_LEN, 0, &vaddr);
60	if (rv != 0)
61		return (rv);
62
63	/* CPU1 is held at reset by default - clear assert bit to release it */
64	reg = bus_space_read_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1));
65	reg &= ~CPU_RESET_ASSERT;
66
67	bus_space_write_4(fdtbus_bs_tag, vaddr, CPU_RESET_OFFSET(1), reg);
68
69	bus_space_unmap(fdtbus_bs_tag, vaddr, MV_CPU_RESET_REGS_LEN);
70
71	return (0);
72}
73
74static int
75platform_cnt_cpus(void)
76{
77	bus_space_handle_t vaddr_scu;
78	phandle_t cpus_node, child;
79	char device_type[16];
80	int fdt_cpu_count = 0;
81	int reg_cpu_count = 0;
82	uint32_t val;
83	int rv;
84
85	cpus_node = OF_finddevice("/cpus");
86	if (cpus_node == -1) {
87		/* Default is one core */
88		mp_ncpus = 1;
89		return (0);
90	}
91
92	/* Get number of 'cpu' nodes from FDT */
93	for (child = OF_child(cpus_node); child != 0; child = OF_peer(child)) {
94		/* Check if child is a CPU */
95		memset(device_type, 0, sizeof(device_type));
96		rv = OF_getprop(child, "device_type", device_type,
97		    sizeof(device_type) - 1);
98		if (rv < 0)
99			continue;
100		if (strcmp(device_type, "cpu") != 0)
101			continue;
102
103		fdt_cpu_count++;
104	}
105
106	/* Get number of CPU cores from SCU register to cross-check with FDT */
107	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
108	    MV_SCU_REGS_LEN, 0, &vaddr_scu);
109	if (rv != 0) {
110		/* Default is one core */
111		mp_ncpus = 1;
112		return (0);
113	}
114
115	val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CONFIG);
116	bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
117        reg_cpu_count = (val & SCU_CFG_REG_NCPU_MASK) + 1;
118
119	/* Set mp_ncpus to number of cpus in FDT unless SOC contains only one */
120	mp_ncpus = min(reg_cpu_count, fdt_cpu_count);
121	/* mp_ncpus must be at least 1 */
122	mp_ncpus = max(1, mp_ncpus);
123
124	return (mp_ncpus);
125}
126
127void
128mv_a38x_platform_mp_setmaxid(platform_t plate)
129{
130
131	/* Armada38x family supports maximum 2 cores */
132	mp_ncpus = platform_cnt_cpus();
133	mp_maxid = mp_ncpus - 1;
134}
135
136void
137mv_a38x_platform_mp_start_ap(platform_t plate)
138{
139	int rv;
140
141	/* Write secondary entry address to PMSU register */
142	rv = pmsu_boot_secondary_cpu();
143	if (rv != 0)
144		return;
145
146	/* Release CPU1 from reset */
147	cpu_reset_deassert();
148}
149