1/*-
2 * Copyright (c) 2015 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27/*
28 * i.MX6 Synchronous Serial Interface (SSI)
29 *
30 * Chapter 61, i.MX 6Dual/6Quad Applications Processor Reference Manual,
31 * Rev. 1, 04/2013
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD$");
36
37#include <sys/param.h>
38#include <sys/systm.h>
39#include <sys/bus.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/malloc.h>
43#include <sys/rman.h>
44#include <sys/timeet.h>
45#include <sys/timetc.h>
46
47#include <dev/sound/pcm/sound.h>
48#include <dev/sound/chip.h>
49#include <mixer_if.h>
50
51#include <dev/ofw/openfirm.h>
52#include <dev/ofw/ofw_bus.h>
53#include <dev/ofw/ofw_bus_subr.h>
54
55#include <machine/bus.h>
56#include <machine/cpu.h>
57#include <machine/intr.h>
58
59#include <arm/freescale/imx/imx6_sdma.h>
60#include <arm/freescale/imx/imx6_anatopvar.h>
61#include <arm/freescale/imx/imx_ccmvar.h>
62
63#define	READ4(_sc, _reg)	\
64	bus_space_read_4(_sc->bst, _sc->bsh, _reg)
65#define	WRITE4(_sc, _reg, _val)	\
66	bus_space_write_4(_sc->bst, _sc->bsh, _reg, _val)
67
68#define	SSI_NCHANNELS	1
69#define	DMAS_TOTAL	8
70
71/* i.MX6 SSI registers */
72
73#define	SSI_STX0	0x00 /* Transmit Data Register n */
74#define	SSI_STX1	0x04 /* Transmit Data Register n */
75#define	SSI_SRX0	0x08 /* Receive Data Register n */
76#define	SSI_SRX1	0x0C /* Receive Data Register n */
77#define	SSI_SCR		0x10 /* Control Register */
78#define	 SCR_I2S_MODE_S	5    /* I2S Mode Select. */
79#define	 SCR_I2S_MODE_M	0x3
80#define	 SCR_SYN	(1 << 4)
81#define	 SCR_NET       	(1 << 3)  /* Network mode */
82#define	 SCR_RE		(1 << 2)  /* Receive Enable. */
83#define	 SCR_TE		(1 << 1)  /* Transmit Enable. */
84#define	 SCR_SSIEN	(1 << 0)  /* SSI Enable */
85#define	SSI_SISR	0x14      /* Interrupt Status Register */
86#define	SSI_SIER	0x18      /* Interrupt Enable Register */
87#define	 SIER_RDMAE	(1 << 22) /* Receive DMA Enable. */
88#define	 SIER_RIE	(1 << 21) /* Receive Interrupt Enable. */
89#define	 SIER_TDMAE	(1 << 20) /* Transmit DMA Enable. */
90#define	 SIER_TIE	(1 << 19) /* Transmit Interrupt Enable. */
91#define	 SIER_TDE0IE	(1 << 12) /* Transmit Data Register Empty 0. */
92#define	 SIER_TUE0IE	(1 << 8)  /* Transmitter Underrun Error 0. */
93#define	 SIER_TFE0IE	(1 << 0)  /* Transmit FIFO Empty 0 IE. */
94#define	SSI_STCR	0x1C	  /* Transmit Configuration Register */
95#define	 STCR_TXBIT0	(1 << 9)  /* Transmit Bit 0 shift MSB/LSB */
96#define	 STCR_TFEN1	(1 << 8)  /* Transmit FIFO Enable 1. */
97#define	 STCR_TFEN0	(1 << 7)  /* Transmit FIFO Enable 0. */
98#define	 STCR_TFDIR	(1 << 6)  /* Transmit Frame Direction. */
99#define	 STCR_TXDIR	(1 << 5)  /* Transmit Clock Direction. */
100#define	 STCR_TSHFD	(1 << 4)  /* Transmit Shift Direction. */
101#define	 STCR_TSCKP	(1 << 3)  /* Transmit Clock Polarity. */
102#define	 STCR_TFSI	(1 << 2)  /* Transmit Frame Sync Invert. */
103#define	 STCR_TFSL	(1 << 1)  /* Transmit Frame Sync Length. */
104#define	 STCR_TEFS	(1 << 0)  /* Transmit Early Frame Sync. */
105#define	SSI_SRCR	0x20      /* Receive Configuration Register */
106#define	SSI_STCCR	0x24      /* Transmit Clock Control Register */
107#define	 STCCR_DIV2	(1 << 18) /* Divide By 2. */
108#define	 STCCR_PSR	(1 << 17) /* Divide clock by 8. */
109#define	 WL3_WL0_S	13
110#define	 WL3_WL0_M	0xf
111#define	 DC4_DC0_S	8
112#define	 DC4_DC0_M	0x1f
113#define	 PM7_PM0_S	0
114#define	 PM7_PM0_M	0xff
115#define	SSI_SRCCR	0x28	/* Receive Clock Control Register */
116#define	SSI_SFCSR	0x2C	/* FIFO Control/Status Register */
117#define	 SFCSR_RFWM1_S	20	/* Receive FIFO Empty WaterMark 1 */
118#define	 SFCSR_RFWM1_M	0xf
119#define	 SFCSR_TFWM1_S	16	/* Transmit FIFO Empty WaterMark 1 */
120#define	 SFCSR_TFWM1_M	0xf
121#define	 SFCSR_RFWM0_S	4	/* Receive FIFO Empty WaterMark 0 */
122#define	 SFCSR_RFWM0_M	0xf
123#define	 SFCSR_TFWM0_S	0	/* Transmit FIFO Empty WaterMark 0 */
124#define	 SFCSR_TFWM0_M	0xf
125#define	SSI_SACNT	0x38	/* AC97 Control Register */
126#define	SSI_SACADD	0x3C	/* AC97 Command Address Register */
127#define	SSI_SACDAT	0x40	/* AC97 Command Data Register */
128#define	SSI_SATAG	0x44	/* AC97 Tag Register */
129#define	SSI_STMSK	0x48	/* Transmit Time Slot Mask Register */
130#define	SSI_SRMSK	0x4C	/* Receive Time Slot Mask Register */
131#define	SSI_SACCST	0x50	/* AC97 Channel Status Register */
132#define	SSI_SACCEN	0x54	/* AC97 Channel Enable Register */
133#define	SSI_SACCDIS	0x58	/* AC97 Channel Disable Register */
134
135static MALLOC_DEFINE(M_SSI, "ssi", "ssi audio");
136
137uint32_t ssi_dma_intr(void *arg, int chn);
138
139struct ssi_rate {
140	uint32_t speed;
141	uint32_t mfi; /* PLL4 Multiplication Factor Integer */
142	uint32_t mfn; /* PLL4 Multiplication Factor Numerator */
143	uint32_t mfd; /* PLL4 Multiplication Factor Denominator */
144	/* More dividers to configure can be added here */
145};
146
147static struct ssi_rate rate_map[] = {
148	{ 192000, 49, 152, 1000 }, /* PLL4 49.152 Mhz */
149	/* TODO: add more frequences */
150	{ 0, 0 },
151};
152
153/*
154 *  i.MX6 example bit clock formula
155 *
156 *  BCLK = 2 channels * 192000 hz * 24 bit = 9216000 hz =
157 *     (24000000 * (49 + 152/1000.0) / 4 / 4 / 2 / 2 / 2 / 1 / 1)
158 *             ^     ^     ^      ^    ^   ^   ^   ^   ^   ^   ^
159 *             |     |     |      |    |   |   |   |   |   |   |
160 *  Fref ------/     |     |      |    |   |   |   |   |   |   |
161 *  PLL4 div select -/     |      |    |   |   |   |   |   |   |
162 *  PLL4 num --------------/      |    |   |   |   |   |   |   |
163 *  PLL4 denom -------------------/    |   |   |   |   |   |   |
164 *  PLL4 post div ---------------------/   |   |   |   |   |   |
165 *  CCM ssi pre div (CCM_CS1CDR) ----------/   |   |   |   |   |
166 *  CCM ssi post div (CCM_CS1CDR) -------------/   |   |   |   |
167 *  SSI PM7_PM0_S ---------------------------------/   |   |   |
168 *  SSI Fixed divider ---------------------------------/   |   |
169 *  SSI DIV2 ----------------------------------------------/   |
170 *  SSI PSR (prescaler /1 or /8) ------------------------------/
171 *
172 *  MCLK (Master clock) depends on DAC, usually BCLK * 4
173 */
174
175struct sc_info {
176	struct resource		*res[2];
177	bus_space_tag_t		bst;
178	bus_space_handle_t	bsh;
179	device_t		dev;
180	struct mtx		*lock;
181	void			*ih;
182	int			pos;
183	int			dma_size;
184	bus_dma_tag_t		dma_tag;
185	bus_dmamap_t		dma_map;
186	bus_addr_t		buf_base_phys;
187	uint32_t		*buf_base;
188	struct sdma_conf	*conf;
189	struct ssi_rate		*sr;
190	struct sdma_softc	*sdma_sc;
191	uint32_t		sdma_ev_rx;
192	uint32_t		sdma_ev_tx;
193	int			sdma_channel;
194};
195
196/* Channel registers */
197struct sc_chinfo {
198	struct snd_dbuf		*buffer;
199	struct pcm_channel	*channel;
200	struct sc_pcminfo	*parent;
201
202	/* Channel information */
203	uint32_t	dir;
204	uint32_t	format;
205
206	/* Flags */
207	uint32_t	run;
208};
209
210/* PCM device private data */
211struct sc_pcminfo {
212	device_t		dev;
213	uint32_t		(*ih)(struct sc_pcminfo *scp);
214	uint32_t		chnum;
215	struct sc_chinfo	chan[SSI_NCHANNELS];
216	struct sc_info		*sc;
217};
218
219static struct resource_spec ssi_spec[] = {
220	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
221	{ SYS_RES_IRQ,		0,	RF_ACTIVE },
222	{ -1, 0 }
223};
224
225static int setup_dma(struct sc_pcminfo *scp);
226static void setup_ssi(struct sc_info *);
227static void ssi_configure_clock(struct sc_info *);
228
229/*
230 * Mixer interface.
231 */
232
233static int
234ssimixer_init(struct snd_mixer *m)
235{
236	struct sc_pcminfo *scp;
237	struct sc_info *sc;
238	int mask;
239
240	scp = mix_getdevinfo(m);
241	sc = scp->sc;
242
243	if (sc == NULL)
244		return -1;
245
246	mask = SOUND_MASK_PCM;
247	mask |= SOUND_MASK_VOLUME;
248
249	snd_mtxlock(sc->lock);
250	pcm_setflags(scp->dev, pcm_getflags(scp->dev) | SD_F_SOFTPCMVOL);
251	mix_setdevs(m, mask);
252	snd_mtxunlock(sc->lock);
253
254	return (0);
255}
256
257static int
258ssimixer_set(struct snd_mixer *m, unsigned dev,
259    unsigned left, unsigned right)
260{
261	struct sc_pcminfo *scp;
262
263	scp = mix_getdevinfo(m);
264
265	/* Here we can configure hardware volume on our DAC */
266
267#if 1
268	device_printf(scp->dev, "ssimixer_set() %d %d\n",
269	    left, right);
270#endif
271
272	return (0);
273}
274
275static kobj_method_t ssimixer_methods[] = {
276	KOBJMETHOD(mixer_init,      ssimixer_init),
277	KOBJMETHOD(mixer_set,       ssimixer_set),
278	KOBJMETHOD_END
279};
280MIXER_DECLARE(ssimixer);
281
282/*
283 * Channel interface.
284 */
285
286static void *
287ssichan_init(kobj_t obj, void *devinfo, struct snd_dbuf *b,
288    struct pcm_channel *c, int dir)
289{
290	struct sc_pcminfo *scp;
291	struct sc_chinfo *ch;
292	struct sc_info *sc;
293
294	scp = (struct sc_pcminfo *)devinfo;
295	sc = scp->sc;
296
297	snd_mtxlock(sc->lock);
298	ch = &scp->chan[0];
299	ch->dir = dir;
300	ch->run = 0;
301	ch->buffer = b;
302	ch->channel = c;
303	ch->parent = scp;
304	snd_mtxunlock(sc->lock);
305
306	if (sndbuf_setup(ch->buffer, sc->buf_base, sc->dma_size) != 0) {
307		device_printf(scp->dev, "Can't setup sndbuf.\n");
308		return NULL;
309	}
310
311	return ch;
312}
313
314static int
315ssichan_free(kobj_t obj, void *data)
316{
317	struct sc_chinfo *ch = data;
318	struct sc_pcminfo *scp = ch->parent;
319	struct sc_info *sc = scp->sc;
320
321#if 0
322	device_printf(scp->dev, "ssichan_free()\n");
323#endif
324
325	snd_mtxlock(sc->lock);
326	/* TODO: free channel buffer */
327	snd_mtxunlock(sc->lock);
328
329	return (0);
330}
331
332static int
333ssichan_setformat(kobj_t obj, void *data, uint32_t format)
334{
335	struct sc_chinfo *ch = data;
336
337	ch->format = format;
338
339	return (0);
340}
341
342static uint32_t
343ssichan_setspeed(kobj_t obj, void *data, uint32_t speed)
344{
345	struct sc_pcminfo *scp;
346	struct sc_chinfo *ch;
347	struct ssi_rate *sr;
348	struct sc_info *sc;
349	int threshold;
350	int i;
351
352	ch = data;
353	scp = ch->parent;
354	sc = scp->sc;
355
356	sr = NULL;
357
358	/* First look for equal frequency. */
359	for (i = 0; rate_map[i].speed != 0; i++) {
360		if (rate_map[i].speed == speed)
361			sr = &rate_map[i];
362	}
363
364	/* If no match, just find nearest. */
365	if (sr == NULL) {
366		for (i = 0; rate_map[i].speed != 0; i++) {
367			sr = &rate_map[i];
368			threshold = sr->speed + ((rate_map[i + 1].speed != 0) ?
369			    ((rate_map[i + 1].speed - sr->speed) >> 1) : 0);
370			if (speed < threshold)
371				break;
372		}
373	}
374
375	sc->sr = sr;
376
377	ssi_configure_clock(sc);
378
379	return (sr->speed);
380}
381
382static void
383ssi_configure_clock(struct sc_info *sc)
384{
385	struct ssi_rate *sr;
386
387	sr = sc->sr;
388
389	pll4_configure_output(sr->mfi, sr->mfn, sr->mfd);
390
391	/* Configure other dividers here, if any */
392}
393
394static uint32_t
395ssichan_setblocksize(kobj_t obj, void *data, uint32_t blocksize)
396{
397	struct sc_chinfo *ch = data;
398	struct sc_pcminfo *scp = ch->parent;
399	struct sc_info *sc = scp->sc;
400
401	sndbuf_resize(ch->buffer, sc->dma_size / blocksize, blocksize);
402
403	setup_dma(scp);
404
405	return (sndbuf_getblksz(ch->buffer));
406}
407
408uint32_t
409ssi_dma_intr(void *arg, int chn)
410{
411	struct sc_pcminfo *scp;
412	struct sdma_conf *conf;
413	struct sc_chinfo *ch;
414	struct sc_info *sc;
415	int bufsize;
416
417	scp = arg;
418	ch = &scp->chan[0];
419	sc = scp->sc;
420	conf = sc->conf;
421
422	bufsize = sndbuf_getsize(ch->buffer);
423
424	sc->pos += conf->period;
425	if (sc->pos >= bufsize)
426		sc->pos -= bufsize;
427
428	if (ch->run)
429		chn_intr(ch->channel);
430
431	return (0);
432}
433
434static int
435find_sdma_controller(struct sc_info *sc)
436{
437	struct sdma_softc *sdma_sc;
438	phandle_t node, sdma_node;
439	device_t sdma_dev;
440	pcell_t dts_value[DMAS_TOTAL];
441	int len;
442
443	if ((node = ofw_bus_get_node(sc->dev)) == -1)
444		return (ENXIO);
445
446	if ((len = OF_getproplen(node, "dmas")) <= 0)
447		return (ENXIO);
448
449	if (len != sizeof(dts_value)) {
450		device_printf(sc->dev,
451		    "\"dmas\" property length is invalid: %d (expected %d)",
452		    len, sizeof(dts_value));
453		return (ENXIO);
454	}
455
456	OF_getencprop(node, "dmas", dts_value, sizeof(dts_value));
457
458	sc->sdma_ev_rx = dts_value[1];
459	sc->sdma_ev_tx = dts_value[5];
460
461	sdma_node = OF_node_from_xref(dts_value[0]);
462
463	sdma_sc = NULL;
464
465	sdma_dev = devclass_get_device(devclass_find("sdma"), 0);
466	if (sdma_dev)
467		sdma_sc = device_get_softc(sdma_dev);
468
469	if (sdma_sc == NULL) {
470		device_printf(sc->dev, "No sDMA found. Can't operate\n");
471		return (ENXIO);
472	}
473
474	sc->sdma_sc = sdma_sc;
475
476	return (0);
477};
478
479static int
480setup_dma(struct sc_pcminfo *scp)
481{
482	struct sdma_conf *conf;
483	struct sc_chinfo *ch;
484	struct sc_info *sc;
485	int fmt;
486
487	ch = &scp->chan[0];
488	sc = scp->sc;
489	conf = sc->conf;
490
491	conf->ih = ssi_dma_intr;
492	conf->ih_user = scp;
493	conf->saddr = sc->buf_base_phys;
494	conf->daddr = rman_get_start(sc->res[0]) + SSI_STX0;
495	conf->event = sc->sdma_ev_tx; /* SDMA TX event */
496	conf->period = sndbuf_getblksz(ch->buffer);
497	conf->num_bd = sndbuf_getblkcnt(ch->buffer);
498
499	/*
500	 * Word Length
501	 * Can be 32, 24, 16 or 8 for sDMA.
502	 *
503	 * SSI supports 24 at max.
504	 */
505
506	fmt = sndbuf_getfmt(ch->buffer);
507
508	if (fmt & AFMT_16BIT) {
509		conf->word_length = 16;
510		conf->command = CMD_2BYTES;
511	} else if (fmt & AFMT_24BIT) {
512		conf->word_length = 24;
513		conf->command = CMD_3BYTES;
514	} else {
515		device_printf(sc->dev, "Unknown format\n");
516		return (-1);
517	}
518
519	return (0);
520}
521
522static int
523ssi_start(struct sc_pcminfo *scp)
524{
525	struct sc_info *sc;
526	int reg;
527
528	sc = scp->sc;
529
530	if (sdma_configure(sc->sdma_channel, sc->conf) != 0) {
531		device_printf(sc->dev, "Can't configure sDMA\n");
532		return (-1);
533	}
534
535	/* Enable DMA interrupt */
536	reg = (SIER_TDMAE);
537	WRITE4(sc, SSI_SIER, reg);
538
539	sdma_start(sc->sdma_channel);
540
541	return (0);
542}
543
544static int
545ssi_stop(struct sc_pcminfo *scp)
546{
547	struct sc_info *sc;
548	int reg;
549
550	sc = scp->sc;
551
552	reg = READ4(sc, SSI_SIER);
553	reg &= ~(SIER_TDMAE);
554	WRITE4(sc, SSI_SIER, reg);
555
556	sdma_stop(sc->sdma_channel);
557
558	bzero(sc->buf_base, sc->dma_size);
559
560	return (0);
561}
562
563static int
564ssichan_trigger(kobj_t obj, void *data, int go)
565{
566	struct sc_pcminfo *scp;
567	struct sc_chinfo *ch;
568	struct sc_info *sc;
569
570	ch = data;
571	scp = ch->parent;
572	sc = scp->sc;
573
574	snd_mtxlock(sc->lock);
575
576	switch (go) {
577	case PCMTRIG_START:
578#if 0
579		device_printf(scp->dev, "trigger start\n");
580#endif
581		ch->run = 1;
582
583		ssi_start(scp);
584
585		break;
586
587	case PCMTRIG_STOP:
588	case PCMTRIG_ABORT:
589#if 0
590		device_printf(scp->dev, "trigger stop or abort\n");
591#endif
592		ch->run = 0;
593
594		ssi_stop(scp);
595
596		break;
597	}
598
599	snd_mtxunlock(sc->lock);
600
601	return (0);
602}
603
604static uint32_t
605ssichan_getptr(kobj_t obj, void *data)
606{
607	struct sc_pcminfo *scp;
608	struct sc_chinfo *ch;
609	struct sc_info *sc;
610
611	ch = data;
612	scp = ch->parent;
613	sc = scp->sc;
614
615	return (sc->pos);
616}
617
618static uint32_t ssi_pfmt[] = {
619	SND_FORMAT(AFMT_S24_LE, 2, 0),
620	0
621};
622
623static struct pcmchan_caps ssi_pcaps = {44100, 192000, ssi_pfmt, 0};
624
625static struct pcmchan_caps *
626ssichan_getcaps(kobj_t obj, void *data)
627{
628
629	return (&ssi_pcaps);
630}
631
632static kobj_method_t ssichan_methods[] = {
633	KOBJMETHOD(channel_init,         ssichan_init),
634	KOBJMETHOD(channel_free,         ssichan_free),
635	KOBJMETHOD(channel_setformat,    ssichan_setformat),
636	KOBJMETHOD(channel_setspeed,     ssichan_setspeed),
637	KOBJMETHOD(channel_setblocksize, ssichan_setblocksize),
638	KOBJMETHOD(channel_trigger,      ssichan_trigger),
639	KOBJMETHOD(channel_getptr,       ssichan_getptr),
640	KOBJMETHOD(channel_getcaps,      ssichan_getcaps),
641	KOBJMETHOD_END
642};
643CHANNEL_DECLARE(ssichan);
644
645static int
646ssi_probe(device_t dev)
647{
648
649	if (!ofw_bus_status_okay(dev))
650		return (ENXIO);
651
652	if (!ofw_bus_is_compatible(dev, "fsl,imx6q-ssi"))
653		return (ENXIO);
654
655	device_set_desc(dev, "i.MX6 Synchronous Serial Interface (SSI)");
656	return (BUS_PROBE_DEFAULT);
657}
658
659static void
660ssi_intr(void *arg)
661{
662	struct sc_pcminfo *scp;
663	struct sc_chinfo *ch;
664	struct sc_info *sc;
665
666	scp = arg;
667	sc = scp->sc;
668	ch = &scp->chan[0];
669
670	/* We don't use SSI interrupt */
671#if 0
672	device_printf(sc->dev, "SSI Intr 0x%08x\n",
673	    READ4(sc, SSI_SISR));
674#endif
675}
676
677static void
678setup_ssi(struct sc_info *sc)
679{
680	int reg;
681
682	reg = READ4(sc, SSI_STCCR);
683	reg &= ~(WL3_WL0_M << WL3_WL0_S);
684	reg |= (0xb << WL3_WL0_S); /* 24 bit */
685	reg &= ~(DC4_DC0_M << DC4_DC0_S);
686	reg |= (1 << DC4_DC0_S); /* 2 words per frame */
687	reg &= ~(STCCR_DIV2); /* Divide by 1 */
688	reg &= ~(STCCR_PSR); /* Divide by 1 */
689	reg &= ~(PM7_PM0_M << PM7_PM0_S);
690	reg |= (1 << PM7_PM0_S); /* Divide by 2 */
691	WRITE4(sc, SSI_STCCR, reg);
692
693	reg = READ4(sc, SSI_SFCSR);
694	reg &= ~(SFCSR_TFWM0_M << SFCSR_TFWM0_S);
695	reg |= (8 << SFCSR_TFWM0_S); /* empty slots */
696	WRITE4(sc, SSI_SFCSR, reg);
697
698	reg = READ4(sc, SSI_STCR);
699	reg |= (STCR_TFEN0);
700	reg &= ~(STCR_TFEN1);
701	reg &= ~(STCR_TSHFD); /* MSB */
702	reg |= (STCR_TXBIT0);
703	reg |= (STCR_TXDIR | STCR_TFDIR);
704	reg |= (STCR_TSCKP); /* falling edge */
705	reg |= (STCR_TFSI);
706	reg &= ~(STCR_TFSI); /* active high frame sync */
707	reg &= ~(STCR_TFSL);
708	reg |= STCR_TEFS;
709	WRITE4(sc, SSI_STCR, reg);
710
711	reg = READ4(sc, SSI_SCR);
712	reg &= ~(SCR_I2S_MODE_M << SCR_I2S_MODE_S); /* Not master */
713	reg |= (SCR_SSIEN | SCR_TE);
714	reg |= (SCR_NET);
715	reg |= (SCR_SYN);
716	WRITE4(sc, SSI_SCR, reg);
717}
718
719static void
720ssi_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
721{
722	bus_addr_t *addr;
723
724	if (err)
725		return;
726
727	addr = (bus_addr_t*)arg;
728	*addr = segs[0].ds_addr;
729}
730
731static int
732ssi_attach(device_t dev)
733{
734	char status[SND_STATUSLEN];
735	struct sc_pcminfo *scp;
736	struct sc_info *sc;
737	int err;
738
739	sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
740	sc->dev = dev;
741	sc->sr = &rate_map[0];
742	sc->pos = 0;
743	sc->conf = malloc(sizeof(struct sdma_conf), M_DEVBUF, M_WAITOK | M_ZERO);
744
745	sc->lock = snd_mtxcreate(device_get_nameunit(dev), "ssi softc");
746	if (sc->lock == NULL) {
747		device_printf(dev, "Can't create mtx\n");
748		return (ENXIO);
749	}
750
751	if (bus_alloc_resources(dev, ssi_spec, sc->res)) {
752		device_printf(dev, "could not allocate resources\n");
753		return (ENXIO);
754	}
755
756	/* Memory interface */
757	sc->bst = rman_get_bustag(sc->res[0]);
758	sc->bsh = rman_get_bushandle(sc->res[0]);
759
760	/* SDMA */
761	if (find_sdma_controller(sc)) {
762		device_printf(dev, "could not find active SDMA\n");
763		return (ENXIO);
764	}
765
766	/* Setup PCM */
767	scp = malloc(sizeof(struct sc_pcminfo), M_DEVBUF, M_NOWAIT | M_ZERO);
768	scp->sc = sc;
769	scp->dev = dev;
770
771	/*
772	 * Maximum possible DMA buffer.
773	 * Will be used partially to match 24 bit word.
774	 */
775	sc->dma_size = 131072;
776
777	/*
778	 * Must use dma_size boundary as modulo feature required.
779	 * Modulo feature allows setup circular buffer.
780	 */
781
782	err = bus_dma_tag_create(
783	    bus_get_dma_tag(sc->dev),
784	    4, sc->dma_size,		/* alignment, boundary */
785	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
786	    BUS_SPACE_MAXADDR,		/* highaddr */
787	    NULL, NULL,			/* filter, filterarg */
788	    sc->dma_size, 1,		/* maxsize, nsegments */
789	    sc->dma_size, 0,		/* maxsegsize, flags */
790	    NULL, NULL,			/* lockfunc, lockarg */
791	    &sc->dma_tag);
792
793	err = bus_dmamem_alloc(sc->dma_tag, (void **)&sc->buf_base,
794	    BUS_DMA_NOWAIT | BUS_DMA_COHERENT, &sc->dma_map);
795	if (err) {
796		device_printf(dev, "cannot allocate framebuffer\n");
797		return (ENXIO);
798	}
799
800	err = bus_dmamap_load(sc->dma_tag, sc->dma_map, sc->buf_base,
801	    sc->dma_size, ssi_dmamap_cb, &sc->buf_base_phys, BUS_DMA_NOWAIT);
802	if (err) {
803		device_printf(dev, "cannot load DMA map\n");
804		return (ENXIO);
805	}
806
807	bzero(sc->buf_base, sc->dma_size);
808
809	/* Setup interrupt handler */
810	err = bus_setup_intr(dev, sc->res[1], INTR_MPSAFE | INTR_TYPE_AV,
811	    NULL, ssi_intr, scp, &sc->ih);
812	if (err) {
813		device_printf(dev, "Unable to alloc interrupt resource.\n");
814		return (ENXIO);
815	}
816
817	pcm_setflags(dev, pcm_getflags(dev) | SD_F_MPSAFE);
818
819	err = pcm_register(dev, scp, 1, 0);
820	if (err) {
821		device_printf(dev, "Can't register pcm.\n");
822		return (ENXIO);
823	}
824
825	scp->chnum = 0;
826	pcm_addchan(dev, PCMDIR_PLAY, &ssichan_class, scp);
827	scp->chnum++;
828
829	snprintf(status, SND_STATUSLEN, "at simplebus");
830	pcm_setstatus(dev, status);
831
832	mixer_init(dev, &ssimixer_class, scp);
833	setup_ssi(sc);
834
835	imx_ccm_ssi_configure(dev);
836
837	sc->sdma_channel = sdma_alloc();
838	if (sc->sdma_channel < 0) {
839		device_printf(sc->dev, "Can't get sDMA channel\n");
840		return (1);
841	}
842
843	return (0);
844}
845
846static device_method_t ssi_pcm_methods[] = {
847	DEVMETHOD(device_probe,		ssi_probe),
848	DEVMETHOD(device_attach,	ssi_attach),
849	{ 0, 0 }
850};
851
852static driver_t ssi_pcm_driver = {
853	"pcm",
854	ssi_pcm_methods,
855	PCM_SOFTC_SIZE,
856};
857
858DRIVER_MODULE(ssi, simplebus, ssi_pcm_driver, pcm_devclass, 0, 0);
859MODULE_DEPEND(ssi, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
860MODULE_DEPEND(ssi, sdma, 0, 0, 0);
861MODULE_VERSION(ssi, 1);
862