1/*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28/* 29 * Allwinner Gigabit Ethernet 30 */ 31 32#ifndef __IF_AWGREG_H__ 33#define __IF_AWGREG_H__ 34 35#define EMAC_BASIC_CTL_0 0x00 36#define BASIC_CTL_SPEED (0x3 << 2) 37#define BASIC_CTL_SPEED_SHIFT 2 38#define BASIC_CTL_SPEED_1000 0 39#define BASIC_CTL_SPEED_10 2 40#define BASIC_CTL_SPEED_100 3 41#define BASIC_CTL_LOOPBACK (1 << 1) 42#define BASIC_CTL_DUPLEX (1 << 0) 43#define EMAC_BASIC_CTL_1 0x04 44#define BASIC_CTL_BURST_LEN (0x3f << 24) 45#define BASIC_CTL_BURST_LEN_SHIFT 24 46#define BASIC_CTL_RX_TX_PRI (1 << 1) 47#define BASIC_CTL_SOFT_RST (1 << 0) 48#define EMAC_INT_STA 0x08 49#define RX_BUF_UA_INT (1 << 10) 50#define RX_INT (1 << 8) 51#define TX_UNDERFLOW_INT (1 << 4) 52#define TX_BUF_UA_INT (1 << 2) 53#define TX_DMA_STOPPED_INT (1 << 1) 54#define TX_INT (1 << 0) 55#define EMAC_INT_EN 0x0c 56#define RX_BUF_UA_INT_EN (1 << 10) 57#define RX_INT_EN (1 << 8) 58#define TX_UNDERFLOW_INT_EN (1 << 4) 59#define TX_BUF_UA_INT_EN (1 << 2) 60#define TX_DMA_STOPPED_INT_EN (1 << 1) 61#define TX_INT_EN (1 << 0) 62#define EMAC_TX_CTL_0 0x10 63#define TX_EN (1 << 31) 64#define EMAC_TX_CTL_1 0x14 65#define TX_DMA_START (1 << 31) 66#define TX_DMA_EN (1 << 30) 67#define TX_NEXT_FRAME (1 << 2) 68#define TX_MD (1 << 1) 69#define FLUSH_TX_FIFO (1 << 0) 70#define EMAC_TX_FLOW_CTL 0x1c 71#define PAUSE_TIME (0xffff << 4) 72#define PAUSE_TIME_SHIFT 4 73#define TX_FLOW_CTL_EN (1 << 0) 74#define EMAC_TX_DMA_LIST 0x20 75#define EMAC_RX_CTL_0 0x24 76#define RX_EN (1 << 31) 77#define JUMBO_FRM_EN (1 << 29) 78#define STRIP_FCS (1 << 28) 79#define CHECK_CRC (1 << 27) 80#define RX_FLOW_CTL_EN (1 << 16) 81#define EMAC_RX_CTL_1 0x28 82#define RX_DMA_START (1 << 31) 83#define RX_DMA_EN (1 << 30) 84#define RX_MD (1 << 1) 85#define EMAC_RX_DMA_LIST 0x34 86#define EMAC_RX_FRM_FLT 0x38 87#define DIS_ADDR_FILTER (1 << 31) 88#define DIS_BROADCAST (1 << 17) 89#define RX_ALL_MULTICAST (1 << 16) 90#define CTL_FRM_FILTER (0x3 << 12) 91#define CTL_FRM_FILTER_SHIFT 12 92#define HASH_MULTICAST (1 << 9) 93#define HASH_UNICAST (1 << 8) 94#define SA_FILTER_EN (1 << 6) 95#define SA_INV_FILTER (1 << 5) 96#define DA_INV_FILTER (1 << 4) 97#define FLT_MD (1 << 1) 98#define RX_ALL (1 << 0) 99#define EMAC_RX_HASH_0 0x40 100#define EMAC_RX_HASH_1 0x44 101#define EMAC_MII_CMD 0x48 102#define MDC_DIV_RATIO_M (0x7 << 20) 103#define MDC_DIV_RATIO_M_16 0 104#define MDC_DIV_RATIO_M_32 1 105#define MDC_DIV_RATIO_M_64 2 106#define MDC_DIV_RATIO_M_128 3 107#define MDC_DIV_RATIO_M_SHIFT 20 108#define PHY_ADDR (0x1f << 12) 109#define PHY_ADDR_SHIFT 12 110#define PHY_REG_ADDR (0x1f << 4) 111#define PHY_REG_ADDR_SHIFT 4 112#define MII_WR (1 << 1) 113#define MII_BUSY (1 << 0) 114#define EMAC_MII_DATA 0x4c 115#define EMAC_ADDR_HIGH(n) (0x50 + (n) * 8) 116#define EMAC_ADDR_LOW(n) (0x54 + (n) * 8) 117#define EMAC_TX_DMA_STA 0xb0 118#define EMAC_TX_DMA_CUR_DESC 0xb4 119#define EMAC_TX_DMA_CUR_BUF 0xb8 120#define EMAC_RX_DMA_STA 0xc0 121#define EMAC_RX_DMA_CUR_DESC 0xc4 122#define EMAC_RX_DMA_CUR_BUF 0xc8 123#define EMAC_RGMII_STA 0xd0 124 125struct emac_desc { 126 uint32_t status; 127/* Transmit */ 128#define TX_DESC_CTL (1 << 31) 129#define TX_HEADER_ERR (1 << 16) 130#define TX_LENGTH_ERR (1 << 14) 131#define TX_PAYLOAD_ERR (1 << 12) 132#define TX_CRS_ERR (1 << 10) 133#define TX_COL_ERR_0 (1 << 9) 134#define TX_COL_ERR_1 (1 << 8) 135#define TX_COL_CNT (0xf << 3) 136#define TX_COL_CNT_SHIFT 3 137#define TX_DEFER_ERR (1 << 2) 138#define TX_UNDERFLOW_ERR (1 << 1) 139#define TX_DEFER (1 << 0) 140/* Receive */ 141#define RX_DESC_CTL (1 << 31) 142#define RX_DAF_FAIL (1 << 30) 143#define RX_FRM_LEN (0x3fff << 16) 144#define RX_FRM_LEN_SHIFT 16 145#define RX_NO_ENOUGH_BUF_ERR (1 << 14) 146#define RX_SAF_FAIL (1 << 13) 147#define RX_OVERFLOW_ERR (1 << 11) 148#define RX_FIR_DESC (1 << 9) 149#define RX_LAST_DESC (1 << 8) 150#define RX_HEADER_ERR (1 << 7) 151#define RX_COL_ERR (1 << 6) 152#define RX_FRM_TYPE (1 << 5) 153#define RX_LENGTH_ERR (1 << 4) 154#define RX_PHY_ERR (1 << 3) 155#define RX_CRC_ERR (1 << 1) 156#define RX_PAYLOAD_ERR (1 << 0) 157 158 uint32_t size; 159/* Transmit */ 160#define TX_INT_CTL (1 << 31) 161#define TX_LAST_DESC (1 << 30) 162#define TX_FIR_DESC (1 << 29) 163#define TX_CHECKSUM_CTL (0x3 << 27) 164#define TX_CHECKSUM_CTL_IP 1 165#define TX_CHECKSUM_CTL_NO_PSE 2 166#define TX_CHECKSUM_CTL_FULL 3 167#define TX_CHECKSUM_CTL_SHIFT 27 168#define TX_CRC_CTL (1 << 26) 169#define TX_BUF_SIZE (0xfff << 0) 170#define TX_BUF_SIZE_SHIFT 0 171/* Receive */ 172#define RX_INT_CTL (1 << 31) 173#define RX_BUF_SIZE (0xfff << 0) 174#define RX_BUF_SIZE_SHIFT 0 175 176 uint32_t addr; 177 178 uint32_t next; 179} __packed; 180 181#endif /* !__IF_AWGREG_H__ */ 182