1/*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 *
25 * $FreeBSD$
26 */
27
28/*
29 * Allwinner RSB (Reduced Serial Bus) and P2WI (Push-Pull Two Wire Interface)
30 */
31
32#include <sys/cdefs.h>
33__FBSDID("$FreeBSD$");
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/bus.h>
38#include <sys/rman.h>
39#include <sys/kernel.h>
40#include <sys/lock.h>
41#include <sys/module.h>
42#include <sys/mutex.h>
43#include <machine/bus.h>
44
45#include <dev/ofw/ofw_bus.h>
46#include <dev/ofw/ofw_bus_subr.h>
47
48#include <dev/iicbus/iiconf.h>
49#include <dev/iicbus/iicbus.h>
50
51#include <dev/extres/clk/clk.h>
52#include <dev/extres/hwreset/hwreset.h>
53
54#include "iicbus_if.h"
55
56#define	RSB_CTRL		0x00
57#define	 START_TRANS		(1 << 7)
58#define	 GLOBAL_INT_ENB		(1 << 1)
59#define	 SOFT_RESET		(1 << 0)
60#define	RSB_CCR		0x04
61#define	RSB_INTE		0x08
62#define	RSB_INTS		0x0c
63#define	 INT_TRANS_ERR_ID(x)	(((x) >> 8) & 0xf)
64#define	 INT_LOAD_BSY		(1 << 2)
65#define	 INT_TRANS_ERR		(1 << 1)
66#define	 INT_TRANS_OVER		(1 << 0)
67#define	 INT_MASK		(INT_LOAD_BSY|INT_TRANS_ERR|INT_TRANS_OVER)
68#define	RSB_DADDR0		0x10
69#define	RSB_DADDR1		0x14
70#define	RSB_DLEN		0x18
71#define	 DLEN_READ		(1 << 4)
72#define	RSB_DATA0		0x1c
73#define	RSB_DATA1		0x20
74#define	RSB_CMD			0x2c
75#define	 CMD_SRTA		0xe8
76#define	 CMD_RD8		0x8b
77#define	 CMD_RD16		0x9c
78#define	 CMD_RD32		0xa6
79#define	 CMD_WR8		0x4e
80#define	 CMD_WR16		0x59
81#define	 CMD_WR32		0x63
82#define	RSB_DAR			0x30
83#define	 DAR_RTA		(0xff << 16)
84#define	 DAR_RTA_SHIFT		16
85#define	 DAR_DA			(0xffff << 0)
86#define	 DAR_DA_SHIFT		0
87
88#define	RSB_MAXLEN		8
89#define	RSB_RESET_RETRY		100
90#define	RSB_I2C_TIMEOUT		hz
91
92#define	RSB_ADDR_PMIC_PRIMARY	0x3a3
93#define	RSB_ADDR_PMIC_SECONDARY	0x745
94#define	RSB_ADDR_PERIPH_IC	0xe89
95
96#define	A31_P2WI	1
97#define	A23_RSB		2
98
99static struct ofw_compat_data compat_data[] = {
100	{ "allwinner,sun6i-a31-p2wi",		A31_P2WI },
101	{ "allwinner,sun8i-a23-rsb",		A23_RSB },
102	{ NULL,					0 }
103};
104
105static struct resource_spec rsb_spec[] = {
106	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
107	{ -1, 0 }
108};
109
110/*
111 * Device address to Run-time address mappings.
112 *
113 * Run-time address (RTA) is an 8-bit value used to address the device during
114 * a read or write transaction. The following are valid RTAs:
115 *  0x17 0x2d 0x3a 0x4e 0x59 0x63 0x74 0x8b 0x9c 0xa6 0xb1 0xc5 0xd2 0xe8 0xff
116 *
117 * Allwinner uses RTA 0x2d for the primary PMIC, 0x3a for the secondary PMIC,
118 * and 0x4e for the peripheral IC (where applicable).
119 */
120static const struct {
121	uint16_t	addr;
122	uint8_t		rta;
123} rsb_rtamap[] = {
124	{ .addr = RSB_ADDR_PMIC_PRIMARY,	.rta = 0x2d },
125	{ .addr = RSB_ADDR_PMIC_SECONDARY,	.rta = 0x3a },
126	{ .addr = RSB_ADDR_PERIPH_IC,		.rta = 0x4e },
127	{ .addr = 0,				.rta = 0 }
128};
129
130struct rsb_softc {
131	struct resource	*res;
132	struct mtx	mtx;
133	clk_t		clk;
134	hwreset_t	rst;
135	device_t	iicbus;
136	int		busy;
137	uint32_t	status;
138	uint16_t	cur_addr;
139	int		type;
140
141	struct iic_msg	*msg;
142};
143
144#define	RSB_LOCK(sc)			mtx_lock(&(sc)->mtx)
145#define	RSB_UNLOCK(sc)			mtx_unlock(&(sc)->mtx)
146#define	RSB_ASSERT_LOCKED(sc)		mtx_assert(&(sc)->mtx, MA_OWNED)
147#define	RSB_READ(sc, reg)		bus_read_4((sc)->res, (reg))
148#define	RSB_WRITE(sc, reg, val)	bus_write_4((sc)->res, (reg), (val))
149
150static phandle_t
151rsb_get_node(device_t bus, device_t dev)
152{
153	return (ofw_bus_get_node(bus));
154}
155
156static int
157rsb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
158{
159	struct rsb_softc *sc;
160	int retry;
161
162	sc = device_get_softc(dev);
163
164	RSB_LOCK(sc);
165
166	/* Write soft-reset bit and wait for it to self-clear. */
167	RSB_WRITE(sc, RSB_CTRL, SOFT_RESET);
168	for (retry = RSB_RESET_RETRY; retry > 0; retry--)
169		if ((RSB_READ(sc, RSB_CTRL) & SOFT_RESET) == 0)
170			break;
171
172	RSB_UNLOCK(sc);
173
174	if (retry == 0) {
175		device_printf(dev, "soft reset timeout\n");
176		return (ETIMEDOUT);
177	}
178
179	return (IIC_ENOADDR);
180}
181
182static uint32_t
183rsb_encode(const uint8_t *buf, u_int len, u_int off)
184{
185	uint32_t val;
186	u_int n;
187
188	val = 0;
189	for (n = off; n < MIN(len, 4 + off); n++)
190		val |= ((uint32_t)buf[n] << ((n - off) * NBBY));
191
192	return val;
193}
194
195static void
196rsb_decode(const uint32_t val, uint8_t *buf, u_int len, u_int off)
197{
198	u_int n;
199
200	for (n = off; n < MIN(len, 4 + off); n++)
201		buf[n] = (val >> ((n - off) * NBBY)) & 0xff;
202}
203
204static int
205rsb_start(device_t dev)
206{
207	struct rsb_softc *sc;
208	int error, retry;
209
210	sc = device_get_softc(dev);
211
212	RSB_ASSERT_LOCKED(sc);
213
214	/* Start the transfer */
215	RSB_WRITE(sc, RSB_CTRL, GLOBAL_INT_ENB | START_TRANS);
216
217	/* Wait for transfer to complete */
218	error = ETIMEDOUT;
219	for (retry = RSB_I2C_TIMEOUT; retry > 0; retry--) {
220		sc->status |= RSB_READ(sc, RSB_INTS);
221		if ((sc->status & INT_TRANS_OVER) != 0) {
222			error = 0;
223			break;
224		}
225		DELAY((1000 * hz) / RSB_I2C_TIMEOUT);
226	}
227	if (error == 0 && (sc->status & INT_TRANS_OVER) == 0) {
228		device_printf(dev, "transfer error, status 0x%08x\n",
229		    sc->status);
230		error = EIO;
231	}
232
233	return (error);
234
235}
236
237static int
238rsb_set_rta(device_t dev, uint16_t addr)
239{
240	struct rsb_softc *sc;
241	uint8_t rta;
242	int i;
243
244	sc = device_get_softc(dev);
245
246	RSB_ASSERT_LOCKED(sc);
247
248	/* Lookup run-time address for given device address */
249	for (rta = 0, i = 0; rsb_rtamap[i].rta != 0; i++)
250		if (rsb_rtamap[i].addr == addr) {
251			rta = rsb_rtamap[i].rta;
252			break;
253		}
254	if (rta == 0) {
255		device_printf(dev, "RTA not known for address %#x\n", addr);
256		return (ENXIO);
257	}
258
259	/* Set run-time address */
260	RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
261	RSB_WRITE(sc, RSB_DAR, (addr << DAR_DA_SHIFT) | (rta << DAR_RTA_SHIFT));
262	RSB_WRITE(sc, RSB_CMD, CMD_SRTA);
263
264	return (rsb_start(dev));
265}
266
267static int
268rsb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
269{
270	struct rsb_softc *sc;
271	uint32_t daddr[2], data[2], dlen;
272	uint16_t device_addr;
273	uint8_t cmd;
274	int error;
275
276	sc = device_get_softc(dev);
277
278	/*
279	 * P2WI and RSB are not really I2C or SMBus controllers, so there are
280	 * some restrictions imposed by the driver.
281	 *
282	 * Transfers must contain exactly two messages. The first is always
283	 * a write, containing a single data byte offset. Data will either
284	 * be read from or written to the corresponding data byte in the
285	 * second message. The slave address in both messages must be the
286	 * same.
287	 */
288	if (nmsgs != 2 || (msgs[0].flags & IIC_M_RD) == IIC_M_RD ||
289	    (msgs[0].slave >> 1) != (msgs[1].slave >> 1) ||
290	    msgs[0].len != 1 || msgs[1].len > RSB_MAXLEN)
291		return (EINVAL);
292
293	/* The RSB controller can read or write 1, 2, or 4 bytes at a time. */
294	if (sc->type == A23_RSB) {
295		if ((msgs[1].flags & IIC_M_RD) != 0) {
296			switch (msgs[1].len) {
297			case 1:
298				cmd = CMD_RD8;
299				break;
300			case 2:
301				cmd = CMD_RD16;
302				break;
303			case 4:
304				cmd = CMD_RD32;
305				break;
306			default:
307				return (EINVAL);
308			}
309		} else {
310			switch (msgs[1].len) {
311			case 1:
312				cmd = CMD_WR8;
313				break;
314			case 2:
315				cmd = CMD_WR16;
316				break;
317			case 4:
318				cmd = CMD_WR32;
319				break;
320			default:
321				return (EINVAL);
322			}
323		}
324	}
325
326	RSB_LOCK(sc);
327	while (sc->busy)
328		mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
329	sc->busy = 1;
330	sc->status = 0;
331
332	/* Select current run-time address if necessary */
333	if (sc->type == A23_RSB) {
334		device_addr = msgs[0].slave >> 1;
335		if (sc->cur_addr != device_addr) {
336			error = rsb_set_rta(dev, device_addr);
337			if (error != 0)
338				goto done;
339			sc->cur_addr = device_addr;
340			sc->status = 0;
341		}
342	}
343
344	/* Clear interrupt status */
345	RSB_WRITE(sc, RSB_INTS, RSB_READ(sc, RSB_INTS));
346
347	/* Program data access address registers */
348	daddr[0] = rsb_encode(msgs[0].buf, msgs[0].len, 0);
349	RSB_WRITE(sc, RSB_DADDR0, daddr[0]);
350
351	/* Write data */
352	if ((msgs[1].flags & IIC_M_RD) == 0) {
353		data[0] = rsb_encode(msgs[1].buf, msgs[1].len, 0);
354		RSB_WRITE(sc, RSB_DATA0, data[0]);
355	}
356
357	/* Set command type for RSB */
358	if (sc->type == A23_RSB)
359		RSB_WRITE(sc, RSB_CMD, cmd);
360
361	/* Program data length register and transfer direction */
362	dlen = msgs[0].len - 1;
363	if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD)
364		dlen |= DLEN_READ;
365	RSB_WRITE(sc, RSB_DLEN, dlen);
366
367	/* Start transfer */
368	error = rsb_start(dev);
369	if (error != 0)
370		goto done;
371
372	/* Read data */
373	if ((msgs[1].flags & IIC_M_RD) == IIC_M_RD) {
374		data[0] = RSB_READ(sc, RSB_DATA0);
375		rsb_decode(data[0], msgs[1].buf, msgs[1].len, 0);
376	}
377
378done:
379	sc->msg = NULL;
380	sc->busy = 0;
381	wakeup(sc);
382	RSB_UNLOCK(sc);
383
384	return (error);
385}
386
387static int
388rsb_probe(device_t dev)
389{
390	if (!ofw_bus_status_okay(dev))
391		return (ENXIO);
392
393	switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
394	case A23_RSB:
395		device_set_desc(dev, "Allwinner RSB");
396		break;
397	case A31_P2WI:
398		device_set_desc(dev, "Allwinner P2WI");
399		break;
400	default:
401		return (ENXIO);
402	}
403
404	return (BUS_PROBE_DEFAULT);
405}
406
407static int
408rsb_attach(device_t dev)
409{
410	struct rsb_softc *sc;
411	int error;
412
413	sc = device_get_softc(dev);
414	mtx_init(&sc->mtx, device_get_nameunit(dev), "rsb", MTX_DEF);
415
416	sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
417
418	if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) == 0) {
419		error = clk_enable(sc->clk);
420		if (error != 0) {
421			device_printf(dev, "cannot enable clock\n");
422			goto fail;
423		}
424	}
425	if (hwreset_get_by_ofw_idx(dev, 0, 0, &sc->rst) == 0) {
426		error = hwreset_deassert(sc->rst);
427		if (error != 0) {
428			device_printf(dev, "cannot de-assert reset\n");
429			goto fail;
430		}
431	}
432
433	if (bus_alloc_resources(dev, rsb_spec, &sc->res) != 0) {
434		device_printf(dev, "cannot allocate resources for device\n");
435		error = ENXIO;
436		goto fail;
437	}
438
439	sc->iicbus = device_add_child(dev, "iicbus", -1);
440	if (sc->iicbus == NULL) {
441		device_printf(dev, "cannot add iicbus child device\n");
442		error = ENXIO;
443		goto fail;
444	}
445
446	bus_generic_attach(dev);
447
448	return (0);
449
450fail:
451	bus_release_resources(dev, rsb_spec, &sc->res);
452	if (sc->rst != NULL)
453		hwreset_release(sc->rst);
454	if (sc->clk != NULL)
455		clk_release(sc->clk);
456	mtx_destroy(&sc->mtx);
457	return (error);
458}
459
460static device_method_t rsb_methods[] = {
461	/* Device interface */
462	DEVMETHOD(device_probe,		rsb_probe),
463	DEVMETHOD(device_attach,	rsb_attach),
464
465	/* Bus interface */
466	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
467	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
468	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
469	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
470	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
471	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
472	DEVMETHOD(bus_adjust_resource,	bus_generic_adjust_resource),
473	DEVMETHOD(bus_set_resource,	bus_generic_rl_set_resource),
474	DEVMETHOD(bus_get_resource,	bus_generic_rl_get_resource),
475
476	/* OFW methods */
477	DEVMETHOD(ofw_bus_get_node,	rsb_get_node),
478
479	/* iicbus interface */
480	DEVMETHOD(iicbus_callback,	iicbus_null_callback),
481	DEVMETHOD(iicbus_reset,		rsb_reset),
482	DEVMETHOD(iicbus_transfer,	rsb_transfer),
483
484	DEVMETHOD_END
485};
486
487static driver_t rsb_driver = {
488	"iichb",
489	rsb_methods,
490	sizeof(struct rsb_softc),
491};
492
493static devclass_t rsb_devclass;
494
495EARLY_DRIVER_MODULE(iicbus, rsb, iicbus_driver, iicbus_devclass, 0, 0,
496    BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
497EARLY_DRIVER_MODULE(rsb, simplebus, rsb_driver, rsb_devclass, 0, 0,
498    BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
499MODULE_VERSION(rsb, 1);
500MODULE_DEPEND(rsb, iicbus, 1, 1, 1);
501SIMPLEBUS_PNP_INFO(compat_data);
502