1/*- 2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca> 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28/* 29 * Allwinner GMAC clock 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD$"); 34 35#include <sys/param.h> 36#include <sys/systm.h> 37#include <sys/bus.h> 38#include <sys/rman.h> 39#include <sys/kernel.h> 40#include <sys/module.h> 41#include <machine/bus.h> 42 43#include <dev/ofw/ofw_bus.h> 44#include <dev/ofw/ofw_bus_subr.h> 45#include <dev/ofw/ofw_subr.h> 46 47#include <dev/extres/clk/clk_mux.h> 48#include <dev/extres/clk/clk_gate.h> 49 50#include "clkdev_if.h" 51 52#define GMAC_CLK_PIT (0x1 << 2) 53#define GMAC_CLK_PIT_SHIFT 2 54#define GMAC_CLK_PIT_MII 0 55#define GMAC_CLK_PIT_RGMII 1 56#define GMAC_CLK_SRC (0x3 << 0) 57#define GMAC_CLK_SRC_SHIFT 0 58#define GMAC_CLK_SRC_MII 0 59#define GMAC_CLK_SRC_EXT_RGMII 1 60#define GMAC_CLK_SRC_RGMII 2 61 62#define EMAC_TXC_DIV_CFG (1 << 15) 63#define EMAC_TXC_DIV_CFG_SHIFT 15 64#define EMAC_TXC_DIV_CFG_125MHZ 0 65#define EMAC_TXC_DIV_CFG_25MHZ 1 66#define EMAC_PHY_SELECT (1 << 16) 67#define EMAC_PHY_SELECT_SHIFT 16 68#define EMAC_PHY_SELECT_INT 0 69#define EMAC_PHY_SELECT_EXT 1 70#define EMAC_ETXDC (0x7 << 10) 71#define EMAC_ETXDC_SHIFT 10 72#define EMAC_ERXDC (0x1f << 5) 73#define EMAC_ERXDC_SHIFT 5 74 75#define CLK_IDX_MII 0 76#define CLK_IDX_RGMII 1 77#define CLK_IDX_COUNT 2 78 79static struct ofw_compat_data compat_data[] = { 80 { "allwinner,sun7i-a20-gmac-clk", 1 }, 81 { NULL, 0 } 82}; 83 84struct aw_gmacclk_sc { 85 device_t clkdev; 86 bus_addr_t reg; 87 88 int rx_delay; 89 int tx_delay; 90}; 91 92#define GMACCLK_READ(sc, val) CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val)) 93#define GMACCLK_WRITE(sc, val) CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val)) 94#define DEVICE_LOCK(sc) CLKDEV_DEVICE_LOCK((sc)->clkdev) 95#define DEVICE_UNLOCK(sc) CLKDEV_DEVICE_UNLOCK((sc)->clkdev) 96 97static int 98aw_gmacclk_init(struct clknode *clk, device_t dev) 99{ 100 struct aw_gmacclk_sc *sc; 101 uint32_t val, index; 102 103 sc = clknode_get_softc(clk); 104 105 DEVICE_LOCK(sc); 106 GMACCLK_READ(sc, &val); 107 DEVICE_UNLOCK(sc); 108 109 switch ((val & GMAC_CLK_SRC) >> GMAC_CLK_SRC_SHIFT) { 110 case GMAC_CLK_SRC_MII: 111 index = CLK_IDX_MII; 112 break; 113 case GMAC_CLK_SRC_RGMII: 114 index = CLK_IDX_RGMII; 115 break; 116 default: 117 return (ENXIO); 118 } 119 120 clknode_init_parent_idx(clk, index); 121 return (0); 122} 123 124static int 125aw_gmacclk_set_mux(struct clknode *clk, int index) 126{ 127 struct aw_gmacclk_sc *sc; 128 uint32_t val, clk_src, pit, txc_div; 129 int error; 130 131 sc = clknode_get_softc(clk); 132 error = 0; 133 134 switch (index) { 135 case CLK_IDX_MII: 136 clk_src = GMAC_CLK_SRC_MII; 137 pit = GMAC_CLK_PIT_MII; 138 txc_div = EMAC_TXC_DIV_CFG_25MHZ; 139 break; 140 case CLK_IDX_RGMII: 141 clk_src = GMAC_CLK_SRC_RGMII; 142 pit = GMAC_CLK_PIT_RGMII; 143 txc_div = EMAC_TXC_DIV_CFG_125MHZ; 144 break; 145 default: 146 return (ENXIO); 147 } 148 149 DEVICE_LOCK(sc); 150 GMACCLK_READ(sc, &val); 151 val &= ~(GMAC_CLK_SRC | GMAC_CLK_PIT); 152 val |= (clk_src << GMAC_CLK_SRC_SHIFT); 153 val |= (pit << GMAC_CLK_PIT_SHIFT); 154 GMACCLK_WRITE(sc, val); 155 DEVICE_UNLOCK(sc); 156 157 return (0); 158} 159 160static clknode_method_t aw_gmacclk_clknode_methods[] = { 161 /* Device interface */ 162 CLKNODEMETHOD(clknode_init, aw_gmacclk_init), 163 CLKNODEMETHOD(clknode_set_mux, aw_gmacclk_set_mux), 164 CLKNODEMETHOD_END 165}; 166DEFINE_CLASS_1(aw_gmacclk_clknode, aw_gmacclk_clknode_class, 167 aw_gmacclk_clknode_methods, sizeof(struct aw_gmacclk_sc), clknode_class); 168 169static int 170aw_gmacclk_probe(device_t dev) 171{ 172 if (!ofw_bus_status_okay(dev)) 173 return (ENXIO); 174 175 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 176 return (ENXIO); 177 178 device_set_desc(dev, "Allwinner GMAC Clock"); 179 return (BUS_PROBE_DEFAULT); 180} 181 182static int 183aw_gmacclk_attach(device_t dev) 184{ 185 struct clknode_init_def def; 186 struct aw_gmacclk_sc *sc; 187 struct clkdom *clkdom; 188 struct clknode *clk; 189 clk_t clk_parent; 190 bus_addr_t paddr; 191 bus_size_t psize; 192 phandle_t node; 193 int error, ncells, i; 194 195 node = ofw_bus_get_node(dev); 196 197 if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) { 198 device_printf(dev, "cannot parse 'reg' property\n"); 199 return (ENXIO); 200 } 201 202 error = ofw_bus_parse_xref_list_get_length(node, "clocks", 203 "#clock-cells", &ncells); 204 if (error != 0 || ncells != CLK_IDX_COUNT) { 205 device_printf(dev, "couldn't find parent clocks\n"); 206 return (ENXIO); 207 } 208 209 clkdom = clkdom_create(dev); 210 211 memset(&def, 0, sizeof(def)); 212 error = clk_parse_ofw_clk_name(dev, node, &def.name); 213 if (error != 0) { 214 device_printf(dev, "cannot parse clock name\n"); 215 error = ENXIO; 216 goto fail; 217 } 218 def.id = 1; 219 def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK); 220 for (i = 0; i < ncells; i++) { 221 error = clk_get_by_ofw_index(dev, 0, i, &clk_parent); 222 if (error != 0) { 223 device_printf(dev, "cannot get clock %d\n", error); 224 goto fail; 225 } 226 def.parent_names[i] = clk_get_name(clk_parent); 227 clk_release(clk_parent); 228 } 229 def.parent_cnt = ncells; 230 231 clk = clknode_create(clkdom, &aw_gmacclk_clknode_class, &def); 232 if (clk == NULL) { 233 device_printf(dev, "cannot create clknode\n"); 234 error = ENXIO; 235 goto fail; 236 } 237 238 sc = clknode_get_softc(clk); 239 sc->reg = paddr; 240 sc->clkdev = device_get_parent(dev); 241 sc->tx_delay = sc->rx_delay = -1; 242 OF_getencprop(node, "tx-delay", &sc->tx_delay, sizeof(sc->tx_delay)); 243 OF_getencprop(node, "rx-delay", &sc->rx_delay, sizeof(sc->rx_delay)); 244 245 clknode_register(clkdom, clk); 246 247 if (clkdom_finit(clkdom) != 0) { 248 device_printf(dev, "cannot finalize clkdom initialization\n"); 249 error = ENXIO; 250 goto fail; 251 } 252 253 if (bootverbose) 254 clkdom_dump(clkdom); 255 256 return (0); 257 258fail: 259 return (error); 260} 261 262static device_method_t aw_gmacclk_methods[] = { 263 /* Device interface */ 264 DEVMETHOD(device_probe, aw_gmacclk_probe), 265 DEVMETHOD(device_attach, aw_gmacclk_attach), 266 267 DEVMETHOD_END 268}; 269 270static driver_t aw_gmacclk_driver = { 271 "aw_gmacclk", 272 aw_gmacclk_methods, 273 0 274}; 275 276static devclass_t aw_gmacclk_devclass; 277 278EARLY_DRIVER_MODULE(aw_gmacclk, simplebus, aw_gmacclk_driver, 279 aw_gmacclk_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 280