1/*
2 * \file       trc_pkt_types_stm.h
3 * \brief      OpenCSD : STM decoder
4 *
5 * \copyright  Copyright (c) 2015, ARM Limited. All Rights Reserved.
6 */
7
8/*
9 * Redistribution and use in source and binary forms, with or without modification,
10 * are permitted provided that the following conditions are met:
11 *
12 * 1. Redistributions of source code must retain the above copyright notice,
13 * this list of conditions and the following disclaimer.
14 *
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 *
19 * 3. Neither the name of the copyright holder nor the names of its contributors
20 * may be used to endorse or promote products derived from this software without
21 * specific prior written permission.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34#ifndef ARM_TRC_PKT_TYPES_STM_H_INCLUDED
35#define ARM_TRC_PKT_TYPES_STM_H_INCLUDED
36
37#include "opencsd/trc_pkt_types.h"
38
39/** @addtogroup trc_pkts
40@{*/
41
42/** @name STM Packet Types
43@{*/
44
45/** STM protocol packet types.
46    Contains both protocol packet types and markers for unsynced processor
47    state and bad packet sequences.
48*/
49typedef enum _ocsd_stm_pkt_type
50{
51/* markers for unknown packets  / state*/
52    STM_PKT_NOTSYNC,            /**< Not synchronised */
53    STM_PKT_INCOMPLETE_EOT,     /**< Incomplete packet flushed at end of trace. */
54    STM_PKT_NO_ERR_TYPE,        /**< No error in error packet marker. */
55
56/* markers for valid packets*/
57    STM_PKT_ASYNC,      /**< Alignment synchronisation packet */
58    STM_PKT_VERSION,    /**< Version packet */
59    STM_PKT_FREQ,       /**< Frequency packet */
60    STM_PKT_NULL,       /**< Null packet */
61    STM_PKT_TRIG,       /**< Trigger event packet. */
62
63    STM_PKT_GERR,       /**< Global error packet - protocol error but unknown which master had error */
64    STM_PKT_MERR,       /**< Master error packet - current master detected an error (e.g. dropped trace) */
65
66    STM_PKT_M8,         /**< Set current master */
67    STM_PKT_C8,         /**< Set lower 8 bits of current channel */
68    STM_PKT_C16,        /**< Set current channel */
69
70    STM_PKT_FLAG,       /**< Flag packet */
71
72    STM_PKT_D4,         /**< 4 bit data payload packet */
73    STM_PKT_D8,         /**< 8 bit data payload packet */
74    STM_PKT_D16,        /**< 16 bit data payload packet */
75    STM_PKT_D32,        /**< 32 bit data payload packet */
76    STM_PKT_D64,        /**< 64 bit data payload packet */
77
78/* packet errors.*/
79    STM_PKT_BAD_SEQUENCE,   /**< Incorrect protocol sequence */
80    STM_PKT_RESERVED,       /**< Reserved packet header / not supported by CS-STM */
81
82} ocsd_stm_pkt_type;
83
84/** STM timestamp encoding type.
85    Extracted from STM version packet.
86    CS-STM supports Natural binary and grey encodings.
87*/
88typedef enum _ocsd_stm_ts_type
89{
90    STM_TS_UNKNOWN,     /**< TS encoding unknown at present. */
91    STM_TS_NATBINARY,   /**< TS encoding natural binary */
92    STM_TS_GREY         /**< TS encoding grey coded. */
93} ocsd_stm_ts_type;
94
95/** STM trace packet
96
97    Structure containing the packet data for a single STM packet, plus
98    data persisting between packets (master, channel, last timestamp).
99*/
100typedef struct _ocsd_stm_pkt
101{
102    ocsd_stm_pkt_type type;        /**< STM packet type */
103
104    uint8_t     master;             /**< current master */
105    uint16_t    channel;            /**< current channel */
106
107    uint64_t    timestamp;          /**< latest timestamp value -> as binary - packet processor does grey decoding */
108    uint8_t     pkt_ts_bits;        /**< timestamp bits updated this packet */
109    uint8_t     pkt_has_ts;         /**< current packet has associated timestamp (ts bits can be 0 if same value as last time) */
110
111    ocsd_stm_ts_type ts_type;      /**< timestamp encoding type */
112
113    uint8_t     pkt_has_marker;     /**< flag to indicate current packet has marker */
114
115    union {
116        uint8_t  D8;    /**< payload for D8 or D4 data packet, or parameter value for other packets with 8 bit value [VERSION, TRIG, xERR] */
117        uint16_t D16;   /**< payload for D16 data packet, or reserved opcode in bad packet header (1-3 nibbles) */
118        uint32_t D32;   /**< payload for D32 data packet, or parameter value for other packets with 32 bit value [FREQ] */
119        uint64_t D64;   /**< payload for D64 data packet */
120    } payload;
121
122    ocsd_stm_pkt_type err_type;    /**< Initial type of packet if type indicates bad sequence. */
123
124} ocsd_stm_pkt;
125
126/** HW Event trace feature
127    Defines if the STM supports or has enabled the HW event trace feature.
128    This may not always be able to be determined by the registers, or the feature
129    values can override if HW event trace is to be ignored.
130*/
131typedef enum _hw_event_feat {
132    HwEvent_Unknown_Disabled,   /*!< status of HW event features not known - assume not present or disabled */
133    HwEvent_Enabled,            /*!< HW event present and enabled - ignore Feat regs, assume hwev_mast value valid */
134    HwEvent_UseRegisters        /*!< Feature Register values and enable bits used to determine HW event trace status */
135} hw_event_feat_t;
136
137
138/** STM hardware configuration.
139    Contains hardware register values at time of trace capture and HW event feature
140    field to enable and control decode of STM trace stream.
141*/
142typedef struct _ocsd_stm_cfg
143{
144    uint32_t reg_tcsr;          /**< Contains CoreSight trace ID, HWTEN */
145    uint32_t reg_feat3r;        /**< defines number of masters */
146    uint32_t reg_devid;         /**< defines number of channels per master */
147
148    uint32_t reg_feat1r;        /**< defines HW trace features */
149    uint32_t reg_hwev_mast;     /**< master ID for HW event trace */
150    hw_event_feat_t hw_event;   /**< status of HW event trace */
151} ocsd_stm_cfg;
152
153/** @}*/
154/** @}*/
155
156#endif // ARM_TRC_PKT_TYPES_STM_H_INCLUDED
157
158/* End of File trc_pkt_types_stm.h */
159