1/* 2 * \file trc_idec_arminst.h 3 * \brief OpenCSD : 4 * 5 * \copyright Copyright (c) 2015, ARM Limited. All Rights Reserved. 6 */ 7 8/* 9 * Redistribution and use in source and binary forms, with or without modification, 10 * are permitted provided that the following conditions are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright notice, 13 * this list of conditions and the following disclaimer. 14 * 15 * 2. Redistributions in binary form must reproduce the above copyright notice, 16 * this list of conditions and the following disclaimer in the documentation 17 * and/or other materials provided with the distribution. 18 * 19 * 3. Neither the name of the copyright holder nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 'AS IS' AND 24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 28 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 30 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35#ifndef ARM_TRC_IDEC_ARMINST_H_INCLUDED 36#define ARM_TRC_IDEC_ARMINST_H_INCLUDED 37 38#ifndef __STDC_CONSTANT_MACROS 39#define __STDC_CONSTANT_MACROS 1 40#endif 41 42#include "opencsd/ocsd_if_types.h" 43#include <cstdint> 44 45/* supplementary decode information */ 46struct decode_info { 47 uint16_t arch_version; 48 ocsd_instr_subtype instr_sub_type; 49}; 50 51/* 52For Thumb2, test if a halfword is the first half of a 32-bit instruction, 53as opposed to a complete 16-bit instruction. 54*/ 55inline int is_wide_thumb(uint16_t insthw) 56{ 57 return (insthw & 0xF800) >= 0xE800; 58} 59 60/* 61In the following queries, 16-bit Thumb2 instructions should be 62passed in as the high halfword, e.g. xxxx0000. 63*/ 64 65/* 66Test whether an instruction is a branch (software change of the PC). 67This includes branch instructions and all loads and data-processing 68instructions that write to the PC. It does not include exception 69instructions such as SVC, HVC and SMC. 70(Performance event 0x0C includes these.) 71*/ 72int inst_ARM_is_branch(uint32_t inst, struct decode_info *info); 73int inst_Thumb_is_branch(uint32_t inst, struct decode_info *info); 74int inst_A64_is_branch(uint32_t inst, struct decode_info *info); 75 76/* 77Test whether an instruction is a direct (aka immediate) branch. 78Performance event 0x0D counts these. 79*/ 80int inst_ARM_is_direct_branch(uint32_t inst); 81int inst_Thumb_is_direct_branch(uint32_t inst, struct decode_info *info); 82int inst_Thumb_is_direct_branch_link(uint32_t inst, uint8_t *is_link, uint8_t *is_cond, struct decode_info *info); 83int inst_A64_is_direct_branch(uint32_t inst, struct decode_info *info); 84int inst_A64_is_direct_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info); 85 86/* 87Get branch destination for a direct branch. 88*/ 89int inst_ARM_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc); 90int inst_Thumb_branch_destination(uint32_t addr, uint32_t inst, uint32_t *pnpc); 91int inst_A64_branch_destination(uint64_t addr, uint32_t inst, uint64_t *pnpc); 92 93int inst_ARM_is_indirect_branch(uint32_t inst, struct decode_info *info); 94int inst_Thumb_is_indirect_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info); 95int inst_Thumb_is_indirect_branch(uint32_t inst, struct decode_info *info); 96int inst_A64_is_indirect_branch_link(uint32_t inst, uint8_t *is_link, struct decode_info *info); 97int inst_A64_is_indirect_branch(uint32_t inst, struct decode_info *info); 98 99int inst_ARM_is_branch_and_link(uint32_t inst, struct decode_info *info); 100int inst_Thumb_is_branch_and_link(uint32_t inst, struct decode_info *info); 101int inst_A64_is_branch_and_link(uint32_t inst, struct decode_info *info); 102 103int inst_ARM_is_conditional(uint32_t inst); 104int inst_Thumb_is_conditional(uint32_t inst); 105int inst_A64_is_conditional(uint32_t inst); 106 107/* For an IT instruction, return the number of instructions conditionalized 108 (from 1 to 4). For other instructions, return zero. */ 109unsigned int inst_Thumb_is_IT(uint32_t inst); 110 111typedef enum { 112 ARM_BARRIER_NONE, 113 ARM_BARRIER_ISB, 114 ARM_BARRIER_DMB, 115 ARM_BARRIER_DSB 116} arm_barrier_t; 117 118arm_barrier_t inst_ARM_barrier(uint32_t inst); 119arm_barrier_t inst_Thumb_barrier(uint32_t inst); 120arm_barrier_t inst_A64_barrier(uint32_t inst); 121 122int inst_ARM_wfiwfe(uint32_t inst); 123int inst_Thumb_wfiwfe(uint32_t inst); 124int inst_A64_wfiwfe(uint32_t inst); 125 126/* 127Test whether an instruction is definitely undefined, e.g. because 128allocated to a "permanently UNDEFINED" space (UDF mnemonic). 129Other instructions besides the ones indicated, may always or 130sometimes cause an undefined instruction trap. This call is 131intended to be helpful in 'runaway decode' prevention. 132*/ 133int inst_ARM_is_UDF(uint32_t inst); 134int inst_Thumb_is_UDF(uint32_t inst); 135int inst_A64_is_UDF(uint32_t inst); 136 137#endif // ARM_TRC_IDEC_ARMINST_H_INCLUDED 138 139/* End of File trc_idec_arminst.h */ 140