1//===-- X86InstrInfo.td - Main X86 Instruction Definition --*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file describes the X86 instruction set, defining the instructions, and 10// properties of the instructions which are needed for code generation, machine 11// code emission, and analysis. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// X86 specific DAG Nodes. 17// 18 19def SDTX86CmpTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>, 20 SDTCisSameAs<1, 2>]>; 21def SDTX86FCmp : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisFP<1>, 22 SDTCisSameAs<1, 2>]>; 23 24def SDTX86Cmov : SDTypeProfile<1, 4, 25 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, 26 SDTCisVT<3, i8>, SDTCisVT<4, i32>]>; 27 28// Unary and binary operator instructions that set EFLAGS as a side-effect. 29def SDTUnaryArithWithFlags : SDTypeProfile<2, 1, 30 [SDTCisSameAs<0, 2>, 31 SDTCisInt<0>, SDTCisVT<1, i32>]>; 32 33def SDTBinaryArithWithFlags : SDTypeProfile<2, 2, 34 [SDTCisSameAs<0, 2>, 35 SDTCisSameAs<0, 3>, 36 SDTCisInt<0>, SDTCisVT<1, i32>]>; 37 38// SDTBinaryArithWithFlagsInOut - RES1, EFLAGS = op LHS, RHS, EFLAGS 39def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3, 40 [SDTCisSameAs<0, 2>, 41 SDTCisSameAs<0, 3>, 42 SDTCisInt<0>, 43 SDTCisVT<1, i32>, 44 SDTCisVT<4, i32>]>; 45// RES1, RES2, FLAGS = op LHS, RHS 46def SDT2ResultBinaryArithWithFlags : SDTypeProfile<3, 2, 47 [SDTCisSameAs<0, 1>, 48 SDTCisSameAs<0, 2>, 49 SDTCisSameAs<0, 3>, 50 SDTCisInt<0>, SDTCisVT<1, i32>]>; 51def SDTX86BrCond : SDTypeProfile<0, 3, 52 [SDTCisVT<0, OtherVT>, 53 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 54 55def SDTX86SetCC : SDTypeProfile<1, 2, 56 [SDTCisVT<0, i8>, 57 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 58def SDTX86SetCC_C : SDTypeProfile<1, 2, 59 [SDTCisInt<0>, 60 SDTCisVT<1, i8>, SDTCisVT<2, i32>]>; 61 62def SDTX86sahf : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i8>]>; 63 64def SDTX86rdrand : SDTypeProfile<2, 0, [SDTCisInt<0>, SDTCisVT<1, i32>]>; 65 66def SDTX86rdpkru : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; 67def SDTX86wrpkru : SDTypeProfile<0, 3, [SDTCisVT<0, i32>, SDTCisVT<1, i32>, 68 SDTCisVT<2, i32>]>; 69 70def SDTX86cas : SDTypeProfile<0, 3, [SDTCisPtrTy<0>, SDTCisInt<1>, 71 SDTCisVT<2, i8>]>; 72def SDTX86caspair : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>; 73def SDTX86caspairSaveEbx8 : SDTypeProfile<1, 3, 74 [SDTCisVT<0, i32>, SDTCisPtrTy<1>, 75 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>; 76def SDTX86caspairSaveRbx16 : SDTypeProfile<1, 3, 77 [SDTCisVT<0, i64>, SDTCisPtrTy<1>, 78 SDTCisVT<2, i64>, SDTCisVT<3, i64>]>; 79 80def SDTLockBinaryArithWithFlags : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 81 SDTCisPtrTy<1>, 82 SDTCisInt<2>]>; 83 84def SDTLockUnaryArithWithFlags : SDTypeProfile<1, 1, [SDTCisVT<0, i32>, 85 SDTCisPtrTy<1>]>; 86 87def SDTX86Ret : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>; 88 89def SDT_X86CallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, 90 SDTCisVT<1, i32>]>; 91def SDT_X86CallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, 92 SDTCisVT<1, i32>]>; 93 94def SDT_X86Call : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 95 96def SDT_X86NtBrind : SDTypeProfile<0, -1, [SDTCisVT<0, iPTR>]>; 97 98def SDT_X86VASTART_SAVE_XMM_REGS : SDTypeProfile<0, -1, [SDTCisVT<0, i8>, 99 SDTCisVT<1, iPTR>, 100 SDTCisVT<2, iPTR>]>; 101 102def SDT_X86VAARG_64 : SDTypeProfile<1, -1, [SDTCisPtrTy<0>, 103 SDTCisPtrTy<1>, 104 SDTCisVT<2, i32>, 105 SDTCisVT<3, i8>, 106 SDTCisVT<4, i32>]>; 107 108def SDTX86RepStr : SDTypeProfile<0, 1, [SDTCisVT<0, OtherVT>]>; 109 110def SDTX86Void : SDTypeProfile<0, 0, []>; 111 112def SDTX86Wrapper : SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>; 113 114def SDT_X86TLSADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 115 116def SDT_X86TLSBASEADDR : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 117 118def SDT_X86TLSCALL : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 119 120def SDT_X86WIN_ALLOCA : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>; 121 122def SDT_X86SEG_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 123 124def SDT_X86PROBED_ALLOCA : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>, SDTCisVT<1, iPTR>]>; 125 126def SDT_X86EHRET : SDTypeProfile<0, 1, [SDTCisInt<0>]>; 127 128def SDT_X86TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>, SDTCisVT<1, i32>]>; 129 130def SDT_X86MEMBARRIER : SDTypeProfile<0, 0, []>; 131 132def SDT_X86ENQCMD : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, 133 SDTCisPtrTy<1>, SDTCisSameAs<1, 2>]>; 134 135def X86MemBarrier : SDNode<"X86ISD::MEMBARRIER", SDT_X86MEMBARRIER, 136 [SDNPHasChain,SDNPSideEffect]>; 137def X86MFence : SDNode<"X86ISD::MFENCE", SDT_X86MEMBARRIER, 138 [SDNPHasChain]>; 139 140 141def X86bsf : SDNode<"X86ISD::BSF", SDTUnaryArithWithFlags>; 142def X86bsr : SDNode<"X86ISD::BSR", SDTUnaryArithWithFlags>; 143def X86fshl : SDNode<"X86ISD::FSHL", SDTIntShiftDOp>; 144def X86fshr : SDNode<"X86ISD::FSHR", SDTIntShiftDOp>; 145 146def X86cmp : SDNode<"X86ISD::CMP" , SDTX86CmpTest>; 147def X86fcmp : SDNode<"X86ISD::FCMP", SDTX86FCmp>; 148def X86strict_fcmp : SDNode<"X86ISD::STRICT_FCMP", SDTX86FCmp, [SDNPHasChain]>; 149def X86strict_fcmps : SDNode<"X86ISD::STRICT_FCMPS", SDTX86FCmp, [SDNPHasChain]>; 150def X86bt : SDNode<"X86ISD::BT", SDTX86CmpTest>; 151 152def X86cmov : SDNode<"X86ISD::CMOV", SDTX86Cmov>; 153def X86brcond : SDNode<"X86ISD::BRCOND", SDTX86BrCond, 154 [SDNPHasChain]>; 155def X86setcc : SDNode<"X86ISD::SETCC", SDTX86SetCC>; 156def X86setcc_c : SDNode<"X86ISD::SETCC_CARRY", SDTX86SetCC_C>; 157 158def X86rdrand : SDNode<"X86ISD::RDRAND", SDTX86rdrand, 159 [SDNPHasChain, SDNPSideEffect]>; 160 161def X86rdseed : SDNode<"X86ISD::RDSEED", SDTX86rdrand, 162 [SDNPHasChain, SDNPSideEffect]>; 163 164def X86rdpkru : SDNode<"X86ISD::RDPKRU", SDTX86rdpkru, 165 [SDNPHasChain, SDNPSideEffect]>; 166def X86wrpkru : SDNode<"X86ISD::WRPKRU", SDTX86wrpkru, 167 [SDNPHasChain, SDNPSideEffect]>; 168 169def X86cas : SDNode<"X86ISD::LCMPXCHG_DAG", SDTX86cas, 170 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 171 SDNPMayLoad, SDNPMemOperand]>; 172def X86cas8 : SDNode<"X86ISD::LCMPXCHG8_DAG", SDTX86caspair, 173 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 174 SDNPMayLoad, SDNPMemOperand]>; 175def X86cas16 : SDNode<"X86ISD::LCMPXCHG16_DAG", SDTX86caspair, 176 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 177 SDNPMayLoad, SDNPMemOperand]>; 178def X86cas8save_ebx : SDNode<"X86ISD::LCMPXCHG8_SAVE_EBX_DAG", 179 SDTX86caspairSaveEbx8, 180 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 181 SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 182def X86cas16save_rbx : SDNode<"X86ISD::LCMPXCHG16_SAVE_RBX_DAG", 183 SDTX86caspairSaveRbx16, 184 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, 185 SDNPMayStore, SDNPMayLoad, SDNPMemOperand]>; 186 187def X86retflag : SDNode<"X86ISD::RET_FLAG", SDTX86Ret, 188 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 189def X86iret : SDNode<"X86ISD::IRET", SDTX86Ret, 190 [SDNPHasChain, SDNPOptInGlue]>; 191 192def X86vastart_save_xmm_regs : 193 SDNode<"X86ISD::VASTART_SAVE_XMM_REGS", 194 SDT_X86VASTART_SAVE_XMM_REGS, 195 [SDNPHasChain, SDNPVariadic]>; 196def X86vaarg64 : 197 SDNode<"X86ISD::VAARG_64", SDT_X86VAARG_64, 198 [SDNPHasChain, SDNPMayLoad, SDNPMayStore, 199 SDNPMemOperand]>; 200def X86callseq_start : 201 SDNode<"ISD::CALLSEQ_START", SDT_X86CallSeqStart, 202 [SDNPHasChain, SDNPOutGlue]>; 203def X86callseq_end : 204 SDNode<"ISD::CALLSEQ_END", SDT_X86CallSeqEnd, 205 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 206 207def X86call : SDNode<"X86ISD::CALL", SDT_X86Call, 208 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 209 SDNPVariadic]>; 210 211def X86NoTrackCall : SDNode<"X86ISD::NT_CALL", SDT_X86Call, 212 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, 213 SDNPVariadic]>; 214def X86NoTrackBrind : SDNode<"X86ISD::NT_BRIND", SDT_X86NtBrind, 215 [SDNPHasChain]>; 216 217def X86rep_stos: SDNode<"X86ISD::REP_STOS", SDTX86RepStr, 218 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore]>; 219def X86rep_movs: SDNode<"X86ISD::REP_MOVS", SDTX86RepStr, 220 [SDNPHasChain, SDNPInGlue, SDNPOutGlue, SDNPMayStore, 221 SDNPMayLoad]>; 222 223def X86Wrapper : SDNode<"X86ISD::Wrapper", SDTX86Wrapper>; 224def X86WrapperRIP : SDNode<"X86ISD::WrapperRIP", SDTX86Wrapper>; 225 226def X86RecoverFrameAlloc : SDNode<"ISD::LOCAL_RECOVER", 227 SDTypeProfile<1, 1, [SDTCisSameAs<0, 1>, 228 SDTCisInt<1>]>>; 229 230def X86tlsaddr : SDNode<"X86ISD::TLSADDR", SDT_X86TLSADDR, 231 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 232 233def X86tlsbaseaddr : SDNode<"X86ISD::TLSBASEADDR", SDT_X86TLSBASEADDR, 234 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 235 236def X86ehret : SDNode<"X86ISD::EH_RETURN", SDT_X86EHRET, 237 [SDNPHasChain]>; 238 239def X86eh_sjlj_setjmp : SDNode<"X86ISD::EH_SJLJ_SETJMP", 240 SDTypeProfile<1, 1, [SDTCisInt<0>, 241 SDTCisPtrTy<1>]>, 242 [SDNPHasChain, SDNPSideEffect]>; 243def X86eh_sjlj_longjmp : SDNode<"X86ISD::EH_SJLJ_LONGJMP", 244 SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>, 245 [SDNPHasChain, SDNPSideEffect]>; 246def X86eh_sjlj_setup_dispatch : SDNode<"X86ISD::EH_SJLJ_SETUP_DISPATCH", 247 SDTypeProfile<0, 0, []>, 248 [SDNPHasChain, SDNPSideEffect]>; 249 250def X86tcret : SDNode<"X86ISD::TC_RETURN", SDT_X86TCRET, 251 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; 252 253def X86add_flag : SDNode<"X86ISD::ADD", SDTBinaryArithWithFlags, 254 [SDNPCommutative]>; 255def X86sub_flag : SDNode<"X86ISD::SUB", SDTBinaryArithWithFlags>; 256def X86smul_flag : SDNode<"X86ISD::SMUL", SDTBinaryArithWithFlags, 257 [SDNPCommutative]>; 258def X86umul_flag : SDNode<"X86ISD::UMUL", SDT2ResultBinaryArithWithFlags, 259 [SDNPCommutative]>; 260def X86adc_flag : SDNode<"X86ISD::ADC", SDTBinaryArithWithFlagsInOut>; 261def X86sbb_flag : SDNode<"X86ISD::SBB", SDTBinaryArithWithFlagsInOut>; 262 263def X86or_flag : SDNode<"X86ISD::OR", SDTBinaryArithWithFlags, 264 [SDNPCommutative]>; 265def X86xor_flag : SDNode<"X86ISD::XOR", SDTBinaryArithWithFlags, 266 [SDNPCommutative]>; 267def X86and_flag : SDNode<"X86ISD::AND", SDTBinaryArithWithFlags, 268 [SDNPCommutative]>; 269 270def X86lock_add : SDNode<"X86ISD::LADD", SDTLockBinaryArithWithFlags, 271 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 272 SDNPMemOperand]>; 273def X86lock_sub : SDNode<"X86ISD::LSUB", SDTLockBinaryArithWithFlags, 274 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 275 SDNPMemOperand]>; 276def X86lock_or : SDNode<"X86ISD::LOR", SDTLockBinaryArithWithFlags, 277 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 278 SDNPMemOperand]>; 279def X86lock_xor : SDNode<"X86ISD::LXOR", SDTLockBinaryArithWithFlags, 280 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 281 SDNPMemOperand]>; 282def X86lock_and : SDNode<"X86ISD::LAND", SDTLockBinaryArithWithFlags, 283 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, 284 SDNPMemOperand]>; 285 286def X86bextr : SDNode<"X86ISD::BEXTR", SDTIntBinOp>; 287 288def X86bzhi : SDNode<"X86ISD::BZHI", SDTIntBinOp>; 289 290def X86pdep : SDNode<"X86ISD::PDEP", SDTIntBinOp>; 291def X86pext : SDNode<"X86ISD::PEXT", SDTIntBinOp>; 292 293def X86mul_imm : SDNode<"X86ISD::MUL_IMM", SDTIntBinOp>; 294 295def X86WinAlloca : SDNode<"X86ISD::WIN_ALLOCA", SDT_X86WIN_ALLOCA, 296 [SDNPHasChain, SDNPOutGlue]>; 297 298def X86SegAlloca : SDNode<"X86ISD::SEG_ALLOCA", SDT_X86SEG_ALLOCA, 299 [SDNPHasChain]>; 300 301def X86ProbedAlloca : SDNode<"X86ISD::PROBED_ALLOCA", SDT_X86PROBED_ALLOCA, 302 [SDNPHasChain]>; 303 304def X86TLSCall : SDNode<"X86ISD::TLSCALL", SDT_X86TLSCALL, 305 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; 306 307def X86lwpins : SDNode<"X86ISD::LWPINS", 308 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 309 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 310 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPSideEffect]>; 311 312def X86umwait : SDNode<"X86ISD::UMWAIT", 313 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 314 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 315 [SDNPHasChain, SDNPSideEffect]>; 316 317def X86tpause : SDNode<"X86ISD::TPAUSE", 318 SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisInt<1>, 319 SDTCisVT<2, i32>, SDTCisVT<3, i32>]>, 320 [SDNPHasChain, SDNPSideEffect]>; 321 322def X86enqcmd : SDNode<"X86ISD::ENQCMD", SDT_X86ENQCMD, 323 [SDNPHasChain, SDNPSideEffect]>; 324def X86enqcmds : SDNode<"X86ISD::ENQCMDS", SDT_X86ENQCMD, 325 [SDNPHasChain, SDNPSideEffect]>; 326 327//===----------------------------------------------------------------------===// 328// X86 Operand Definitions. 329// 330 331// A version of ptr_rc which excludes SP, ESP, and RSP. This is used for 332// the index operand of an address, to conform to x86 encoding restrictions. 333def ptr_rc_nosp : PointerLikeRegClass<1>; 334 335// *mem - Operand definitions for the funky X86 addressing mode operands. 336// 337def X86MemAsmOperand : AsmOperandClass { 338 let Name = "Mem"; 339} 340let RenderMethod = "addMemOperands", SuperClasses = [X86MemAsmOperand] in { 341 def X86Mem8AsmOperand : AsmOperandClass { let Name = "Mem8"; } 342 def X86Mem16AsmOperand : AsmOperandClass { let Name = "Mem16"; } 343 def X86Mem32AsmOperand : AsmOperandClass { let Name = "Mem32"; } 344 def X86Mem64AsmOperand : AsmOperandClass { let Name = "Mem64"; } 345 def X86Mem80AsmOperand : AsmOperandClass { let Name = "Mem80"; } 346 def X86Mem128AsmOperand : AsmOperandClass { let Name = "Mem128"; } 347 def X86Mem256AsmOperand : AsmOperandClass { let Name = "Mem256"; } 348 def X86Mem512AsmOperand : AsmOperandClass { let Name = "Mem512"; } 349 // Gather mem operands 350 def X86Mem64_RC128Operand : AsmOperandClass { let Name = "Mem64_RC128"; } 351 def X86Mem128_RC128Operand : AsmOperandClass { let Name = "Mem128_RC128"; } 352 def X86Mem256_RC128Operand : AsmOperandClass { let Name = "Mem256_RC128"; } 353 def X86Mem128_RC256Operand : AsmOperandClass { let Name = "Mem128_RC256"; } 354 def X86Mem256_RC256Operand : AsmOperandClass { let Name = "Mem256_RC256"; } 355 356 def X86Mem64_RC128XOperand : AsmOperandClass { let Name = "Mem64_RC128X"; } 357 def X86Mem128_RC128XOperand : AsmOperandClass { let Name = "Mem128_RC128X"; } 358 def X86Mem256_RC128XOperand : AsmOperandClass { let Name = "Mem256_RC128X"; } 359 def X86Mem128_RC256XOperand : AsmOperandClass { let Name = "Mem128_RC256X"; } 360 def X86Mem256_RC256XOperand : AsmOperandClass { let Name = "Mem256_RC256X"; } 361 def X86Mem512_RC256XOperand : AsmOperandClass { let Name = "Mem512_RC256X"; } 362 def X86Mem256_RC512Operand : AsmOperandClass { let Name = "Mem256_RC512"; } 363 def X86Mem512_RC512Operand : AsmOperandClass { let Name = "Mem512_RC512"; } 364 365 def X86SibMemOperand : AsmOperandClass { let Name = "SibMem"; } 366} 367 368def X86AbsMemAsmOperand : AsmOperandClass { 369 let Name = "AbsMem"; 370 let SuperClasses = [X86MemAsmOperand]; 371} 372 373class X86MemOperand<string printMethod, 374 AsmOperandClass parserMatchClass = X86MemAsmOperand> : Operand<iPTR> { 375 let PrintMethod = printMethod; 376 let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, SEGMENT_REG); 377 let ParserMatchClass = parserMatchClass; 378 let OperandType = "OPERAND_MEMORY"; 379} 380 381// Gather mem operands 382class X86VMemOperand<RegisterClass RC, string printMethod, 383 AsmOperandClass parserMatchClass> 384 : X86MemOperand<printMethod, parserMatchClass> { 385 let MIOperandInfo = (ops ptr_rc, i8imm, RC, i32imm, SEGMENT_REG); 386} 387 388def anymem : X86MemOperand<"printMemReference">; 389def X86any_fcmp : PatFrags<(ops node:$lhs, node:$rhs), 390 [(X86strict_fcmp node:$lhs, node:$rhs), 391 (X86fcmp node:$lhs, node:$rhs)]>; 392 393// FIXME: Right now we allow any size during parsing, but we might want to 394// restrict to only unsized memory. 395def opaquemem : X86MemOperand<"printMemReference">; 396 397def sibmem: X86MemOperand<"printMemReference", X86SibMemOperand>; 398 399def i8mem : X86MemOperand<"printbytemem", X86Mem8AsmOperand>; 400def i16mem : X86MemOperand<"printwordmem", X86Mem16AsmOperand>; 401def i32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; 402def i64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; 403def i128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand>; 404def i256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand>; 405def i512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand>; 406def f32mem : X86MemOperand<"printdwordmem", X86Mem32AsmOperand>; 407def f64mem : X86MemOperand<"printqwordmem", X86Mem64AsmOperand>; 408def f80mem : X86MemOperand<"printtbytemem", X86Mem80AsmOperand>; 409def f128mem : X86MemOperand<"printxmmwordmem", X86Mem128AsmOperand>; 410def f256mem : X86MemOperand<"printymmwordmem", X86Mem256AsmOperand>; 411def f512mem : X86MemOperand<"printzmmwordmem", X86Mem512AsmOperand>; 412 413// Gather mem operands 414def vx64mem : X86VMemOperand<VR128, "printqwordmem", X86Mem64_RC128Operand>; 415def vx128mem : X86VMemOperand<VR128, "printxmmwordmem", X86Mem128_RC128Operand>; 416def vx256mem : X86VMemOperand<VR128, "printymmwordmem", X86Mem256_RC128Operand>; 417def vy128mem : X86VMemOperand<VR256, "printxmmwordmem", X86Mem128_RC256Operand>; 418def vy256mem : X86VMemOperand<VR256, "printymmwordmem", X86Mem256_RC256Operand>; 419 420def vx64xmem : X86VMemOperand<VR128X, "printqwordmem", X86Mem64_RC128XOperand>; 421def vx128xmem : X86VMemOperand<VR128X, "printxmmwordmem", X86Mem128_RC128XOperand>; 422def vx256xmem : X86VMemOperand<VR128X, "printymmwordmem", X86Mem256_RC128XOperand>; 423def vy128xmem : X86VMemOperand<VR256X, "printxmmwordmem", X86Mem128_RC256XOperand>; 424def vy256xmem : X86VMemOperand<VR256X, "printymmwordmem", X86Mem256_RC256XOperand>; 425def vy512xmem : X86VMemOperand<VR256X, "printzmmwordmem", X86Mem512_RC256XOperand>; 426def vz256mem : X86VMemOperand<VR512, "printymmwordmem", X86Mem256_RC512Operand>; 427def vz512mem : X86VMemOperand<VR512, "printzmmwordmem", X86Mem512_RC512Operand>; 428 429// A version of i8mem for use on x86-64 and x32 that uses a NOREX GPR instead 430// of a plain GPR, so that it doesn't potentially require a REX prefix. 431def ptr_rc_norex : PointerLikeRegClass<2>; 432def ptr_rc_norex_nosp : PointerLikeRegClass<3>; 433 434def i8mem_NOREX : Operand<iPTR> { 435 let PrintMethod = "printbytemem"; 436 let MIOperandInfo = (ops ptr_rc_norex, i8imm, ptr_rc_norex_nosp, i32imm, 437 SEGMENT_REG); 438 let ParserMatchClass = X86Mem8AsmOperand; 439 let OperandType = "OPERAND_MEMORY"; 440} 441 442// GPRs available for tailcall. 443// It represents GR32_TC, GR64_TC or GR64_TCW64. 444def ptr_rc_tailcall : PointerLikeRegClass<4>; 445 446// Special i32mem for addresses of load folding tail calls. These are not 447// allowed to use callee-saved registers since they must be scheduled 448// after callee-saved register are popped. 449def i32mem_TC : Operand<i32> { 450 let PrintMethod = "printdwordmem"; 451 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, ptr_rc_tailcall, 452 i32imm, SEGMENT_REG); 453 let ParserMatchClass = X86Mem32AsmOperand; 454 let OperandType = "OPERAND_MEMORY"; 455} 456 457// Special i64mem for addresses of load folding tail calls. These are not 458// allowed to use callee-saved registers since they must be scheduled 459// after callee-saved register are popped. 460def i64mem_TC : Operand<i64> { 461 let PrintMethod = "printqwordmem"; 462 let MIOperandInfo = (ops ptr_rc_tailcall, i8imm, 463 ptr_rc_tailcall, i32imm, SEGMENT_REG); 464 let ParserMatchClass = X86Mem64AsmOperand; 465 let OperandType = "OPERAND_MEMORY"; 466} 467 468// Special parser to detect 16-bit mode to select 16-bit displacement. 469def X86AbsMem16AsmOperand : AsmOperandClass { 470 let Name = "AbsMem16"; 471 let RenderMethod = "addAbsMemOperands"; 472 let SuperClasses = [X86AbsMemAsmOperand]; 473} 474 475// Branch targets print as pc-relative values. 476class BranchTargetOperand<ValueType ty> : Operand<ty> { 477 let OperandType = "OPERAND_PCREL"; 478 let PrintMethod = "printPCRelImm"; 479 let ParserMatchClass = X86AbsMemAsmOperand; 480} 481 482def i32imm_brtarget : BranchTargetOperand<i32>; 483def i16imm_brtarget : BranchTargetOperand<i16>; 484 485// 64-bits but only 32 bits are significant, and those bits are treated as being 486// pc relative. 487def i64i32imm_brtarget : BranchTargetOperand<i64>; 488 489def brtarget : BranchTargetOperand<OtherVT>; 490def brtarget8 : BranchTargetOperand<OtherVT>; 491def brtarget16 : BranchTargetOperand<OtherVT> { 492 let ParserMatchClass = X86AbsMem16AsmOperand; 493} 494def brtarget32 : BranchTargetOperand<OtherVT>; 495 496let RenderMethod = "addSrcIdxOperands" in { 497 def X86SrcIdx8Operand : AsmOperandClass { 498 let Name = "SrcIdx8"; 499 let SuperClasses = [X86Mem8AsmOperand]; 500 } 501 def X86SrcIdx16Operand : AsmOperandClass { 502 let Name = "SrcIdx16"; 503 let SuperClasses = [X86Mem16AsmOperand]; 504 } 505 def X86SrcIdx32Operand : AsmOperandClass { 506 let Name = "SrcIdx32"; 507 let SuperClasses = [X86Mem32AsmOperand]; 508 } 509 def X86SrcIdx64Operand : AsmOperandClass { 510 let Name = "SrcIdx64"; 511 let SuperClasses = [X86Mem64AsmOperand]; 512 } 513} // RenderMethod = "addSrcIdxOperands" 514 515let RenderMethod = "addDstIdxOperands" in { 516 def X86DstIdx8Operand : AsmOperandClass { 517 let Name = "DstIdx8"; 518 let SuperClasses = [X86Mem8AsmOperand]; 519 } 520 def X86DstIdx16Operand : AsmOperandClass { 521 let Name = "DstIdx16"; 522 let SuperClasses = [X86Mem16AsmOperand]; 523 } 524 def X86DstIdx32Operand : AsmOperandClass { 525 let Name = "DstIdx32"; 526 let SuperClasses = [X86Mem32AsmOperand]; 527 } 528 def X86DstIdx64Operand : AsmOperandClass { 529 let Name = "DstIdx64"; 530 let SuperClasses = [X86Mem64AsmOperand]; 531 } 532} // RenderMethod = "addDstIdxOperands" 533 534let RenderMethod = "addMemOffsOperands" in { 535 def X86MemOffs16_8AsmOperand : AsmOperandClass { 536 let Name = "MemOffs16_8"; 537 let SuperClasses = [X86Mem8AsmOperand]; 538 } 539 def X86MemOffs16_16AsmOperand : AsmOperandClass { 540 let Name = "MemOffs16_16"; 541 let SuperClasses = [X86Mem16AsmOperand]; 542 } 543 def X86MemOffs16_32AsmOperand : AsmOperandClass { 544 let Name = "MemOffs16_32"; 545 let SuperClasses = [X86Mem32AsmOperand]; 546 } 547 def X86MemOffs32_8AsmOperand : AsmOperandClass { 548 let Name = "MemOffs32_8"; 549 let SuperClasses = [X86Mem8AsmOperand]; 550 } 551 def X86MemOffs32_16AsmOperand : AsmOperandClass { 552 let Name = "MemOffs32_16"; 553 let SuperClasses = [X86Mem16AsmOperand]; 554 } 555 def X86MemOffs32_32AsmOperand : AsmOperandClass { 556 let Name = "MemOffs32_32"; 557 let SuperClasses = [X86Mem32AsmOperand]; 558 } 559 def X86MemOffs32_64AsmOperand : AsmOperandClass { 560 let Name = "MemOffs32_64"; 561 let SuperClasses = [X86Mem64AsmOperand]; 562 } 563 def X86MemOffs64_8AsmOperand : AsmOperandClass { 564 let Name = "MemOffs64_8"; 565 let SuperClasses = [X86Mem8AsmOperand]; 566 } 567 def X86MemOffs64_16AsmOperand : AsmOperandClass { 568 let Name = "MemOffs64_16"; 569 let SuperClasses = [X86Mem16AsmOperand]; 570 } 571 def X86MemOffs64_32AsmOperand : AsmOperandClass { 572 let Name = "MemOffs64_32"; 573 let SuperClasses = [X86Mem32AsmOperand]; 574 } 575 def X86MemOffs64_64AsmOperand : AsmOperandClass { 576 let Name = "MemOffs64_64"; 577 let SuperClasses = [X86Mem64AsmOperand]; 578 } 579} // RenderMethod = "addMemOffsOperands" 580 581class X86SrcIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 582 : X86MemOperand<printMethod, parserMatchClass> { 583 let MIOperandInfo = (ops ptr_rc, SEGMENT_REG); 584} 585 586class X86DstIdxOperand<string printMethod, AsmOperandClass parserMatchClass> 587 : X86MemOperand<printMethod, parserMatchClass> { 588 let MIOperandInfo = (ops ptr_rc); 589} 590 591def srcidx8 : X86SrcIdxOperand<"printSrcIdx8", X86SrcIdx8Operand>; 592def srcidx16 : X86SrcIdxOperand<"printSrcIdx16", X86SrcIdx16Operand>; 593def srcidx32 : X86SrcIdxOperand<"printSrcIdx32", X86SrcIdx32Operand>; 594def srcidx64 : X86SrcIdxOperand<"printSrcIdx64", X86SrcIdx64Operand>; 595def dstidx8 : X86DstIdxOperand<"printDstIdx8", X86DstIdx8Operand>; 596def dstidx16 : X86DstIdxOperand<"printDstIdx16", X86DstIdx16Operand>; 597def dstidx32 : X86DstIdxOperand<"printDstIdx32", X86DstIdx32Operand>; 598def dstidx64 : X86DstIdxOperand<"printDstIdx64", X86DstIdx64Operand>; 599 600class X86MemOffsOperand<Operand immOperand, string printMethod, 601 AsmOperandClass parserMatchClass> 602 : X86MemOperand<printMethod, parserMatchClass> { 603 let MIOperandInfo = (ops immOperand, SEGMENT_REG); 604} 605 606def offset16_8 : X86MemOffsOperand<i16imm, "printMemOffs8", 607 X86MemOffs16_8AsmOperand>; 608def offset16_16 : X86MemOffsOperand<i16imm, "printMemOffs16", 609 X86MemOffs16_16AsmOperand>; 610def offset16_32 : X86MemOffsOperand<i16imm, "printMemOffs32", 611 X86MemOffs16_32AsmOperand>; 612def offset32_8 : X86MemOffsOperand<i32imm, "printMemOffs8", 613 X86MemOffs32_8AsmOperand>; 614def offset32_16 : X86MemOffsOperand<i32imm, "printMemOffs16", 615 X86MemOffs32_16AsmOperand>; 616def offset32_32 : X86MemOffsOperand<i32imm, "printMemOffs32", 617 X86MemOffs32_32AsmOperand>; 618def offset32_64 : X86MemOffsOperand<i32imm, "printMemOffs64", 619 X86MemOffs32_64AsmOperand>; 620def offset64_8 : X86MemOffsOperand<i64imm, "printMemOffs8", 621 X86MemOffs64_8AsmOperand>; 622def offset64_16 : X86MemOffsOperand<i64imm, "printMemOffs16", 623 X86MemOffs64_16AsmOperand>; 624def offset64_32 : X86MemOffsOperand<i64imm, "printMemOffs32", 625 X86MemOffs64_32AsmOperand>; 626def offset64_64 : X86MemOffsOperand<i64imm, "printMemOffs64", 627 X86MemOffs64_64AsmOperand>; 628 629def ccode : Operand<i8> { 630 let PrintMethod = "printCondCode"; 631 let OperandNamespace = "X86"; 632 let OperandType = "OPERAND_COND_CODE"; 633} 634 635class ImmSExtAsmOperandClass : AsmOperandClass { 636 let SuperClasses = [ImmAsmOperand]; 637 let RenderMethod = "addImmOperands"; 638} 639 640def X86GR32orGR64AsmOperand : AsmOperandClass { 641 let Name = "GR32orGR64"; 642} 643def GR32orGR64 : RegisterOperand<GR32> { 644 let ParserMatchClass = X86GR32orGR64AsmOperand; 645} 646 647def X86GR16orGR32orGR64AsmOperand : AsmOperandClass { 648 let Name = "GR16orGR32orGR64"; 649} 650def GR16orGR32orGR64 : RegisterOperand<GR16> { 651 let ParserMatchClass = X86GR16orGR32orGR64AsmOperand; 652} 653 654def AVX512RCOperand : AsmOperandClass { 655 let Name = "AVX512RC"; 656} 657def AVX512RC : Operand<i32> { 658 let PrintMethod = "printRoundingControl"; 659 let OperandNamespace = "X86"; 660 let OperandType = "OPERAND_ROUNDING_CONTROL"; 661 let ParserMatchClass = AVX512RCOperand; 662} 663 664// Sign-extended immediate classes. We don't need to define the full lattice 665// here because there is no instruction with an ambiguity between ImmSExti64i32 666// and ImmSExti32i8. 667// 668// The strange ranges come from the fact that the assembler always works with 669// 64-bit immediates, but for a 16-bit target value we want to accept both "-1" 670// (which will be a -1ULL), and "0xFF" (-1 in 16-bits). 671 672// [0, 0x7FFFFFFF] | 673// [0xFFFFFFFF80000000, 0xFFFFFFFFFFFFFFFF] 674def ImmSExti64i32AsmOperand : ImmSExtAsmOperandClass { 675 let Name = "ImmSExti64i32"; 676} 677 678// [0, 0x0000007F] | [0x000000000000FF80, 0x000000000000FFFF] | 679// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 680def ImmSExti16i8AsmOperand : ImmSExtAsmOperandClass { 681 let Name = "ImmSExti16i8"; 682 let SuperClasses = [ImmSExti64i32AsmOperand]; 683} 684 685// [0, 0x0000007F] | [0x00000000FFFFFF80, 0x00000000FFFFFFFF] | 686// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 687def ImmSExti32i8AsmOperand : ImmSExtAsmOperandClass { 688 let Name = "ImmSExti32i8"; 689} 690 691// [0, 0x0000007F] | 692// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 693def ImmSExti64i8AsmOperand : ImmSExtAsmOperandClass { 694 let Name = "ImmSExti64i8"; 695 let SuperClasses = [ImmSExti16i8AsmOperand, ImmSExti32i8AsmOperand, 696 ImmSExti64i32AsmOperand]; 697} 698 699// 4-bit immediate used by some XOP instructions 700// [0, 0xF] 701def ImmUnsignedi4AsmOperand : AsmOperandClass { 702 let Name = "ImmUnsignedi4"; 703 let RenderMethod = "addImmOperands"; 704 let DiagnosticType = "InvalidImmUnsignedi4"; 705} 706 707// Unsigned immediate used by SSE/AVX instructions 708// [0, 0xFF] 709// [0xFFFFFFFFFFFFFF80, 0xFFFFFFFFFFFFFFFF] 710def ImmUnsignedi8AsmOperand : AsmOperandClass { 711 let Name = "ImmUnsignedi8"; 712 let RenderMethod = "addImmOperands"; 713} 714 715// A couple of more descriptive operand definitions. 716// 16-bits but only 8 bits are significant. 717def i16i8imm : Operand<i16> { 718 let ParserMatchClass = ImmSExti16i8AsmOperand; 719 let OperandType = "OPERAND_IMMEDIATE"; 720} 721// 32-bits but only 8 bits are significant. 722def i32i8imm : Operand<i32> { 723 let ParserMatchClass = ImmSExti32i8AsmOperand; 724 let OperandType = "OPERAND_IMMEDIATE"; 725} 726 727// 64-bits but only 32 bits are significant. 728def i64i32imm : Operand<i64> { 729 let ParserMatchClass = ImmSExti64i32AsmOperand; 730 let OperandType = "OPERAND_IMMEDIATE"; 731} 732 733// 64-bits but only 8 bits are significant. 734def i64i8imm : Operand<i64> { 735 let ParserMatchClass = ImmSExti64i8AsmOperand; 736 let OperandType = "OPERAND_IMMEDIATE"; 737} 738 739// Unsigned 4-bit immediate used by some XOP instructions. 740def u4imm : Operand<i8> { 741 let PrintMethod = "printU8Imm"; 742 let ParserMatchClass = ImmUnsignedi4AsmOperand; 743 let OperandType = "OPERAND_IMMEDIATE"; 744} 745 746// Unsigned 8-bit immediate used by SSE/AVX instructions. 747def u8imm : Operand<i8> { 748 let PrintMethod = "printU8Imm"; 749 let ParserMatchClass = ImmUnsignedi8AsmOperand; 750 let OperandType = "OPERAND_IMMEDIATE"; 751} 752 753// 16-bit immediate but only 8-bits are significant and they are unsigned. 754// Used by BT instructions. 755def i16u8imm : Operand<i16> { 756 let PrintMethod = "printU8Imm"; 757 let ParserMatchClass = ImmUnsignedi8AsmOperand; 758 let OperandType = "OPERAND_IMMEDIATE"; 759} 760 761// 32-bit immediate but only 8-bits are significant and they are unsigned. 762// Used by some SSE/AVX instructions that use intrinsics. 763def i32u8imm : Operand<i32> { 764 let PrintMethod = "printU8Imm"; 765 let ParserMatchClass = ImmUnsignedi8AsmOperand; 766 let OperandType = "OPERAND_IMMEDIATE"; 767} 768 769// 64-bit immediate but only 8-bits are significant and they are unsigned. 770// Used by BT instructions. 771def i64u8imm : Operand<i64> { 772 let PrintMethod = "printU8Imm"; 773 let ParserMatchClass = ImmUnsignedi8AsmOperand; 774 let OperandType = "OPERAND_IMMEDIATE"; 775} 776 777def lea64_32mem : Operand<i32> { 778 let PrintMethod = "printMemReference"; 779 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 780 let ParserMatchClass = X86MemAsmOperand; 781} 782 783// Memory operands that use 64-bit pointers in both ILP32 and LP64. 784def lea64mem : Operand<i64> { 785 let PrintMethod = "printMemReference"; 786 let MIOperandInfo = (ops GR64, i8imm, GR64_NOSP, i32imm, SEGMENT_REG); 787 let ParserMatchClass = X86MemAsmOperand; 788} 789 790let RenderMethod = "addMaskPairOperands" in { 791 def VK1PairAsmOperand : AsmOperandClass { let Name = "VK1Pair"; } 792 def VK2PairAsmOperand : AsmOperandClass { let Name = "VK2Pair"; } 793 def VK4PairAsmOperand : AsmOperandClass { let Name = "VK4Pair"; } 794 def VK8PairAsmOperand : AsmOperandClass { let Name = "VK8Pair"; } 795 def VK16PairAsmOperand : AsmOperandClass { let Name = "VK16Pair"; } 796} 797 798def VK1Pair : RegisterOperand<VK1PAIR, "printVKPair"> { 799 let ParserMatchClass = VK1PairAsmOperand; 800} 801 802def VK2Pair : RegisterOperand<VK2PAIR, "printVKPair"> { 803 let ParserMatchClass = VK2PairAsmOperand; 804} 805 806def VK4Pair : RegisterOperand<VK4PAIR, "printVKPair"> { 807 let ParserMatchClass = VK4PairAsmOperand; 808} 809 810def VK8Pair : RegisterOperand<VK8PAIR, "printVKPair"> { 811 let ParserMatchClass = VK8PairAsmOperand; 812} 813 814def VK16Pair : RegisterOperand<VK16PAIR, "printVKPair"> { 815 let ParserMatchClass = VK16PairAsmOperand; 816} 817 818//===----------------------------------------------------------------------===// 819// X86 Complex Pattern Definitions. 820// 821 822// Define X86-specific addressing mode. 823def addr : ComplexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>; 824def lea32addr : ComplexPattern<i32, 5, "selectLEAAddr", 825 [add, sub, mul, X86mul_imm, shl, or, frameindex], 826 []>; 827// In 64-bit mode 32-bit LEAs can use RIP-relative addressing. 828def lea64_32addr : ComplexPattern<i32, 5, "selectLEA64_32Addr", 829 [add, sub, mul, X86mul_imm, shl, or, 830 frameindex, X86WrapperRIP], 831 []>; 832 833def tls32addr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 834 [tglobaltlsaddr], []>; 835 836def tls32baseaddr : ComplexPattern<i32, 5, "selectTLSADDRAddr", 837 [tglobaltlsaddr], []>; 838 839def lea64addr : ComplexPattern<i64, 5, "selectLEAAddr", 840 [add, sub, mul, X86mul_imm, shl, or, frameindex, 841 X86WrapperRIP], []>; 842 843def tls64addr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 844 [tglobaltlsaddr], []>; 845 846def tls64baseaddr : ComplexPattern<i64, 5, "selectTLSADDRAddr", 847 [tglobaltlsaddr], []>; 848 849def vectoraddr : ComplexPattern<iPTR, 5, "selectVectorAddr", [],[SDNPWantParent]>; 850 851// A relocatable immediate is an operand that can be relocated by the linker to 852// an immediate, such as a regular symbol in non-PIC code. 853def relocImm : ComplexPattern<iAny, 1, "selectRelocImm", 854 [X86Wrapper], [], 0>; 855 856//===----------------------------------------------------------------------===// 857// X86 Instruction Predicate Definitions. 858def TruePredicate : Predicate<"true">; 859 860def HasCMov : Predicate<"Subtarget->hasCMov()">; 861def NoCMov : Predicate<"!Subtarget->hasCMov()">; 862 863def HasMMX : Predicate<"Subtarget->hasMMX()">; 864def Has3DNow : Predicate<"Subtarget->has3DNow()">; 865def Has3DNowA : Predicate<"Subtarget->has3DNowA()">; 866def HasSSE1 : Predicate<"Subtarget->hasSSE1()">; 867def UseSSE1 : Predicate<"Subtarget->hasSSE1() && !Subtarget->hasAVX()">; 868def HasSSE2 : Predicate<"Subtarget->hasSSE2()">; 869def UseSSE2 : Predicate<"Subtarget->hasSSE2() && !Subtarget->hasAVX()">; 870def HasSSE3 : Predicate<"Subtarget->hasSSE3()">; 871def UseSSE3 : Predicate<"Subtarget->hasSSE3() && !Subtarget->hasAVX()">; 872def HasSSSE3 : Predicate<"Subtarget->hasSSSE3()">; 873def UseSSSE3 : Predicate<"Subtarget->hasSSSE3() && !Subtarget->hasAVX()">; 874def HasSSE41 : Predicate<"Subtarget->hasSSE41()">; 875def NoSSE41 : Predicate<"!Subtarget->hasSSE41()">; 876def UseSSE41 : Predicate<"Subtarget->hasSSE41() && !Subtarget->hasAVX()">; 877def HasSSE42 : Predicate<"Subtarget->hasSSE42()">; 878def UseSSE42 : Predicate<"Subtarget->hasSSE42() && !Subtarget->hasAVX()">; 879def HasSSE4A : Predicate<"Subtarget->hasSSE4A()">; 880def NoAVX : Predicate<"!Subtarget->hasAVX()">; 881def HasAVX : Predicate<"Subtarget->hasAVX()">; 882def HasAVX2 : Predicate<"Subtarget->hasAVX2()">; 883def HasAVX1Only : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX2()">; 884def HasAVX512 : Predicate<"Subtarget->hasAVX512()">; 885def UseAVX : Predicate<"Subtarget->hasAVX() && !Subtarget->hasAVX512()">; 886def UseAVX2 : Predicate<"Subtarget->hasAVX2() && !Subtarget->hasAVX512()">; 887def NoAVX512 : Predicate<"!Subtarget->hasAVX512()">; 888def HasCDI : Predicate<"Subtarget->hasCDI()">; 889def HasVPOPCNTDQ : Predicate<"Subtarget->hasVPOPCNTDQ()">; 890def HasPFI : Predicate<"Subtarget->hasPFI()">; 891def HasERI : Predicate<"Subtarget->hasERI()">; 892def HasDQI : Predicate<"Subtarget->hasDQI()">; 893def NoDQI : Predicate<"!Subtarget->hasDQI()">; 894def HasBWI : Predicate<"Subtarget->hasBWI()">; 895def NoBWI : Predicate<"!Subtarget->hasBWI()">; 896def HasVLX : Predicate<"Subtarget->hasVLX()">; 897def NoVLX : Predicate<"!Subtarget->hasVLX()">; 898def NoVLX_Or_NoBWI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasBWI()">; 899def NoVLX_Or_NoDQI : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasDQI()">; 900def PKU : Predicate<"Subtarget->hasPKU()">; 901def HasVNNI : Predicate<"Subtarget->hasVNNI()">; 902def HasVP2INTERSECT : Predicate<"Subtarget->hasVP2INTERSECT()">; 903def HasBF16 : Predicate<"Subtarget->hasBF16()">; 904 905def HasBITALG : Predicate<"Subtarget->hasBITALG()">; 906def HasPOPCNT : Predicate<"Subtarget->hasPOPCNT()">; 907def HasAES : Predicate<"Subtarget->hasAES()">; 908def HasVAES : Predicate<"Subtarget->hasVAES()">; 909def NoVLX_Or_NoVAES : Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVAES()">; 910def HasFXSR : Predicate<"Subtarget->hasFXSR()">; 911def HasXSAVE : Predicate<"Subtarget->hasXSAVE()">; 912def HasXSAVEOPT : Predicate<"Subtarget->hasXSAVEOPT()">; 913def HasXSAVEC : Predicate<"Subtarget->hasXSAVEC()">; 914def HasXSAVES : Predicate<"Subtarget->hasXSAVES()">; 915def HasPCLMUL : Predicate<"Subtarget->hasPCLMUL()">; 916def NoVLX_Or_NoVPCLMULQDQ : 917 Predicate<"!Subtarget->hasVLX() || !Subtarget->hasVPCLMULQDQ()">; 918def HasVPCLMULQDQ : Predicate<"Subtarget->hasVPCLMULQDQ()">; 919def HasGFNI : Predicate<"Subtarget->hasGFNI()">; 920def HasFMA : Predicate<"Subtarget->hasFMA()">; 921def HasFMA4 : Predicate<"Subtarget->hasFMA4()">; 922def NoFMA4 : Predicate<"!Subtarget->hasFMA4()">; 923def HasXOP : Predicate<"Subtarget->hasXOP()">; 924def HasTBM : Predicate<"Subtarget->hasTBM()">; 925def NoTBM : Predicate<"!Subtarget->hasTBM()">; 926def HasLWP : Predicate<"Subtarget->hasLWP()">; 927def HasMOVBE : Predicate<"Subtarget->hasMOVBE()">; 928def HasRDRAND : Predicate<"Subtarget->hasRDRAND()">; 929def HasF16C : Predicate<"Subtarget->hasF16C()">; 930def HasFSGSBase : Predicate<"Subtarget->hasFSGSBase()">; 931def HasLZCNT : Predicate<"Subtarget->hasLZCNT()">; 932def HasBMI : Predicate<"Subtarget->hasBMI()">; 933def HasBMI2 : Predicate<"Subtarget->hasBMI2()">; 934def NoBMI2 : Predicate<"!Subtarget->hasBMI2()">; 935def HasVBMI : Predicate<"Subtarget->hasVBMI()">; 936def HasVBMI2 : Predicate<"Subtarget->hasVBMI2()">; 937def HasIFMA : Predicate<"Subtarget->hasIFMA()">; 938def HasRTM : Predicate<"Subtarget->hasRTM()">; 939def HasADX : Predicate<"Subtarget->hasADX()">; 940def HasSHA : Predicate<"Subtarget->hasSHA()">; 941def HasSGX : Predicate<"Subtarget->hasSGX()">; 942def HasRDSEED : Predicate<"Subtarget->hasRDSEED()">; 943def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">; 944def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">; 945def HasPrefetchW : Predicate<"Subtarget->hasPrefetchW()">; 946def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">; 947def HasLAHFSAHF : Predicate<"Subtarget->hasLAHFSAHF()">; 948def HasMWAITX : Predicate<"Subtarget->hasMWAITX()">; 949def HasCLZERO : Predicate<"Subtarget->hasCLZERO()">; 950def HasCLDEMOTE : Predicate<"Subtarget->hasCLDEMOTE()">; 951def HasMOVDIRI : Predicate<"Subtarget->hasMOVDIRI()">; 952def HasMOVDIR64B : Predicate<"Subtarget->hasMOVDIR64B()">; 953def HasPTWRITE : Predicate<"Subtarget->hasPTWRITE()">; 954def FPStackf32 : Predicate<"!Subtarget->hasSSE1()">; 955def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">; 956def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">; 957def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">; 958def HasCLWB : Predicate<"Subtarget->hasCLWB()">; 959def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">; 960def HasRDPID : Predicate<"Subtarget->hasRDPID()">; 961def HasWAITPKG : Predicate<"Subtarget->hasWAITPKG()">; 962def HasINVPCID : Predicate<"Subtarget->hasINVPCID()">; 963def HasCmpxchg8b : Predicate<"Subtarget->hasCmpxchg8b()">; 964def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">; 965def HasPCONFIG : Predicate<"Subtarget->hasPCONFIG()">; 966def HasENQCMD : Predicate<"Subtarget->hasENQCMD()">; 967def HasSERIALIZE : Predicate<"Subtarget->hasSERIALIZE()">; 968def HasTSXLDTRK : Predicate<"Subtarget->hasTSXLDTRK()">; 969def HasAMXTILE : Predicate<"Subtarget->hasAMXTILE()">; 970def HasAMXBF16 : Predicate<"Subtarget->hasAMXBF16()">; 971def HasAMXINT8 : Predicate<"Subtarget->hasAMXINT8()">; 972def Not64BitMode : Predicate<"!Subtarget->is64Bit()">, 973 AssemblerPredicate<(all_of (not Mode64Bit)), "Not 64-bit mode">; 974def In64BitMode : Predicate<"Subtarget->is64Bit()">, 975 AssemblerPredicate<(all_of Mode64Bit), "64-bit mode">; 976def IsLP64 : Predicate<"Subtarget->isTarget64BitLP64()">; 977def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">; 978def In16BitMode : Predicate<"Subtarget->is16Bit()">, 979 AssemblerPredicate<(all_of Mode16Bit), "16-bit mode">; 980def Not16BitMode : Predicate<"!Subtarget->is16Bit()">, 981 AssemblerPredicate<(all_of (not Mode16Bit)), "Not 16-bit mode">; 982def In32BitMode : Predicate<"Subtarget->is32Bit()">, 983 AssemblerPredicate<(all_of Mode32Bit), "32-bit mode">; 984def IsWin64 : Predicate<"Subtarget->isTargetWin64()">; 985def NotWin64 : Predicate<"!Subtarget->isTargetWin64()">; 986def NotWin64WithoutFP : Predicate<"!Subtarget->isTargetWin64() ||" 987 "Subtarget->getFrameLowering()->hasFP(*MF)"> { 988 let RecomputePerFunction = 1; 989} 990def IsPS4 : Predicate<"Subtarget->isTargetPS4()">; 991def NotPS4 : Predicate<"!Subtarget->isTargetPS4()">; 992def IsNaCl : Predicate<"Subtarget->isTargetNaCl()">; 993def NotNaCl : Predicate<"!Subtarget->isTargetNaCl()">; 994def SmallCode : Predicate<"TM.getCodeModel() == CodeModel::Small">; 995def KernelCode : Predicate<"TM.getCodeModel() == CodeModel::Kernel">; 996def NearData : Predicate<"TM.getCodeModel() == CodeModel::Small ||" 997 "TM.getCodeModel() == CodeModel::Kernel">; 998def IsNotPIC : Predicate<"!TM.isPositionIndependent()">; 999 1000// We could compute these on a per-module basis but doing so requires accessing 1001// the Function object through the <Target>Subtarget and objections were raised 1002// to that (see post-commit review comments for r301750). 1003let RecomputePerFunction = 1 in { 1004 def OptForSize : Predicate<"shouldOptForSize(MF)">; 1005 def OptForMinSize : Predicate<"MF->getFunction().hasMinSize()">; 1006 def OptForSpeed : Predicate<"!shouldOptForSize(MF)">; 1007 def UseIncDec : Predicate<"!Subtarget->slowIncDec() || " 1008 "shouldOptForSize(MF)">; 1009 def NoSSE41_Or_OptForSize : Predicate<"shouldOptForSize(MF) || " 1010 "!Subtarget->hasSSE41()">; 1011} 1012 1013def CallImmAddr : Predicate<"Subtarget->isLegalToCallImmediateAddr()">; 1014def FavorMemIndirectCall : Predicate<"!Subtarget->slowTwoMemOps()">; 1015def HasFastMem32 : Predicate<"!Subtarget->isUnalignedMem32Slow()">; 1016def HasFastLZCNT : Predicate<"Subtarget->hasFastLZCNT()">; 1017def HasFastSHLDRotate : Predicate<"Subtarget->hasFastSHLDRotate()">; 1018def HasERMSB : Predicate<"Subtarget->hasERMSB()">; 1019def HasMFence : Predicate<"Subtarget->hasMFence()">; 1020def UseIndirectThunkCalls : Predicate<"Subtarget->useIndirectThunkCalls()">; 1021def NotUseIndirectThunkCalls : Predicate<"!Subtarget->useIndirectThunkCalls()">; 1022 1023//===----------------------------------------------------------------------===// 1024// X86 Instruction Format Definitions. 1025// 1026 1027include "X86InstrFormats.td" 1028 1029//===----------------------------------------------------------------------===// 1030// Pattern fragments. 1031// 1032 1033// X86 specific condition code. These correspond to CondCode in 1034// X86InstrInfo.h. They must be kept in synch. 1035def X86_COND_O : PatLeaf<(i8 0)>; 1036def X86_COND_NO : PatLeaf<(i8 1)>; 1037def X86_COND_B : PatLeaf<(i8 2)>; // alt. COND_C 1038def X86_COND_AE : PatLeaf<(i8 3)>; // alt. COND_NC 1039def X86_COND_E : PatLeaf<(i8 4)>; // alt. COND_Z 1040def X86_COND_NE : PatLeaf<(i8 5)>; // alt. COND_NZ 1041def X86_COND_BE : PatLeaf<(i8 6)>; // alt. COND_NA 1042def X86_COND_A : PatLeaf<(i8 7)>; // alt. COND_NBE 1043def X86_COND_S : PatLeaf<(i8 8)>; 1044def X86_COND_NS : PatLeaf<(i8 9)>; 1045def X86_COND_P : PatLeaf<(i8 10)>; // alt. COND_PE 1046def X86_COND_NP : PatLeaf<(i8 11)>; // alt. COND_PO 1047def X86_COND_L : PatLeaf<(i8 12)>; // alt. COND_NGE 1048def X86_COND_GE : PatLeaf<(i8 13)>; // alt. COND_NL 1049def X86_COND_LE : PatLeaf<(i8 14)>; // alt. COND_NG 1050def X86_COND_G : PatLeaf<(i8 15)>; // alt. COND_NLE 1051 1052def i16immSExt8 : ImmLeaf<i16, [{ return isInt<8>(Imm); }]>; 1053def i32immSExt8 : ImmLeaf<i32, [{ return isInt<8>(Imm); }]>; 1054def i64immSExt8 : ImmLeaf<i64, [{ return isInt<8>(Imm); }]>; 1055def i64immSExt32 : ImmLeaf<i64, [{ return isInt<32>(Imm); }]>; 1056 1057def i16relocImmSExt8 : PatLeaf<(i16 relocImm), [{ 1058 return isSExtAbsoluteSymbolRef(8, N); 1059}]>; 1060def i32relocImmSExt8 : PatLeaf<(i32 relocImm), [{ 1061 return isSExtAbsoluteSymbolRef(8, N); 1062}]>; 1063def i64relocImmSExt8 : PatLeaf<(i64 relocImm), [{ 1064 return isSExtAbsoluteSymbolRef(8, N); 1065}]>; 1066def i64relocImmSExt32 : PatLeaf<(i64 relocImm), [{ 1067 return isSExtAbsoluteSymbolRef(32, N); 1068}]>; 1069 1070// If we have multiple users of an immediate, it's much smaller to reuse 1071// the register, rather than encode the immediate in every instruction. 1072// This has the risk of increasing register pressure from stretched live 1073// ranges, however, the immediates should be trivial to rematerialize by 1074// the RA in the event of high register pressure. 1075// TODO : This is currently enabled for stores and binary ops. There are more 1076// cases for which this can be enabled, though this catches the bulk of the 1077// issues. 1078// TODO2 : This should really also be enabled under O2, but there's currently 1079// an issue with RA where we don't pull the constants into their users 1080// when we rematerialize them. I'll follow-up on enabling O2 after we fix that 1081// issue. 1082// TODO3 : This is currently limited to single basic blocks (DAG creation 1083// pulls block immediates to the top and merges them if necessary). 1084// Eventually, it would be nice to allow ConstantHoisting to merge constants 1085// globally for potentially added savings. 1086// 1087def imm_su : PatLeaf<(imm), [{ 1088 return !shouldAvoidImmediateInstFormsForSize(N); 1089}]>; 1090def i64immSExt32_su : PatLeaf<(i64immSExt32), [{ 1091 return !shouldAvoidImmediateInstFormsForSize(N); 1092}]>; 1093 1094def relocImm8_su : PatLeaf<(i8 relocImm), [{ 1095 return !shouldAvoidImmediateInstFormsForSize(N); 1096}]>; 1097def relocImm16_su : PatLeaf<(i16 relocImm), [{ 1098 return !shouldAvoidImmediateInstFormsForSize(N); 1099}]>; 1100def relocImm32_su : PatLeaf<(i32 relocImm), [{ 1101 return !shouldAvoidImmediateInstFormsForSize(N); 1102}]>; 1103 1104def i16relocImmSExt8_su : PatLeaf<(i16relocImmSExt8), [{ 1105 return !shouldAvoidImmediateInstFormsForSize(N); 1106}]>; 1107def i32relocImmSExt8_su : PatLeaf<(i32relocImmSExt8), [{ 1108 return !shouldAvoidImmediateInstFormsForSize(N); 1109}]>; 1110def i64relocImmSExt8_su : PatLeaf<(i64relocImmSExt8), [{ 1111 return !shouldAvoidImmediateInstFormsForSize(N); 1112}]>; 1113def i64relocImmSExt32_su : PatLeaf<(i64relocImmSExt32), [{ 1114 return !shouldAvoidImmediateInstFormsForSize(N); 1115}]>; 1116 1117def i16immSExt8_su : PatLeaf<(i16immSExt8), [{ 1118 return !shouldAvoidImmediateInstFormsForSize(N); 1119}]>; 1120def i32immSExt8_su : PatLeaf<(i32immSExt8), [{ 1121 return !shouldAvoidImmediateInstFormsForSize(N); 1122}]>; 1123def i64immSExt8_su : PatLeaf<(i64immSExt8), [{ 1124 return !shouldAvoidImmediateInstFormsForSize(N); 1125}]>; 1126 1127// i64immZExt32 predicate - True if the 64-bit immediate fits in a 32-bit 1128// unsigned field. 1129def i64immZExt32 : ImmLeaf<i64, [{ return isUInt<32>(Imm); }]>; 1130 1131def i64immZExt32SExt8 : ImmLeaf<i64, [{ 1132 return isUInt<32>(Imm) && isInt<8>(static_cast<int32_t>(Imm)); 1133}]>; 1134 1135// Helper fragments for loads. 1136 1137// It's safe to fold a zextload/extload from i1 as a regular i8 load. The 1138// upper bits are guaranteed to be zero and we were going to emit a MOV8rm 1139// which might get folded during peephole anyway. 1140def loadi8 : PatFrag<(ops node:$ptr), (i8 (unindexedload node:$ptr)), [{ 1141 LoadSDNode *LD = cast<LoadSDNode>(N); 1142 ISD::LoadExtType ExtType = LD->getExtensionType(); 1143 return ExtType == ISD::NON_EXTLOAD || ExtType == ISD::EXTLOAD || 1144 ExtType == ISD::ZEXTLOAD; 1145}]>; 1146 1147// It's always safe to treat a anyext i16 load as a i32 load if the i16 is 1148// known to be 32-bit aligned or better. Ditto for i8 to i16. 1149def loadi16 : PatFrag<(ops node:$ptr), (i16 (unindexedload node:$ptr)), [{ 1150 LoadSDNode *LD = cast<LoadSDNode>(N); 1151 ISD::LoadExtType ExtType = LD->getExtensionType(); 1152 if (ExtType == ISD::NON_EXTLOAD) 1153 return true; 1154 if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) 1155 return LD->getAlignment() >= 2 && LD->isSimple(); 1156 return false; 1157}]>; 1158 1159def loadi32 : PatFrag<(ops node:$ptr), (i32 (unindexedload node:$ptr)), [{ 1160 LoadSDNode *LD = cast<LoadSDNode>(N); 1161 ISD::LoadExtType ExtType = LD->getExtensionType(); 1162 if (ExtType == ISD::NON_EXTLOAD) 1163 return true; 1164 if (ExtType == ISD::EXTLOAD && EnablePromoteAnyextLoad) 1165 return LD->getAlignment() >= 4 && LD->isSimple(); 1166 return false; 1167}]>; 1168 1169def loadi64 : PatFrag<(ops node:$ptr), (i64 (load node:$ptr))>; 1170def loadf32 : PatFrag<(ops node:$ptr), (f32 (load node:$ptr))>; 1171def loadf64 : PatFrag<(ops node:$ptr), (f64 (load node:$ptr))>; 1172def loadf80 : PatFrag<(ops node:$ptr), (f80 (load node:$ptr))>; 1173def loadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr))>; 1174def alignedloadf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 1175 LoadSDNode *Ld = cast<LoadSDNode>(N); 1176 return Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1177}]>; 1178def memopf128 : PatFrag<(ops node:$ptr), (f128 (load node:$ptr)), [{ 1179 LoadSDNode *Ld = cast<LoadSDNode>(N); 1180 return Subtarget->hasSSEUnalignedMem() || 1181 Ld->getAlignment() >= Ld->getMemoryVT().getStoreSize(); 1182}]>; 1183 1184def sextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (sextloadi8 node:$ptr))>; 1185def sextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (sextloadi8 node:$ptr))>; 1186def sextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (sextloadi16 node:$ptr))>; 1187def sextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (sextloadi8 node:$ptr))>; 1188def sextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (sextloadi16 node:$ptr))>; 1189def sextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (sextloadi32 node:$ptr))>; 1190 1191def zextloadi8i1 : PatFrag<(ops node:$ptr), (i8 (zextloadi1 node:$ptr))>; 1192def zextloadi16i1 : PatFrag<(ops node:$ptr), (i16 (zextloadi1 node:$ptr))>; 1193def zextloadi32i1 : PatFrag<(ops node:$ptr), (i32 (zextloadi1 node:$ptr))>; 1194def zextloadi16i8 : PatFrag<(ops node:$ptr), (i16 (zextloadi8 node:$ptr))>; 1195def zextloadi32i8 : PatFrag<(ops node:$ptr), (i32 (zextloadi8 node:$ptr))>; 1196def zextloadi32i16 : PatFrag<(ops node:$ptr), (i32 (zextloadi16 node:$ptr))>; 1197def zextloadi64i1 : PatFrag<(ops node:$ptr), (i64 (zextloadi1 node:$ptr))>; 1198def zextloadi64i8 : PatFrag<(ops node:$ptr), (i64 (zextloadi8 node:$ptr))>; 1199def zextloadi64i16 : PatFrag<(ops node:$ptr), (i64 (zextloadi16 node:$ptr))>; 1200def zextloadi64i32 : PatFrag<(ops node:$ptr), (i64 (zextloadi32 node:$ptr))>; 1201 1202def extloadi8i1 : PatFrag<(ops node:$ptr), (i8 (extloadi1 node:$ptr))>; 1203def extloadi16i1 : PatFrag<(ops node:$ptr), (i16 (extloadi1 node:$ptr))>; 1204def extloadi32i1 : PatFrag<(ops node:$ptr), (i32 (extloadi1 node:$ptr))>; 1205def extloadi16i8 : PatFrag<(ops node:$ptr), (i16 (extloadi8 node:$ptr))>; 1206def extloadi32i8 : PatFrag<(ops node:$ptr), (i32 (extloadi8 node:$ptr))>; 1207def extloadi32i16 : PatFrag<(ops node:$ptr), (i32 (extloadi16 node:$ptr))>; 1208def extloadi64i1 : PatFrag<(ops node:$ptr), (i64 (extloadi1 node:$ptr))>; 1209def extloadi64i8 : PatFrag<(ops node:$ptr), (i64 (extloadi8 node:$ptr))>; 1210def extloadi64i16 : PatFrag<(ops node:$ptr), (i64 (extloadi16 node:$ptr))>; 1211 1212// We can treat an i8/i16 extending load to i64 as a 32 bit load if its known 1213// to be 4 byte aligned or better. 1214def extloadi64i32 : PatFrag<(ops node:$ptr), (i64 (unindexedload node:$ptr)), [{ 1215 LoadSDNode *LD = cast<LoadSDNode>(N); 1216 ISD::LoadExtType ExtType = LD->getExtensionType(); 1217 if (ExtType != ISD::EXTLOAD) 1218 return false; 1219 if (LD->getMemoryVT() == MVT::i32) 1220 return true; 1221 1222 return LD->getAlignment() >= 4 && LD->isSimple(); 1223}]>; 1224 1225 1226// An 'and' node with a single use. 1227def and_su : PatFrag<(ops node:$lhs, node:$rhs), (and node:$lhs, node:$rhs), [{ 1228 return N->hasOneUse(); 1229}]>; 1230// An 'srl' node with a single use. 1231def srl_su : PatFrag<(ops node:$lhs, node:$rhs), (srl node:$lhs, node:$rhs), [{ 1232 return N->hasOneUse(); 1233}]>; 1234// An 'trunc' node with a single use. 1235def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{ 1236 return N->hasOneUse(); 1237}]>; 1238 1239//===----------------------------------------------------------------------===// 1240// Instruction list. 1241// 1242 1243// Nop 1244let hasSideEffects = 0, SchedRW = [WriteNop] in { 1245 def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", []>; 1246 def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero), 1247 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; 1248 def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero), 1249 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; 1250 def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero), 1251 "nop{q}\t$zero", []>, TB, NotMemoryFoldable, 1252 Requires<[In64BitMode]>; 1253 // Also allow register so we can assemble/disassemble 1254 def NOOPWr : I<0x1f, MRMXr, (outs), (ins GR16:$zero), 1255 "nop{w}\t$zero", []>, TB, OpSize16, NotMemoryFoldable; 1256 def NOOPLr : I<0x1f, MRMXr, (outs), (ins GR32:$zero), 1257 "nop{l}\t$zero", []>, TB, OpSize32, NotMemoryFoldable; 1258 def NOOPQr : RI<0x1f, MRMXr, (outs), (ins GR64:$zero), 1259 "nop{q}\t$zero", []>, TB, NotMemoryFoldable, 1260 Requires<[In64BitMode]>; 1261} 1262 1263 1264// Constructing a stack frame. 1265def ENTER : Ii16<0xC8, RawFrmImm8, (outs), (ins i16imm:$len, i8imm:$lvl), 1266 "enter\t$len, $lvl", []>, Sched<[WriteMicrocoded]>; 1267 1268let SchedRW = [WriteALU] in { 1269let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in 1270def LEAVE : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 1271 Requires<[Not64BitMode]>; 1272 1273let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in 1274def LEAVE64 : I<0xC9, RawFrm, (outs), (ins), "leave", []>, 1275 Requires<[In64BitMode]>; 1276} // SchedRW 1277 1278//===----------------------------------------------------------------------===// 1279// Miscellaneous Instructions. 1280// 1281 1282let isBarrier = 1, hasSideEffects = 1, usesCustomInserter = 1, 1283 SchedRW = [WriteSystem] in 1284 def Int_eh_sjlj_setup_dispatch 1285 : PseudoI<(outs), (ins), [(X86eh_sjlj_setup_dispatch)]>; 1286 1287let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in { 1288let mayLoad = 1, SchedRW = [WriteLoad] in { 1289def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 1290 OpSize16; 1291def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 1292 OpSize32, Requires<[Not64BitMode]>; 1293// Long form for the disassembler. 1294let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1295def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", []>, 1296 OpSize16, NotMemoryFoldable; 1297def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", []>, 1298 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; 1299} // isCodeGenOnly = 1, ForceDisassemble = 1 1300} // mayLoad, SchedRW 1301let mayStore = 1, mayLoad = 1, SchedRW = [WriteCopy] in { 1302def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", []>, 1303 OpSize16; 1304def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", []>, 1305 OpSize32, Requires<[Not64BitMode]>; 1306} // mayStore, mayLoad, SchedRW 1307 1308let mayStore = 1, SchedRW = [WriteStore] in { 1309def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 1310 OpSize16; 1311def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 1312 OpSize32, Requires<[Not64BitMode]>; 1313// Long form for the disassembler. 1314let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1315def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[]>, 1316 OpSize16, NotMemoryFoldable; 1317def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[]>, 1318 OpSize32, Requires<[Not64BitMode]>, NotMemoryFoldable; 1319} // isCodeGenOnly = 1, ForceDisassemble = 1 1320 1321def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm), 1322 "push{w}\t$imm", []>, OpSize16; 1323def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm), 1324 "push{w}\t$imm", []>, OpSize16; 1325 1326def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm), 1327 "push{l}\t$imm", []>, OpSize32, 1328 Requires<[Not64BitMode]>; 1329def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm), 1330 "push{l}\t$imm", []>, OpSize32, 1331 Requires<[Not64BitMode]>; 1332} // mayStore, SchedRW 1333 1334let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in { 1335def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src", []>, 1336 OpSize16; 1337def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src", []>, 1338 OpSize32, Requires<[Not64BitMode]>; 1339} // mayLoad, mayStore, SchedRW 1340 1341} 1342 1343let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, 1344 SchedRW = [WriteRMW], Defs = [ESP] in { 1345 let Uses = [ESP] in 1346 def RDFLAGS32 : PseudoI<(outs GR32:$dst), (ins), 1347 [(set GR32:$dst, (int_x86_flags_read_u32))]>, 1348 Requires<[Not64BitMode]>; 1349 1350 let Uses = [RSP] in 1351 def RDFLAGS64 : PseudoI<(outs GR64:$dst), (ins), 1352 [(set GR64:$dst, (int_x86_flags_read_u64))]>, 1353 Requires<[In64BitMode]>; 1354} 1355 1356let mayLoad = 1, mayStore = 1, usesCustomInserter = 1, 1357 SchedRW = [WriteRMW] in { 1358 let Defs = [ESP, EFLAGS, DF], Uses = [ESP] in 1359 def WRFLAGS32 : PseudoI<(outs), (ins GR32:$src), 1360 [(int_x86_flags_write_u32 GR32:$src)]>, 1361 Requires<[Not64BitMode]>; 1362 1363 let Defs = [RSP, EFLAGS, DF], Uses = [RSP] in 1364 def WRFLAGS64 : PseudoI<(outs), (ins GR64:$src), 1365 [(int_x86_flags_write_u64 GR64:$src)]>, 1366 Requires<[In64BitMode]>; 1367} 1368 1369let Defs = [ESP, EFLAGS, DF], Uses = [ESP], mayLoad = 1, hasSideEffects=0, 1370 SchedRW = [WriteLoad] in { 1371def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize16; 1372def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", []>, OpSize32, 1373 Requires<[Not64BitMode]>; 1374} 1375 1376let Defs = [ESP], Uses = [ESP, EFLAGS, DF], mayStore = 1, hasSideEffects=0, 1377 SchedRW = [WriteStore] in { 1378def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize16; 1379def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", []>, OpSize32, 1380 Requires<[Not64BitMode]>; 1381} 1382 1383let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in { 1384let mayLoad = 1, SchedRW = [WriteLoad] in { 1385def POP64r : I<0x58, AddRegFrm, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 1386 OpSize32, Requires<[In64BitMode]>; 1387// Long form for the disassembler. 1388let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1389def POP64rmr: I<0x8F, MRM0r, (outs GR64:$reg), (ins), "pop{q}\t$reg", []>, 1390 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; 1391} // isCodeGenOnly = 1, ForceDisassemble = 1 1392} // mayLoad, SchedRW 1393let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in 1394def POP64rmm: I<0x8F, MRM0m, (outs), (ins i64mem:$dst), "pop{q}\t$dst", []>, 1395 OpSize32, Requires<[In64BitMode]>; 1396let mayStore = 1, SchedRW = [WriteStore] in { 1397def PUSH64r : I<0x50, AddRegFrm, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 1398 OpSize32, Requires<[In64BitMode]>; 1399// Long form for the disassembler. 1400let isCodeGenOnly = 1, ForceDisassemble = 1 in { 1401def PUSH64rmr: I<0xFF, MRM6r, (outs), (ins GR64:$reg), "push{q}\t$reg", []>, 1402 OpSize32, Requires<[In64BitMode]>, NotMemoryFoldable; 1403} // isCodeGenOnly = 1, ForceDisassemble = 1 1404} // mayStore, SchedRW 1405let mayLoad = 1, mayStore = 1, SchedRW = [WriteCopy] in { 1406def PUSH64rmm: I<0xFF, MRM6m, (outs), (ins i64mem:$src), "push{q}\t$src", []>, 1407 OpSize32, Requires<[In64BitMode]>; 1408} // mayLoad, mayStore, SchedRW 1409} 1410 1411let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1, 1412 SchedRW = [WriteStore] in { 1413def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm), 1414 "push{q}\t$imm", []>, OpSize32, 1415 Requires<[In64BitMode]>; 1416def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm), 1417 "push{q}\t$imm", []>, OpSize32, 1418 Requires<[In64BitMode]>; 1419} 1420 1421let Defs = [RSP, EFLAGS, DF], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in 1422def POPF64 : I<0x9D, RawFrm, (outs), (ins), "popfq", []>, 1423 OpSize32, Requires<[In64BitMode]>, Sched<[WriteLoad]>; 1424let Defs = [RSP], Uses = [RSP, EFLAGS, DF], mayStore = 1, hasSideEffects=0 in 1425def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", []>, 1426 OpSize32, Requires<[In64BitMode]>, Sched<[WriteStore]>; 1427 1428let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP], 1429 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in { 1430def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", []>, 1431 OpSize32, Requires<[Not64BitMode]>; 1432def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", []>, 1433 OpSize16, Requires<[Not64BitMode]>; 1434} 1435let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], 1436 mayStore = 1, hasSideEffects = 0, SchedRW = [WriteStore] in { 1437def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", []>, 1438 OpSize32, Requires<[Not64BitMode]>; 1439def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", []>, 1440 OpSize16, Requires<[Not64BitMode]>; 1441} 1442 1443let Constraints = "$src = $dst", SchedRW = [WriteBSWAP32] in { 1444// This instruction is a consequence of BSWAP32r observing operand size. The 1445// encoding is valid, but the behavior is undefined. 1446let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in 1447def BSWAP16r_BAD : I<0xC8, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 1448 "bswap{w}\t$dst", []>, OpSize16, TB; 1449// GR32 = bswap GR32 1450def BSWAP32r : I<0xC8, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 1451 "bswap{l}\t$dst", 1452 [(set GR32:$dst, (bswap GR32:$src))]>, OpSize32, TB; 1453 1454let SchedRW = [WriteBSWAP64] in 1455def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 1456 "bswap{q}\t$dst", 1457 [(set GR64:$dst, (bswap GR64:$src))]>, TB; 1458} // Constraints = "$src = $dst", SchedRW 1459 1460// Bit scan instructions. 1461let Defs = [EFLAGS] in { 1462def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1463 "bsf{w}\t{$src, $dst|$dst, $src}", 1464 [(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))]>, 1465 PS, OpSize16, Sched<[WriteBSF]>; 1466def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1467 "bsf{w}\t{$src, $dst|$dst, $src}", 1468 [(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))]>, 1469 PS, OpSize16, Sched<[WriteBSFLd]>; 1470def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1471 "bsf{l}\t{$src, $dst|$dst, $src}", 1472 [(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))]>, 1473 PS, OpSize32, Sched<[WriteBSF]>; 1474def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1475 "bsf{l}\t{$src, $dst|$dst, $src}", 1476 [(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))]>, 1477 PS, OpSize32, Sched<[WriteBSFLd]>; 1478def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1479 "bsf{q}\t{$src, $dst|$dst, $src}", 1480 [(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))]>, 1481 PS, Sched<[WriteBSF]>; 1482def BSF64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1483 "bsf{q}\t{$src, $dst|$dst, $src}", 1484 [(set GR64:$dst, EFLAGS, (X86bsf (loadi64 addr:$src)))]>, 1485 PS, Sched<[WriteBSFLd]>; 1486 1487def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1488 "bsr{w}\t{$src, $dst|$dst, $src}", 1489 [(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))]>, 1490 PS, OpSize16, Sched<[WriteBSR]>; 1491def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1492 "bsr{w}\t{$src, $dst|$dst, $src}", 1493 [(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))]>, 1494 PS, OpSize16, Sched<[WriteBSRLd]>; 1495def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1496 "bsr{l}\t{$src, $dst|$dst, $src}", 1497 [(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))]>, 1498 PS, OpSize32, Sched<[WriteBSR]>; 1499def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1500 "bsr{l}\t{$src, $dst|$dst, $src}", 1501 [(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))]>, 1502 PS, OpSize32, Sched<[WriteBSRLd]>; 1503def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1504 "bsr{q}\t{$src, $dst|$dst, $src}", 1505 [(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))]>, 1506 PS, Sched<[WriteBSR]>; 1507def BSR64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1508 "bsr{q}\t{$src, $dst|$dst, $src}", 1509 [(set GR64:$dst, EFLAGS, (X86bsr (loadi64 addr:$src)))]>, 1510 PS, Sched<[WriteBSRLd]>; 1511} // Defs = [EFLAGS] 1512 1513let SchedRW = [WriteMicrocoded] in { 1514let Defs = [EDI,ESI], Uses = [EDI,ESI,DF] in { 1515def MOVSB : I<0xA4, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1516 "movsb\t{$src, $dst|$dst, $src}", []>; 1517def MOVSW : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1518 "movsw\t{$src, $dst|$dst, $src}", []>, OpSize16; 1519def MOVSL : I<0xA5, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1520 "movs{l|d}\t{$src, $dst|$dst, $src}", []>, OpSize32; 1521def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1522 "movsq\t{$src, $dst|$dst, $src}", []>, 1523 Requires<[In64BitMode]>; 1524} 1525 1526let Defs = [EDI], Uses = [AL,EDI,DF] in 1527def STOSB : I<0xAA, RawFrmDst, (outs), (ins dstidx8:$dst), 1528 "stosb\t{%al, $dst|$dst, al}", []>; 1529let Defs = [EDI], Uses = [AX,EDI,DF] in 1530def STOSW : I<0xAB, RawFrmDst, (outs), (ins dstidx16:$dst), 1531 "stosw\t{%ax, $dst|$dst, ax}", []>, OpSize16; 1532let Defs = [EDI], Uses = [EAX,EDI,DF] in 1533def STOSL : I<0xAB, RawFrmDst, (outs), (ins dstidx32:$dst), 1534 "stos{l|d}\t{%eax, $dst|$dst, eax}", []>, OpSize32; 1535let Defs = [RDI], Uses = [RAX,RDI,DF] in 1536def STOSQ : RI<0xAB, RawFrmDst, (outs), (ins dstidx64:$dst), 1537 "stosq\t{%rax, $dst|$dst, rax}", []>, 1538 Requires<[In64BitMode]>; 1539 1540let Defs = [EDI,EFLAGS], Uses = [AL,EDI,DF] in 1541def SCASB : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst), 1542 "scasb\t{$dst, %al|al, $dst}", []>; 1543let Defs = [EDI,EFLAGS], Uses = [AX,EDI,DF] in 1544def SCASW : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst), 1545 "scasw\t{$dst, %ax|ax, $dst}", []>, OpSize16; 1546let Defs = [EDI,EFLAGS], Uses = [EAX,EDI,DF] in 1547def SCASL : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst), 1548 "scas{l|d}\t{$dst, %eax|eax, $dst}", []>, OpSize32; 1549let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in 1550def SCASQ : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst), 1551 "scasq\t{$dst, %rax|rax, $dst}", []>, 1552 Requires<[In64BitMode]>; 1553 1554let Defs = [EDI,ESI,EFLAGS], Uses = [EDI,ESI,DF] in { 1555def CMPSB : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src), 1556 "cmpsb\t{$dst, $src|$src, $dst}", []>; 1557def CMPSW : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src), 1558 "cmpsw\t{$dst, $src|$src, $dst}", []>, OpSize16; 1559def CMPSL : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src), 1560 "cmps{l|d}\t{$dst, $src|$src, $dst}", []>, OpSize32; 1561def CMPSQ : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src), 1562 "cmpsq\t{$dst, $src|$src, $dst}", []>, 1563 Requires<[In64BitMode]>; 1564} 1565} // SchedRW 1566 1567//===----------------------------------------------------------------------===// 1568// Move Instructions. 1569// 1570let SchedRW = [WriteMove] in { 1571let hasSideEffects = 0, isMoveReg = 1 in { 1572def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src), 1573 "mov{b}\t{$src, $dst|$dst, $src}", []>; 1574def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 1575 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16; 1576def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 1577 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32; 1578def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 1579 "mov{q}\t{$src, $dst|$dst, $src}", []>; 1580} 1581 1582let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 1583def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src), 1584 "mov{b}\t{$src, $dst|$dst, $src}", 1585 [(set GR8:$dst, imm:$src)]>; 1586def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src), 1587 "mov{w}\t{$src, $dst|$dst, $src}", 1588 [(set GR16:$dst, imm:$src)]>, OpSize16; 1589def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src), 1590 "mov{l}\t{$src, $dst|$dst, $src}", 1591 [(set GR32:$dst, imm:$src)]>, OpSize32; 1592def MOV64ri32 : RIi32S<0xC7, MRM0r, (outs GR64:$dst), (ins i64i32imm:$src), 1593 "mov{q}\t{$src, $dst|$dst, $src}", 1594 [(set GR64:$dst, i64immSExt32:$src)]>; 1595} 1596let isReMaterializable = 1, isMoveImm = 1 in { 1597def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src), 1598 "movabs{q}\t{$src, $dst|$dst, $src}", 1599 [(set GR64:$dst, imm:$src)]>; 1600} 1601 1602// Longer forms that use a ModR/M byte. Needed for disassembler 1603let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in { 1604def MOV8ri_alt : Ii8 <0xC6, MRM0r, (outs GR8 :$dst), (ins i8imm :$src), 1605 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1606 FoldGenData<"MOV8ri">; 1607def MOV16ri_alt : Ii16<0xC7, MRM0r, (outs GR16:$dst), (ins i16imm:$src), 1608 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 1609 FoldGenData<"MOV16ri">; 1610def MOV32ri_alt : Ii32<0xC7, MRM0r, (outs GR32:$dst), (ins i32imm:$src), 1611 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 1612 FoldGenData<"MOV32ri">; 1613} 1614} // SchedRW 1615 1616let SchedRW = [WriteStore] in { 1617def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src), 1618 "mov{b}\t{$src, $dst|$dst, $src}", 1619 [(store (i8 imm_su:$src), addr:$dst)]>; 1620def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src), 1621 "mov{w}\t{$src, $dst|$dst, $src}", 1622 [(store (i16 imm_su:$src), addr:$dst)]>, OpSize16; 1623def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src), 1624 "mov{l}\t{$src, $dst|$dst, $src}", 1625 [(store (i32 imm_su:$src), addr:$dst)]>, OpSize32; 1626def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src), 1627 "mov{q}\t{$src, $dst|$dst, $src}", 1628 [(store i64immSExt32_su:$src, addr:$dst)]>, 1629 Requires<[In64BitMode]>; 1630} // SchedRW 1631 1632def : Pat<(i32 relocImm:$src), (MOV32ri relocImm:$src)>; 1633def : Pat<(i64 relocImm:$src), (MOV64ri relocImm:$src)>; 1634 1635def : Pat<(store (i8 relocImm8_su:$src), addr:$dst), 1636 (MOV8mi addr:$dst, relocImm8_su:$src)>; 1637def : Pat<(store (i16 relocImm16_su:$src), addr:$dst), 1638 (MOV16mi addr:$dst, relocImm16_su:$src)>; 1639def : Pat<(store (i32 relocImm32_su:$src), addr:$dst), 1640 (MOV32mi addr:$dst, relocImm32_su:$src)>; 1641def : Pat<(store (i64 i64relocImmSExt32_su:$src), addr:$dst), 1642 (MOV64mi32 addr:$dst, i64immSExt32_su:$src)>; 1643 1644let hasSideEffects = 0 in { 1645 1646/// Memory offset versions of moves. The immediate is an address mode sized 1647/// offset from the segment base. 1648let SchedRW = [WriteALU] in { 1649let mayLoad = 1 in { 1650let Defs = [AL] in 1651def MOV8ao32 : Ii32<0xA0, RawFrmMemOffs, (outs), (ins offset32_8:$src), 1652 "mov{b}\t{$src, %al|al, $src}", []>, 1653 AdSize32; 1654let Defs = [AX] in 1655def MOV16ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_16:$src), 1656 "mov{w}\t{$src, %ax|ax, $src}", []>, 1657 OpSize16, AdSize32; 1658let Defs = [EAX] in 1659def MOV32ao32 : Ii32<0xA1, RawFrmMemOffs, (outs), (ins offset32_32:$src), 1660 "mov{l}\t{$src, %eax|eax, $src}", []>, 1661 OpSize32, AdSize32; 1662let Defs = [RAX] in 1663def MOV64ao32 : RIi32<0xA1, RawFrmMemOffs, (outs), (ins offset32_64:$src), 1664 "mov{q}\t{$src, %rax|rax, $src}", []>, 1665 AdSize32; 1666 1667let Defs = [AL] in 1668def MOV8ao16 : Ii16<0xA0, RawFrmMemOffs, (outs), (ins offset16_8:$src), 1669 "mov{b}\t{$src, %al|al, $src}", []>, AdSize16; 1670let Defs = [AX] in 1671def MOV16ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_16:$src), 1672 "mov{w}\t{$src, %ax|ax, $src}", []>, 1673 OpSize16, AdSize16; 1674let Defs = [EAX] in 1675def MOV32ao16 : Ii16<0xA1, RawFrmMemOffs, (outs), (ins offset16_32:$src), 1676 "mov{l}\t{$src, %eax|eax, $src}", []>, 1677 AdSize16, OpSize32; 1678} // mayLoad 1679let mayStore = 1 in { 1680let Uses = [AL] in 1681def MOV8o32a : Ii32<0xA2, RawFrmMemOffs, (outs), (ins offset32_8:$dst), 1682 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize32; 1683let Uses = [AX] in 1684def MOV16o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_16:$dst), 1685 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 1686 OpSize16, AdSize32; 1687let Uses = [EAX] in 1688def MOV32o32a : Ii32<0xA3, RawFrmMemOffs, (outs), (ins offset32_32:$dst), 1689 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 1690 OpSize32, AdSize32; 1691let Uses = [RAX] in 1692def MOV64o32a : RIi32<0xA3, RawFrmMemOffs, (outs), (ins offset32_64:$dst), 1693 "mov{q}\t{%rax, $dst|$dst, rax}", []>, 1694 AdSize32; 1695 1696let Uses = [AL] in 1697def MOV8o16a : Ii16<0xA2, RawFrmMemOffs, (outs), (ins offset16_8:$dst), 1698 "mov{b}\t{%al, $dst|$dst, al}", []>, AdSize16; 1699let Uses = [AX] in 1700def MOV16o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_16:$dst), 1701 "mov{w}\t{%ax, $dst|$dst, ax}", []>, 1702 OpSize16, AdSize16; 1703let Uses = [EAX] in 1704def MOV32o16a : Ii16<0xA3, RawFrmMemOffs, (outs), (ins offset16_32:$dst), 1705 "mov{l}\t{%eax, $dst|$dst, eax}", []>, 1706 OpSize32, AdSize16; 1707} // mayStore 1708 1709// These forms all have full 64-bit absolute addresses in their instructions 1710// and use the movabs mnemonic to indicate this specific form. 1711let mayLoad = 1 in { 1712let Defs = [AL] in 1713def MOV8ao64 : Ii64<0xA0, RawFrmMemOffs, (outs), (ins offset64_8:$src), 1714 "movabs{b}\t{$src, %al|al, $src}", []>, 1715 AdSize64; 1716let Defs = [AX] in 1717def MOV16ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_16:$src), 1718 "movabs{w}\t{$src, %ax|ax, $src}", []>, 1719 OpSize16, AdSize64; 1720let Defs = [EAX] in 1721def MOV32ao64 : Ii64<0xA1, RawFrmMemOffs, (outs), (ins offset64_32:$src), 1722 "movabs{l}\t{$src, %eax|eax, $src}", []>, 1723 OpSize32, AdSize64; 1724let Defs = [RAX] in 1725def MOV64ao64 : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64_64:$src), 1726 "movabs{q}\t{$src, %rax|rax, $src}", []>, 1727 AdSize64; 1728} // mayLoad 1729 1730let mayStore = 1 in { 1731let Uses = [AL] in 1732def MOV8o64a : Ii64<0xA2, RawFrmMemOffs, (outs), (ins offset64_8:$dst), 1733 "movabs{b}\t{%al, $dst|$dst, al}", []>, 1734 AdSize64; 1735let Uses = [AX] in 1736def MOV16o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_16:$dst), 1737 "movabs{w}\t{%ax, $dst|$dst, ax}", []>, 1738 OpSize16, AdSize64; 1739let Uses = [EAX] in 1740def MOV32o64a : Ii64<0xA3, RawFrmMemOffs, (outs), (ins offset64_32:$dst), 1741 "movabs{l}\t{%eax, $dst|$dst, eax}", []>, 1742 OpSize32, AdSize64; 1743let Uses = [RAX] in 1744def MOV64o64a : RIi64<0xA3, RawFrmMemOffs, (outs), (ins offset64_64:$dst), 1745 "movabs{q}\t{%rax, $dst|$dst, rax}", []>, 1746 AdSize64; 1747} // mayStore 1748} // SchedRW 1749} // hasSideEffects = 0 1750 1751let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, 1752 SchedRW = [WriteMove], isMoveReg = 1 in { 1753def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src), 1754 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1755 FoldGenData<"MOV8rr">; 1756def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 1757 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16, 1758 FoldGenData<"MOV16rr">; 1759def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 1760 "mov{l}\t{$src, $dst|$dst, $src}", []>, OpSize32, 1761 FoldGenData<"MOV32rr">; 1762def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 1763 "mov{q}\t{$src, $dst|$dst, $src}", []>, 1764 FoldGenData<"MOV64rr">; 1765} 1766 1767// Reversed version with ".s" suffix for GAS compatibility. 1768def : InstAlias<"mov{b}.s\t{$src, $dst|$dst, $src}", 1769 (MOV8rr_REV GR8:$dst, GR8:$src), 0>; 1770def : InstAlias<"mov{w}.s\t{$src, $dst|$dst, $src}", 1771 (MOV16rr_REV GR16:$dst, GR16:$src), 0>; 1772def : InstAlias<"mov{l}.s\t{$src, $dst|$dst, $src}", 1773 (MOV32rr_REV GR32:$dst, GR32:$src), 0>; 1774def : InstAlias<"mov{q}.s\t{$src, $dst|$dst, $src}", 1775 (MOV64rr_REV GR64:$dst, GR64:$src), 0>; 1776def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1777 (MOV8rr_REV GR8:$dst, GR8:$src), 0, "att">; 1778def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1779 (MOV16rr_REV GR16:$dst, GR16:$src), 0, "att">; 1780def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1781 (MOV32rr_REV GR32:$dst, GR32:$src), 0, "att">; 1782def : InstAlias<"mov.s\t{$src, $dst|$dst, $src}", 1783 (MOV64rr_REV GR64:$dst, GR64:$src), 0, "att">; 1784 1785let canFoldAsLoad = 1, isReMaterializable = 1, SchedRW = [WriteLoad] in { 1786def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src), 1787 "mov{b}\t{$src, $dst|$dst, $src}", 1788 [(set GR8:$dst, (loadi8 addr:$src))]>; 1789def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 1790 "mov{w}\t{$src, $dst|$dst, $src}", 1791 [(set GR16:$dst, (loadi16 addr:$src))]>, OpSize16; 1792def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 1793 "mov{l}\t{$src, $dst|$dst, $src}", 1794 [(set GR32:$dst, (loadi32 addr:$src))]>, OpSize32; 1795def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 1796 "mov{q}\t{$src, $dst|$dst, $src}", 1797 [(set GR64:$dst, (load addr:$src))]>; 1798} 1799 1800let SchedRW = [WriteStore] in { 1801def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), 1802 "mov{b}\t{$src, $dst|$dst, $src}", 1803 [(store GR8:$src, addr:$dst)]>; 1804def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 1805 "mov{w}\t{$src, $dst|$dst, $src}", 1806 [(store GR16:$src, addr:$dst)]>, OpSize16; 1807def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 1808 "mov{l}\t{$src, $dst|$dst, $src}", 1809 [(store GR32:$src, addr:$dst)]>, OpSize32; 1810def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 1811 "mov{q}\t{$src, $dst|$dst, $src}", 1812 [(store GR64:$src, addr:$dst)]>; 1813} // SchedRW 1814 1815// Versions of MOV8rr, MOV8mr, and MOV8rm that use i8mem_NOREX and GR8_NOREX so 1816// that they can be used for copying and storing h registers, which can't be 1817// encoded when a REX prefix is present. 1818let isCodeGenOnly = 1 in { 1819let hasSideEffects = 0, isMoveReg = 1 in 1820def MOV8rr_NOREX : I<0x88, MRMDestReg, 1821 (outs GR8_NOREX:$dst), (ins GR8_NOREX:$src), 1822 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1823 Sched<[WriteMove]>; 1824let mayStore = 1, hasSideEffects = 0 in 1825def MOV8mr_NOREX : I<0x88, MRMDestMem, 1826 (outs), (ins i8mem_NOREX:$dst, GR8_NOREX:$src), 1827 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1828 Sched<[WriteStore]>; 1829let mayLoad = 1, hasSideEffects = 0, 1830 canFoldAsLoad = 1, isReMaterializable = 1 in 1831def MOV8rm_NOREX : I<0x8A, MRMSrcMem, 1832 (outs GR8_NOREX:$dst), (ins i8mem_NOREX:$src), 1833 "mov{b}\t{$src, $dst|$dst, $src}", []>, 1834 Sched<[WriteLoad]>; 1835} 1836 1837 1838// Condition code ops, incl. set if equal/not equal/... 1839let SchedRW = [WriteLAHFSAHF] in { 1840let Defs = [EFLAGS], Uses = [AH], hasSideEffects = 0 in 1841def SAHF : I<0x9E, RawFrm, (outs), (ins), "sahf", []>, // flags = AH 1842 Requires<[HasLAHFSAHF]>; 1843let Defs = [AH], Uses = [EFLAGS], hasSideEffects = 0 in 1844def LAHF : I<0x9F, RawFrm, (outs), (ins), "lahf", []>, // AH = flags 1845 Requires<[HasLAHFSAHF]>; 1846} // SchedRW 1847 1848//===----------------------------------------------------------------------===// 1849// Bit tests instructions: BT, BTS, BTR, BTC. 1850 1851let Defs = [EFLAGS] in { 1852let SchedRW = [WriteBitTest] in { 1853def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2), 1854 "bt{w}\t{$src2, $src1|$src1, $src2}", 1855 [(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))]>, 1856 OpSize16, TB, NotMemoryFoldable; 1857def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2), 1858 "bt{l}\t{$src2, $src1|$src1, $src2}", 1859 [(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))]>, 1860 OpSize32, TB, NotMemoryFoldable; 1861def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2), 1862 "bt{q}\t{$src2, $src1|$src1, $src2}", 1863 [(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))]>, TB, 1864 NotMemoryFoldable; 1865} // SchedRW 1866 1867// Unlike with the register+register form, the memory+register form of the 1868// bt instruction does not ignore the high bits of the index. From ISel's 1869// perspective, this is pretty bizarre. Make these instructions disassembly 1870// only for now. These instructions are also slow on modern CPUs so that's 1871// another reason to avoid generating them. 1872 1873let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteBitTestRegLd] in { 1874 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1875 "bt{w}\t{$src2, $src1|$src1, $src2}", 1876 []>, OpSize16, TB, NotMemoryFoldable; 1877 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1878 "bt{l}\t{$src2, $src1|$src1, $src2}", 1879 []>, OpSize32, TB, NotMemoryFoldable; 1880 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1881 "bt{q}\t{$src2, $src1|$src1, $src2}", 1882 []>, TB, NotMemoryFoldable; 1883} 1884 1885let SchedRW = [WriteBitTest] in { 1886def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16u8imm:$src2), 1887 "bt{w}\t{$src2, $src1|$src1, $src2}", 1888 [(set EFLAGS, (X86bt GR16:$src1, imm:$src2))]>, 1889 OpSize16, TB; 1890def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32u8imm:$src2), 1891 "bt{l}\t{$src2, $src1|$src1, $src2}", 1892 [(set EFLAGS, (X86bt GR32:$src1, imm:$src2))]>, 1893 OpSize32, TB; 1894def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64u8imm:$src2), 1895 "bt{q}\t{$src2, $src1|$src1, $src2}", 1896 [(set EFLAGS, (X86bt GR64:$src1, imm:$src2))]>, TB; 1897} // SchedRW 1898 1899// Note that these instructions aren't slow because that only applies when the 1900// other operand is in a register. When it's an immediate, bt is still fast. 1901let SchedRW = [WriteBitTestImmLd] in { 1902def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 1903 "bt{w}\t{$src2, $src1|$src1, $src2}", 1904 [(set EFLAGS, (X86bt (loadi16 addr:$src1), 1905 imm:$src2))]>, 1906 OpSize16, TB; 1907def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 1908 "bt{l}\t{$src2, $src1|$src1, $src2}", 1909 [(set EFLAGS, (X86bt (loadi32 addr:$src1), 1910 imm:$src2))]>, 1911 OpSize32, TB; 1912def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 1913 "bt{q}\t{$src2, $src1|$src1, $src2}", 1914 [(set EFLAGS, (X86bt (loadi64 addr:$src1), 1915 imm:$src2))]>, TB, 1916 Requires<[In64BitMode]>; 1917} // SchedRW 1918 1919let hasSideEffects = 0 in { 1920let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 1921def BTC16rr : I<0xBB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1922 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 1923 OpSize16, TB, NotMemoryFoldable; 1924def BTC32rr : I<0xBB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1925 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 1926 OpSize32, TB, NotMemoryFoldable; 1927def BTC64rr : RI<0xBB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1928 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1929 NotMemoryFoldable; 1930} // SchedRW 1931 1932let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 1933def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1934 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, 1935 OpSize16, TB, NotMemoryFoldable; 1936def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1937 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, 1938 OpSize32, TB, NotMemoryFoldable; 1939def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1940 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1941 NotMemoryFoldable; 1942} 1943 1944let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 1945def BTC16ri8 : Ii8<0xBA, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 1946 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 1947def BTC32ri8 : Ii8<0xBA, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 1948 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 1949def BTC64ri8 : RIi8<0xBA, MRM7r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 1950 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1951} // SchedRW 1952 1953let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 1954def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 1955 "btc{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 1956def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 1957 "btc{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 1958def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 1959 "btc{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1960 Requires<[In64BitMode]>; 1961} 1962 1963let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 1964def BTR16rr : I<0xB3, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 1965 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1966 OpSize16, TB, NotMemoryFoldable; 1967def BTR32rr : I<0xB3, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 1968 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1969 OpSize32, TB, NotMemoryFoldable; 1970def BTR64rr : RI<0xB3, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 1971 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1972 NotMemoryFoldable; 1973} // SchedRW 1974 1975let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 1976def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 1977 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1978 OpSize16, TB, NotMemoryFoldable; 1979def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 1980 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1981 OpSize32, TB, NotMemoryFoldable; 1982def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 1983 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 1984 NotMemoryFoldable; 1985} 1986 1987let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 1988def BTR16ri8 : Ii8<0xBA, MRM6r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 1989 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 1990 OpSize16, TB; 1991def BTR32ri8 : Ii8<0xBA, MRM6r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 1992 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 1993 OpSize32, TB; 1994def BTR64ri8 : RIi8<0xBA, MRM6r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 1995 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 1996} // SchedRW 1997 1998let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 1999def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 2000 "btr{w}\t{$src2, $src1|$src1, $src2}", []>, 2001 OpSize16, TB; 2002def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 2003 "btr{l}\t{$src2, $src1|$src1, $src2}", []>, 2004 OpSize32, TB; 2005def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 2006 "btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2007 Requires<[In64BitMode]>; 2008} 2009 2010let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 2011def BTS16rr : I<0xAB, MRMDestReg, (outs GR16:$dst), (ins GR16:$src1, GR16:$src2), 2012 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 2013 OpSize16, TB, NotMemoryFoldable; 2014def BTS32rr : I<0xAB, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2), 2015 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 2016 OpSize32, TB, NotMemoryFoldable; 2017def BTS64rr : RI<0xAB, MRMDestReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2), 2018 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2019 NotMemoryFoldable; 2020} // SchedRW 2021 2022let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetRegRMW] in { 2023def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2), 2024 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, 2025 OpSize16, TB, NotMemoryFoldable; 2026def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2), 2027 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, 2028 OpSize32, TB, NotMemoryFoldable; 2029def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2), 2030 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2031 NotMemoryFoldable; 2032} 2033 2034let SchedRW = [WriteBitTestSet], Constraints = "$src1 = $dst" in { 2035def BTS16ri8 : Ii8<0xBA, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i16u8imm:$src2), 2036 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 2037def BTS32ri8 : Ii8<0xBA, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i32u8imm:$src2), 2038 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 2039def BTS64ri8 : RIi8<0xBA, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i64u8imm:$src2), 2040 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2041} // SchedRW 2042 2043let mayLoad = 1, mayStore = 1, SchedRW = [WriteBitTestSetImmRMW] in { 2044def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16u8imm:$src2), 2045 "bts{w}\t{$src2, $src1|$src1, $src2}", []>, OpSize16, TB; 2046def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32u8imm:$src2), 2047 "bts{l}\t{$src2, $src1|$src1, $src2}", []>, OpSize32, TB; 2048def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64u8imm:$src2), 2049 "bts{q}\t{$src2, $src1|$src1, $src2}", []>, TB, 2050 Requires<[In64BitMode]>; 2051} 2052} // hasSideEffects = 0 2053} // Defs = [EFLAGS] 2054 2055 2056//===----------------------------------------------------------------------===// 2057// Atomic support 2058// 2059 2060// Atomic swap. These are just normal xchg instructions. But since a memory 2061// operand is referenced, the atomicity is ensured. 2062multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag> { 2063 let Constraints = "$val = $dst", SchedRW = [WriteALULd, WriteRMW] in { 2064 def NAME#8rm : I<opc8, MRMSrcMem, (outs GR8:$dst), 2065 (ins GR8:$val, i8mem:$ptr), 2066 !strconcat(mnemonic, "{b}\t{$val, $ptr|$ptr, $val}"), 2067 [(set 2068 GR8:$dst, 2069 (!cast<PatFrag>(frag # "_8") addr:$ptr, GR8:$val))]>; 2070 def NAME#16rm : I<opc, MRMSrcMem, (outs GR16:$dst), 2071 (ins GR16:$val, i16mem:$ptr), 2072 !strconcat(mnemonic, "{w}\t{$val, $ptr|$ptr, $val}"), 2073 [(set 2074 GR16:$dst, 2075 (!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))]>, 2076 OpSize16; 2077 def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst), 2078 (ins GR32:$val, i32mem:$ptr), 2079 !strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"), 2080 [(set 2081 GR32:$dst, 2082 (!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))]>, 2083 OpSize32; 2084 def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst), 2085 (ins GR64:$val, i64mem:$ptr), 2086 !strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"), 2087 [(set 2088 GR64:$dst, 2089 (!cast<PatFrag>(frag # "_64") addr:$ptr, GR64:$val))]>; 2090 } 2091} 2092 2093defm XCHG : ATOMIC_SWAP<0x86, 0x87, "xchg", "atomic_swap">, NotMemoryFoldable; 2094 2095// Swap between registers. 2096let SchedRW = [WriteXCHG] in { 2097let Constraints = "$src1 = $dst1, $src2 = $dst2", hasSideEffects = 0 in { 2098def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst1, GR8:$dst2), 2099 (ins GR8:$src1, GR8:$src2), 2100 "xchg{b}\t{$src2, $src1|$src1, $src2}", []>, NotMemoryFoldable; 2101def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst1, GR16:$dst2), 2102 (ins GR16:$src1, GR16:$src2), 2103 "xchg{w}\t{$src2, $src1|$src1, $src2}", []>, 2104 OpSize16, NotMemoryFoldable; 2105def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst1, GR32:$dst2), 2106 (ins GR32:$src1, GR32:$src2), 2107 "xchg{l}\t{$src2, $src1|$src1, $src2}", []>, 2108 OpSize32, NotMemoryFoldable; 2109def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst1, GR64:$dst2), 2110 (ins GR64:$src1 ,GR64:$src2), 2111 "xchg{q}\t{$src2, $src1|$src1, $src2}", []>, NotMemoryFoldable; 2112} 2113 2114// Swap between EAX and other registers. 2115let Constraints = "$src = $dst", hasSideEffects = 0 in { 2116let Uses = [AX], Defs = [AX] in 2117def XCHG16ar : I<0x90, AddRegFrm, (outs GR16:$dst), (ins GR16:$src), 2118 "xchg{w}\t{$src, %ax|ax, $src}", []>, OpSize16; 2119let Uses = [EAX], Defs = [EAX] in 2120def XCHG32ar : I<0x90, AddRegFrm, (outs GR32:$dst), (ins GR32:$src), 2121 "xchg{l}\t{$src, %eax|eax, $src}", []>, OpSize32; 2122let Uses = [RAX], Defs = [RAX] in 2123def XCHG64ar : RI<0x90, AddRegFrm, (outs GR64:$dst), (ins GR64:$src), 2124 "xchg{q}\t{$src, %rax|rax, $src}", []>; 2125} 2126} // SchedRW 2127 2128let hasSideEffects = 0, Constraints = "$src1 = $dst1, $src2 = $dst2", 2129 Defs = [EFLAGS], SchedRW = [WriteXCHG] in { 2130def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst1, GR8:$dst2), 2131 (ins GR8:$src1, GR8:$src2), 2132 "xadd{b}\t{$src2, $src1|$src1, $src2}", []>, TB; 2133def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst1, GR16:$dst2), 2134 (ins GR16:$src1, GR16:$src2), 2135 "xadd{w}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize16; 2136def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst1, GR32:$dst2), 2137 (ins GR32:$src1, GR32:$src2), 2138 "xadd{l}\t{$src2, $src1|$src1, $src2}", []>, TB, OpSize32; 2139def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst1, GR64:$dst2), 2140 (ins GR64:$src1, GR64:$src2), 2141 "xadd{q}\t{$src2, $src1|$src1, $src2}", []>, TB; 2142} // SchedRW 2143 2144let mayLoad = 1, mayStore = 1, hasSideEffects = 0, Constraints = "$val = $dst", 2145 Defs = [EFLAGS], SchedRW = [WriteALULd, WriteRMW] in { 2146def XADD8rm : I<0xC0, MRMSrcMem, (outs GR8:$dst), 2147 (ins GR8:$val, i8mem:$ptr), 2148 "xadd{b}\t{$val, $ptr|$ptr, $val}", []>, TB; 2149def XADD16rm : I<0xC1, MRMSrcMem, (outs GR16:$dst), 2150 (ins GR16:$val, i16mem:$ptr), 2151 "xadd{w}\t{$val, $ptr|$ptr, $val}", []>, TB, 2152 OpSize16; 2153def XADD32rm : I<0xC1, MRMSrcMem, (outs GR32:$dst), 2154 (ins GR32:$val, i32mem:$ptr), 2155 "xadd{l}\t{$val, $ptr|$ptr, $val}", []>, TB, 2156 OpSize32; 2157def XADD64rm : RI<0xC1, MRMSrcMem, (outs GR64:$dst), 2158 (ins GR64:$val, i64mem:$ptr), 2159 "xadd{q}\t{$val, $ptr|$ptr, $val}", []>, TB; 2160 2161} 2162 2163let SchedRW = [WriteCMPXCHG], hasSideEffects = 0 in { 2164let Defs = [AL, EFLAGS], Uses = [AL] in 2165def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src), 2166 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, 2167 NotMemoryFoldable; 2168let Defs = [AX, EFLAGS], Uses = [AX] in 2169def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 2170 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, 2171 NotMemoryFoldable; 2172let Defs = [EAX, EFLAGS], Uses = [EAX] in 2173def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src), 2174 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, 2175 NotMemoryFoldable; 2176let Defs = [RAX, EFLAGS], Uses = [RAX] in 2177def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src), 2178 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, 2179 NotMemoryFoldable; 2180} // SchedRW, hasSideEffects 2181 2182let SchedRW = [WriteCMPXCHGRMW], mayLoad = 1, mayStore = 1, 2183 hasSideEffects = 0 in { 2184let Defs = [AL, EFLAGS], Uses = [AL] in 2185def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src), 2186 "cmpxchg{b}\t{$src, $dst|$dst, $src}", []>, TB, 2187 NotMemoryFoldable; 2188let Defs = [AX, EFLAGS], Uses = [AX] in 2189def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2190 "cmpxchg{w}\t{$src, $dst|$dst, $src}", []>, TB, OpSize16, 2191 NotMemoryFoldable; 2192let Defs = [EAX, EFLAGS], Uses = [EAX] in 2193def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2194 "cmpxchg{l}\t{$src, $dst|$dst, $src}", []>, TB, OpSize32, 2195 NotMemoryFoldable; 2196let Defs = [RAX, EFLAGS], Uses = [RAX] in 2197def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2198 "cmpxchg{q}\t{$src, $dst|$dst, $src}", []>, TB, 2199 NotMemoryFoldable; 2200 2201let Defs = [EAX, EDX, EFLAGS], Uses = [EAX, EBX, ECX, EDX] in 2202def CMPXCHG8B : I<0xC7, MRM1m, (outs), (ins i64mem:$dst), 2203 "cmpxchg8b\t$dst", []>, TB, Requires<[HasCmpxchg8b]>; 2204 2205let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in 2206// NOTE: In64BitMode check needed for the AssemblerPredicate. 2207def CMPXCHG16B : RI<0xC7, MRM1m, (outs), (ins i128mem:$dst), 2208 "cmpxchg16b\t$dst", []>, 2209 TB, Requires<[HasCmpxchg16b,In64BitMode]>; 2210} // SchedRW, mayLoad, mayStore, hasSideEffects 2211 2212 2213// Lock instruction prefix 2214let SchedRW = [WriteMicrocoded] in 2215def LOCK_PREFIX : I<0xF0, PrefixByte, (outs), (ins), "lock", []>; 2216 2217let SchedRW = [WriteNop] in { 2218 2219// Rex64 instruction prefix 2220def REX64_PREFIX : I<0x48, PrefixByte, (outs), (ins), "rex64", []>, 2221 Requires<[In64BitMode]>; 2222 2223// Data16 instruction prefix 2224def DATA16_PREFIX : I<0x66, PrefixByte, (outs), (ins), "data16", []>; 2225} // SchedRW 2226 2227// Repeat string operation instruction prefixes 2228let Defs = [ECX], Uses = [ECX,DF], SchedRW = [WriteMicrocoded] in { 2229// Repeat (used with INS, OUTS, MOVS, LODS and STOS) 2230def REP_PREFIX : I<0xF3, PrefixByte, (outs), (ins), "rep", []>; 2231// Repeat while not equal (used with CMPS and SCAS) 2232def REPNE_PREFIX : I<0xF2, PrefixByte, (outs), (ins), "repne", []>; 2233} 2234 2235// String manipulation instructions 2236let SchedRW = [WriteMicrocoded] in { 2237let Defs = [AL,ESI], Uses = [ESI,DF] in 2238def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src), 2239 "lodsb\t{$src, %al|al, $src}", []>; 2240let Defs = [AX,ESI], Uses = [ESI,DF] in 2241def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src), 2242 "lodsw\t{$src, %ax|ax, $src}", []>, OpSize16; 2243let Defs = [EAX,ESI], Uses = [ESI,DF] in 2244def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src), 2245 "lods{l|d}\t{$src, %eax|eax, $src}", []>, OpSize32; 2246let Defs = [RAX,ESI], Uses = [ESI,DF] in 2247def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src), 2248 "lodsq\t{$src, %rax|rax, $src}", []>, 2249 Requires<[In64BitMode]>; 2250} 2251 2252let SchedRW = [WriteSystem] in { 2253let Defs = [ESI], Uses = [DX,ESI,DF] in { 2254def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src), 2255 "outsb\t{$src, %dx|dx, $src}", []>; 2256def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src), 2257 "outsw\t{$src, %dx|dx, $src}", []>, OpSize16; 2258def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src), 2259 "outs{l|d}\t{$src, %dx|dx, $src}", []>, OpSize32; 2260} 2261 2262let Defs = [EDI], Uses = [DX,EDI,DF] in { 2263def INSB : I<0x6C, RawFrmDst, (outs), (ins dstidx8:$dst), 2264 "insb\t{%dx, $dst|$dst, dx}", []>; 2265def INSW : I<0x6D, RawFrmDst, (outs), (ins dstidx16:$dst), 2266 "insw\t{%dx, $dst|$dst, dx}", []>, OpSize16; 2267def INSL : I<0x6D, RawFrmDst, (outs), (ins dstidx32:$dst), 2268 "ins{l|d}\t{%dx, $dst|$dst, dx}", []>, OpSize32; 2269} 2270} 2271 2272// EFLAGS management instructions. 2273let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { 2274def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; 2275def STC : I<0xF9, RawFrm, (outs), (ins), "stc", []>; 2276def CMC : I<0xF5, RawFrm, (outs), (ins), "cmc", []>; 2277} 2278 2279// DF management instructions. 2280let SchedRW = [WriteALU], Defs = [DF] in { 2281def CLD : I<0xFC, RawFrm, (outs), (ins), "cld", []>; 2282def STD : I<0xFD, RawFrm, (outs), (ins), "std", []>; 2283} 2284 2285// Table lookup instructions 2286let Uses = [AL,EBX], Defs = [AL], hasSideEffects = 0, mayLoad = 1 in 2287def XLAT : I<0xD7, RawFrm, (outs), (ins), "xlatb", []>, Sched<[WriteLoad]>; 2288 2289let SchedRW = [WriteMicrocoded] in { 2290// ASCII Adjust After Addition 2291let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2292def AAA : I<0x37, RawFrm, (outs), (ins), "aaa", []>, 2293 Requires<[Not64BitMode]>; 2294 2295// ASCII Adjust AX Before Division 2296let Uses = [AX], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2297def AAD8i8 : Ii8<0xD5, RawFrm, (outs), (ins i8imm:$src), 2298 "aad\t$src", []>, Requires<[Not64BitMode]>; 2299 2300// ASCII Adjust AX After Multiply 2301let Uses = [AL], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2302def AAM8i8 : Ii8<0xD4, RawFrm, (outs), (ins i8imm:$src), 2303 "aam\t$src", []>, Requires<[Not64BitMode]>; 2304 2305// ASCII Adjust AL After Subtraction - sets 2306let Uses = [AL,EFLAGS], Defs = [AX,EFLAGS], hasSideEffects = 0 in 2307def AAS : I<0x3F, RawFrm, (outs), (ins), "aas", []>, 2308 Requires<[Not64BitMode]>; 2309 2310// Decimal Adjust AL after Addition 2311let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 2312def DAA : I<0x27, RawFrm, (outs), (ins), "daa", []>, 2313 Requires<[Not64BitMode]>; 2314 2315// Decimal Adjust AL after Subtraction 2316let Uses = [AL,EFLAGS], Defs = [AL,EFLAGS], hasSideEffects = 0 in 2317def DAS : I<0x2F, RawFrm, (outs), (ins), "das", []>, 2318 Requires<[Not64BitMode]>; 2319} // SchedRW 2320 2321let SchedRW = [WriteSystem] in { 2322// Check Array Index Against Bounds 2323// Note: "bound" does not have reversed operands in at&t syntax. 2324def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2325 "bound\t$dst, $src", []>, OpSize16, 2326 Requires<[Not64BitMode]>; 2327def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2328 "bound\t$dst, $src", []>, OpSize32, 2329 Requires<[Not64BitMode]>; 2330 2331// Adjust RPL Field of Segment Selector 2332def ARPL16rr : I<0x63, MRMDestReg, (outs GR16:$dst), (ins GR16:$src), 2333 "arpl\t{$src, $dst|$dst, $src}", []>, 2334 Requires<[Not64BitMode]>, NotMemoryFoldable; 2335let mayStore = 1 in 2336def ARPL16mr : I<0x63, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2337 "arpl\t{$src, $dst|$dst, $src}", []>, 2338 Requires<[Not64BitMode]>, NotMemoryFoldable; 2339} // SchedRW 2340 2341//===----------------------------------------------------------------------===// 2342// MOVBE Instructions 2343// 2344let Predicates = [HasMOVBE] in { 2345 let SchedRW = [WriteALULd] in { 2346 def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2347 "movbe{w}\t{$src, $dst|$dst, $src}", 2348 [(set GR16:$dst, (bswap (loadi16 addr:$src)))]>, 2349 OpSize16, T8PS; 2350 def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2351 "movbe{l}\t{$src, $dst|$dst, $src}", 2352 [(set GR32:$dst, (bswap (loadi32 addr:$src)))]>, 2353 OpSize32, T8PS; 2354 def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2355 "movbe{q}\t{$src, $dst|$dst, $src}", 2356 [(set GR64:$dst, (bswap (loadi64 addr:$src)))]>, 2357 T8PS; 2358 } 2359 let SchedRW = [WriteStore] in { 2360 def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), 2361 "movbe{w}\t{$src, $dst|$dst, $src}", 2362 [(store (bswap GR16:$src), addr:$dst)]>, 2363 OpSize16, T8PS; 2364 def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2365 "movbe{l}\t{$src, $dst|$dst, $src}", 2366 [(store (bswap GR32:$src), addr:$dst)]>, 2367 OpSize32, T8PS; 2368 def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2369 "movbe{q}\t{$src, $dst|$dst, $src}", 2370 [(store (bswap GR64:$src), addr:$dst)]>, 2371 T8PS; 2372 } 2373} 2374 2375//===----------------------------------------------------------------------===// 2376// RDRAND Instruction 2377// 2378let Predicates = [HasRDRAND], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 2379 def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins), 2380 "rdrand{w}\t$dst", [(set GR16:$dst, EFLAGS, (X86rdrand))]>, 2381 OpSize16, PS; 2382 def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins), 2383 "rdrand{l}\t$dst", [(set GR32:$dst, EFLAGS, (X86rdrand))]>, 2384 OpSize32, PS; 2385 def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins), 2386 "rdrand{q}\t$dst", [(set GR64:$dst, EFLAGS, (X86rdrand))]>, 2387 PS; 2388} 2389 2390//===----------------------------------------------------------------------===// 2391// RDSEED Instruction 2392// 2393let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { 2394 def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins), "rdseed{w}\t$dst", 2395 [(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, PS; 2396 def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins), "rdseed{l}\t$dst", 2397 [(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, PS; 2398 def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins), "rdseed{q}\t$dst", 2399 [(set GR64:$dst, EFLAGS, (X86rdseed))]>, PS; 2400} 2401 2402//===----------------------------------------------------------------------===// 2403// LZCNT Instruction 2404// 2405let Predicates = [HasLZCNT], Defs = [EFLAGS] in { 2406 def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2407 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2408 [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, 2409 XS, OpSize16, Sched<[WriteLZCNT]>; 2410 def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2411 "lzcnt{w}\t{$src, $dst|$dst, $src}", 2412 [(set GR16:$dst, (ctlz (loadi16 addr:$src))), 2413 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteLZCNTLd]>; 2414 2415 def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2416 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2417 [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, 2418 XS, OpSize32, Sched<[WriteLZCNT]>; 2419 def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2420 "lzcnt{l}\t{$src, $dst|$dst, $src}", 2421 [(set GR32:$dst, (ctlz (loadi32 addr:$src))), 2422 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteLZCNTLd]>; 2423 2424 def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2425 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2426 [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, 2427 XS, Sched<[WriteLZCNT]>; 2428 def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2429 "lzcnt{q}\t{$src, $dst|$dst, $src}", 2430 [(set GR64:$dst, (ctlz (loadi64 addr:$src))), 2431 (implicit EFLAGS)]>, XS, Sched<[WriteLZCNTLd]>; 2432} 2433 2434//===----------------------------------------------------------------------===// 2435// BMI Instructions 2436// 2437let Predicates = [HasBMI], Defs = [EFLAGS] in { 2438 def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), 2439 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2440 [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, 2441 XS, OpSize16, Sched<[WriteTZCNT]>; 2442 def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), 2443 "tzcnt{w}\t{$src, $dst|$dst, $src}", 2444 [(set GR16:$dst, (cttz (loadi16 addr:$src))), 2445 (implicit EFLAGS)]>, XS, OpSize16, Sched<[WriteTZCNTLd]>; 2446 2447 def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), 2448 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2449 [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, 2450 XS, OpSize32, Sched<[WriteTZCNT]>; 2451 def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), 2452 "tzcnt{l}\t{$src, $dst|$dst, $src}", 2453 [(set GR32:$dst, (cttz (loadi32 addr:$src))), 2454 (implicit EFLAGS)]>, XS, OpSize32, Sched<[WriteTZCNTLd]>; 2455 2456 def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), 2457 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2458 [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, 2459 XS, Sched<[WriteTZCNT]>; 2460 def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), 2461 "tzcnt{q}\t{$src, $dst|$dst, $src}", 2462 [(set GR64:$dst, (cttz (loadi64 addr:$src))), 2463 (implicit EFLAGS)]>, XS, Sched<[WriteTZCNTLd]>; 2464} 2465 2466multiclass bmi_bls<string mnemonic, Format RegMRM, Format MemMRM, 2467 RegisterClass RC, X86MemOperand x86memop, 2468 X86FoldableSchedWrite sched> { 2469let hasSideEffects = 0 in { 2470 def rr : I<0xF3, RegMRM, (outs RC:$dst), (ins RC:$src), 2471 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 2472 T8PS, VEX_4V, Sched<[sched]>; 2473 let mayLoad = 1 in 2474 def rm : I<0xF3, MemMRM, (outs RC:$dst), (ins x86memop:$src), 2475 !strconcat(mnemonic, "\t{$src, $dst|$dst, $src}"), []>, 2476 T8PS, VEX_4V, Sched<[sched.Folded]>; 2477} 2478} 2479 2480let Predicates = [HasBMI], Defs = [EFLAGS] in { 2481 defm BLSR32 : bmi_bls<"blsr{l}", MRM1r, MRM1m, GR32, i32mem, WriteBLS>; 2482 defm BLSR64 : bmi_bls<"blsr{q}", MRM1r, MRM1m, GR64, i64mem, WriteBLS>, VEX_W; 2483 defm BLSMSK32 : bmi_bls<"blsmsk{l}", MRM2r, MRM2m, GR32, i32mem, WriteBLS>; 2484 defm BLSMSK64 : bmi_bls<"blsmsk{q}", MRM2r, MRM2m, GR64, i64mem, WriteBLS>, VEX_W; 2485 defm BLSI32 : bmi_bls<"blsi{l}", MRM3r, MRM3m, GR32, i32mem, WriteBLS>; 2486 defm BLSI64 : bmi_bls<"blsi{q}", MRM3r, MRM3m, GR64, i64mem, WriteBLS>, VEX_W; 2487} 2488 2489//===----------------------------------------------------------------------===// 2490// Pattern fragments to auto generate BMI instructions. 2491//===----------------------------------------------------------------------===// 2492 2493def or_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 2494 (X86or_flag node:$lhs, node:$rhs), [{ 2495 return hasNoCarryFlagUses(SDValue(N, 1)); 2496}]>; 2497 2498def xor_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 2499 (X86xor_flag node:$lhs, node:$rhs), [{ 2500 return hasNoCarryFlagUses(SDValue(N, 1)); 2501}]>; 2502 2503def and_flag_nocf : PatFrag<(ops node:$lhs, node:$rhs), 2504 (X86and_flag node:$lhs, node:$rhs), [{ 2505 return hasNoCarryFlagUses(SDValue(N, 1)); 2506}]>; 2507 2508let Predicates = [HasBMI] in { 2509 // FIXME: patterns for the load versions are not implemented 2510 def : Pat<(and GR32:$src, (add GR32:$src, -1)), 2511 (BLSR32rr GR32:$src)>; 2512 def : Pat<(and GR64:$src, (add GR64:$src, -1)), 2513 (BLSR64rr GR64:$src)>; 2514 2515 def : Pat<(xor GR32:$src, (add GR32:$src, -1)), 2516 (BLSMSK32rr GR32:$src)>; 2517 def : Pat<(xor GR64:$src, (add GR64:$src, -1)), 2518 (BLSMSK64rr GR64:$src)>; 2519 2520 def : Pat<(and GR32:$src, (ineg GR32:$src)), 2521 (BLSI32rr GR32:$src)>; 2522 def : Pat<(and GR64:$src, (ineg GR64:$src)), 2523 (BLSI64rr GR64:$src)>; 2524 2525 // Versions to match flag producing ops. 2526 def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, -1)), 2527 (BLSR32rr GR32:$src)>; 2528 def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, -1)), 2529 (BLSR64rr GR64:$src)>; 2530 2531 def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, -1)), 2532 (BLSMSK32rr GR32:$src)>; 2533 def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, -1)), 2534 (BLSMSK64rr GR64:$src)>; 2535 2536 def : Pat<(and_flag_nocf GR32:$src, (ineg GR32:$src)), 2537 (BLSI32rr GR32:$src)>; 2538 def : Pat<(and_flag_nocf GR64:$src, (ineg GR64:$src)), 2539 (BLSI64rr GR64:$src)>; 2540} 2541 2542multiclass bmi_bextr<bits<8> opc, string mnemonic, RegisterClass RC, 2543 X86MemOperand x86memop, SDNode OpNode, 2544 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 2545 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2546 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2547 [(set RC:$dst, (OpNode RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2548 T8PS, VEX, Sched<[Sched]>; 2549 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2550 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2551 [(set RC:$dst, (OpNode (ld_frag addr:$src1), RC:$src2)), 2552 (implicit EFLAGS)]>, T8PS, VEX, 2553 Sched<[Sched.Folded, 2554 // x86memop:$src1 2555 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 2556 ReadDefault, 2557 // RC:$src2 2558 Sched.ReadAfterFold]>; 2559} 2560 2561let Predicates = [HasBMI], Defs = [EFLAGS] in { 2562 defm BEXTR32 : bmi_bextr<0xF7, "bextr{l}", GR32, i32mem, 2563 X86bextr, loadi32, WriteBEXTR>; 2564 defm BEXTR64 : bmi_bextr<0xF7, "bextr{q}", GR64, i64mem, 2565 X86bextr, loadi64, WriteBEXTR>, VEX_W; 2566} 2567 2568multiclass bmi_bzhi<bits<8> opc, string mnemonic, RegisterClass RC, 2569 X86MemOperand x86memop, Intrinsic Int, 2570 PatFrag ld_frag, X86FoldableSchedWrite Sched> { 2571 def rr : I<opc, MRMSrcReg4VOp3, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2572 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2573 [(set RC:$dst, (Int RC:$src1, RC:$src2)), (implicit EFLAGS)]>, 2574 T8PS, VEX, Sched<[Sched]>; 2575 def rm : I<opc, MRMSrcMem4VOp3, (outs RC:$dst), (ins x86memop:$src1, RC:$src2), 2576 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2577 [(set RC:$dst, (Int (ld_frag addr:$src1), RC:$src2)), 2578 (implicit EFLAGS)]>, T8PS, VEX, 2579 Sched<[Sched.Folded, 2580 // x86memop:$src1 2581 ReadDefault, ReadDefault, ReadDefault, ReadDefault, 2582 ReadDefault, 2583 // RC:$src2 2584 Sched.ReadAfterFold]>; 2585} 2586 2587let Predicates = [HasBMI2], Defs = [EFLAGS] in { 2588 defm BZHI32 : bmi_bzhi<0xF5, "bzhi{l}", GR32, i32mem, 2589 X86bzhi, loadi32, WriteBZHI>; 2590 defm BZHI64 : bmi_bzhi<0xF5, "bzhi{q}", GR64, i64mem, 2591 X86bzhi, loadi64, WriteBZHI>, VEX_W; 2592} 2593 2594def CountTrailingOnes : SDNodeXForm<imm, [{ 2595 // Count the trailing ones in the immediate. 2596 return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N)); 2597}]>; 2598 2599def BEXTRMaskXForm : SDNodeXForm<imm, [{ 2600 unsigned Length = countTrailingOnes(N->getZExtValue()); 2601 return getI32Imm(Length << 8, SDLoc(N)); 2602}]>; 2603 2604def AndMask64 : ImmLeaf<i64, [{ 2605 return isMask_64(Imm) && !isUInt<32>(Imm); 2606}]>; 2607 2608// Use BEXTR for 64-bit 'and' with large immediate 'mask'. 2609let Predicates = [HasBMI, NoBMI2, NoTBM] in { 2610 def : Pat<(and GR64:$src, AndMask64:$mask), 2611 (BEXTR64rr GR64:$src, 2612 (SUBREG_TO_REG (i64 0), 2613 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 2614 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2615 (BEXTR64rm addr:$src, 2616 (SUBREG_TO_REG (i64 0), 2617 (MOV32ri (BEXTRMaskXForm imm:$mask)), sub_32bit))>; 2618} 2619 2620// Use BZHI for 64-bit 'and' with large immediate 'mask'. 2621let Predicates = [HasBMI2, NoTBM] in { 2622 def : Pat<(and GR64:$src, AndMask64:$mask), 2623 (BZHI64rr GR64:$src, 2624 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2625 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2626 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2627 (BZHI64rm addr:$src, 2628 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2629 (MOV8ri (CountTrailingOnes imm:$mask)), sub_8bit))>; 2630} 2631 2632multiclass bmi_pdep_pext<string mnemonic, RegisterClass RC, 2633 X86MemOperand x86memop, SDNode OpNode, 2634 PatFrag ld_frag> { 2635 def rr : I<0xF5, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), 2636 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2637 [(set RC:$dst, (OpNode RC:$src1, RC:$src2))]>, 2638 VEX_4V, Sched<[WriteALU]>; 2639 def rm : I<0xF5, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), 2640 !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), 2641 [(set RC:$dst, (OpNode RC:$src1, (ld_frag addr:$src2)))]>, 2642 VEX_4V, Sched<[WriteALU.Folded, WriteALU.ReadAfterFold]>; 2643} 2644 2645let Predicates = [HasBMI2] in { 2646 defm PDEP32 : bmi_pdep_pext<"pdep{l}", GR32, i32mem, 2647 X86pdep, loadi32>, T8XD; 2648 defm PDEP64 : bmi_pdep_pext<"pdep{q}", GR64, i64mem, 2649 X86pdep, loadi64>, T8XD, VEX_W; 2650 defm PEXT32 : bmi_pdep_pext<"pext{l}", GR32, i32mem, 2651 X86pext, loadi32>, T8XS; 2652 defm PEXT64 : bmi_pdep_pext<"pext{q}", GR64, i64mem, 2653 X86pext, loadi64>, T8XS, VEX_W; 2654} 2655 2656//===----------------------------------------------------------------------===// 2657// TBM Instructions 2658// 2659let Predicates = [HasTBM], Defs = [EFLAGS] in { 2660 2661multiclass tbm_ternary_imm<bits<8> opc, RegisterClass RC, string OpcodeStr, 2662 X86MemOperand x86memop, PatFrag ld_frag, 2663 SDNode OpNode, Operand immtype, 2664 SDPatternOperator immoperator, 2665 X86FoldableSchedWrite Sched> { 2666 def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl), 2667 !strconcat(OpcodeStr, 2668 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2669 [(set RC:$dst, (OpNode RC:$src1, immoperator:$cntl))]>, 2670 XOP, XOPA, Sched<[Sched]>; 2671 def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst), 2672 (ins x86memop:$src1, immtype:$cntl), 2673 !strconcat(OpcodeStr, 2674 "\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"), 2675 [(set RC:$dst, (OpNode (ld_frag addr:$src1), immoperator:$cntl))]>, 2676 XOP, XOPA, Sched<[Sched.Folded]>; 2677} 2678 2679defm BEXTRI32 : tbm_ternary_imm<0x10, GR32, "bextr{l}", i32mem, loadi32, 2680 X86bextr, i32imm, imm, WriteBEXTR>; 2681let ImmT = Imm32S in 2682defm BEXTRI64 : tbm_ternary_imm<0x10, GR64, "bextr{q}", i64mem, loadi64, 2683 X86bextr, i64i32imm, 2684 i64immSExt32, WriteBEXTR>, VEX_W; 2685 2686multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem, 2687 RegisterClass RC, string OpcodeStr, 2688 X86MemOperand x86memop, X86FoldableSchedWrite Sched> { 2689let hasSideEffects = 0 in { 2690 def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src), 2691 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>, 2692 XOP_4V, XOP9, Sched<[Sched]>; 2693 let mayLoad = 1 in 2694 def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src), 2695 !strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>, 2696 XOP_4V, XOP9, Sched<[Sched.Folded]>; 2697} 2698} 2699 2700multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr, 2701 X86FoldableSchedWrite Sched, 2702 Format FormReg, Format FormMem> { 2703 defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr#"{l}", 2704 i32mem, Sched>; 2705 defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr#"{q}", 2706 i64mem, Sched>, VEX_W; 2707} 2708 2709defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>; 2710defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>; 2711defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>; 2712defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>; 2713defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>; 2714defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>; 2715defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>; 2716defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>; 2717defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>; 2718} // HasTBM, EFLAGS 2719 2720// Use BEXTRI for 64-bit 'and' with large immediate 'mask'. 2721let Predicates = [HasTBM] in { 2722 def : Pat<(and GR64:$src, AndMask64:$mask), 2723 (BEXTRI64ri GR64:$src, (BEXTRMaskXForm imm:$mask))>; 2724 2725 def : Pat<(and (loadi64 addr:$src), AndMask64:$mask), 2726 (BEXTRI64mi addr:$src, (BEXTRMaskXForm imm:$mask))>; 2727} 2728 2729//===----------------------------------------------------------------------===// 2730// Lightweight Profiling Instructions 2731 2732let Predicates = [HasLWP], SchedRW = [WriteSystem] in { 2733 2734def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src", 2735 [(int_x86_llwpcb GR32:$src)]>, XOP, XOP9; 2736def SLWPCB : I<0x12, MRM1r, (outs GR32:$dst), (ins), "slwpcb\t$dst", 2737 [(set GR32:$dst, (int_x86_slwpcb))]>, XOP, XOP9; 2738 2739def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src", 2740 [(int_x86_llwpcb GR64:$src)]>, XOP, XOP9, VEX_W; 2741def SLWPCB64 : I<0x12, MRM1r, (outs GR64:$dst), (ins), "slwpcb\t$dst", 2742 [(set GR64:$dst, (int_x86_slwpcb))]>, XOP, XOP9, VEX_W; 2743 2744multiclass lwpins_intr<RegisterClass RC> { 2745 def rri : Ii32<0x12, MRM0r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2746 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2747 [(set EFLAGS, (X86lwpins RC:$src0, GR32:$src1, timm:$cntl))]>, 2748 XOP_4V, XOPA; 2749 let mayLoad = 1 in 2750 def rmi : Ii32<0x12, MRM0m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 2751 "lwpins\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2752 [(set EFLAGS, (X86lwpins RC:$src0, (loadi32 addr:$src1), timm:$cntl))]>, 2753 XOP_4V, XOPA; 2754} 2755 2756let Defs = [EFLAGS] in { 2757 defm LWPINS32 : lwpins_intr<GR32>; 2758 defm LWPINS64 : lwpins_intr<GR64>, VEX_W; 2759} // EFLAGS 2760 2761multiclass lwpval_intr<RegisterClass RC, Intrinsic Int> { 2762 def rri : Ii32<0x12, MRM1r, (outs), (ins RC:$src0, GR32:$src1, i32imm:$cntl), 2763 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2764 [(Int RC:$src0, GR32:$src1, timm:$cntl)]>, XOP_4V, XOPA; 2765 let mayLoad = 1 in 2766 def rmi : Ii32<0x12, MRM1m, (outs), (ins RC:$src0, i32mem:$src1, i32imm:$cntl), 2767 "lwpval\t{$cntl, $src1, $src0|$src0, $src1, $cntl}", 2768 [(Int RC:$src0, (loadi32 addr:$src1), timm:$cntl)]>, 2769 XOP_4V, XOPA; 2770} 2771 2772defm LWPVAL32 : lwpval_intr<GR32, int_x86_lwpval32>; 2773defm LWPVAL64 : lwpval_intr<GR64, int_x86_lwpval64>, VEX_W; 2774 2775} // HasLWP, SchedRW 2776 2777//===----------------------------------------------------------------------===// 2778// MONITORX/MWAITX Instructions 2779// 2780let SchedRW = [ WriteSystem ] in { 2781 let Uses = [ EAX, ECX, EDX ] in 2782 def MONITORX32rrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, 2783 TB, Requires<[ HasMWAITX, Not64BitMode ]>; 2784 let Uses = [ RAX, ECX, EDX ] in 2785 def MONITORX64rrr : I<0x01, MRM_FA, (outs), (ins), "monitorx", []>, 2786 TB, Requires<[ HasMWAITX, In64BitMode ]>; 2787 2788 let Uses = [ ECX, EAX, EBX ] in { 2789 def MWAITXrrr : I<0x01, MRM_FB, (outs), (ins), "mwaitx", 2790 [(int_x86_mwaitx ECX, EAX, EBX)]>, 2791 TB, Requires<[ HasMWAITX ]>; 2792 } 2793} // SchedRW 2794 2795def : InstAlias<"mwaitx\t{%eax, %ecx, %ebx|ebx, ecx, eax}", (MWAITXrrr)>, 2796 Requires<[ Not64BitMode ]>; 2797def : InstAlias<"mwaitx\t{%rax, %rcx, %rbx|rbx, rcx, rax}", (MWAITXrrr)>, 2798 Requires<[ In64BitMode ]>; 2799 2800def : InstAlias<"monitorx\t{%eax, %ecx, %edx|edx, ecx, eax}", (MONITORX32rrr)>, 2801 Requires<[ Not64BitMode ]>; 2802def : InstAlias<"monitorx\t{%rax, %rcx, %rdx|rdx, rcx, rax}", (MONITORX64rrr)>, 2803 Requires<[ In64BitMode ]>; 2804 2805//===----------------------------------------------------------------------===// 2806// WAITPKG Instructions 2807// 2808let SchedRW = [WriteSystem] in { 2809 def UMONITOR16 : I<0xAE, MRM6r, (outs), (ins GR16:$src), 2810 "umonitor\t$src", [(int_x86_umonitor GR16:$src)]>, 2811 XS, AdSize16, Requires<[HasWAITPKG, Not64BitMode]>; 2812 def UMONITOR32 : I<0xAE, MRM6r, (outs), (ins GR32:$src), 2813 "umonitor\t$src", [(int_x86_umonitor GR32:$src)]>, 2814 XS, AdSize32, Requires<[HasWAITPKG]>; 2815 def UMONITOR64 : I<0xAE, MRM6r, (outs), (ins GR64:$src), 2816 "umonitor\t$src", [(int_x86_umonitor GR64:$src)]>, 2817 XS, AdSize64, Requires<[HasWAITPKG, In64BitMode]>; 2818 let Uses = [EAX, EDX], Defs = [EFLAGS] in { 2819 def UMWAIT : I<0xAE, MRM6r, 2820 (outs), (ins GR32orGR64:$src), "umwait\t$src", 2821 [(set EFLAGS, (X86umwait GR32orGR64:$src, EDX, EAX))]>, 2822 XD, Requires<[HasWAITPKG]>; 2823 def TPAUSE : I<0xAE, MRM6r, 2824 (outs), (ins GR32orGR64:$src), "tpause\t$src", 2825 [(set EFLAGS, (X86tpause GR32orGR64:$src, EDX, EAX))]>, 2826 PD, Requires<[HasWAITPKG]>, NotMemoryFoldable; 2827 } 2828} // SchedRW 2829 2830//===----------------------------------------------------------------------===// 2831// MOVDIRI - Move doubleword/quadword as direct store 2832// 2833let SchedRW = [WriteStore] in { 2834def MOVDIRI32 : I<0xF9, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), 2835 "movdiri\t{$src, $dst|$dst, $src}", 2836 [(int_x86_directstore32 addr:$dst, GR32:$src)]>, 2837 T8PS, Requires<[HasMOVDIRI]>; 2838def MOVDIRI64 : RI<0xF9, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src), 2839 "movdiri\t{$src, $dst|$dst, $src}", 2840 [(int_x86_directstore64 addr:$dst, GR64:$src)]>, 2841 T8PS, Requires<[In64BitMode, HasMOVDIRI]>; 2842} // SchedRW 2843 2844//===----------------------------------------------------------------------===// 2845// MOVDIR64B - Move 64 bytes as direct store 2846// 2847let SchedRW = [WriteStore] in { 2848def MOVDIR64B16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 2849 "movdir64b\t{$src, $dst|$dst, $src}", []>, 2850 T8PD, AdSize16, Requires<[HasMOVDIR64B, Not64BitMode]>; 2851def MOVDIR64B32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 2852 "movdir64b\t{$src, $dst|$dst, $src}", 2853 [(int_x86_movdir64b GR32:$dst, addr:$src)]>, 2854 T8PD, AdSize32, Requires<[HasMOVDIR64B]>; 2855def MOVDIR64B64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 2856 "movdir64b\t{$src, $dst|$dst, $src}", 2857 [(int_x86_movdir64b GR64:$dst, addr:$src)]>, 2858 T8PD, AdSize64, Requires<[HasMOVDIR64B, In64BitMode]>; 2859} // SchedRW 2860 2861//===----------------------------------------------------------------------===// 2862// ENQCMD/S - Enqueue 64-byte command as user with 64-byte write atomicity 2863// 2864let SchedRW = [WriteStore], Defs = [EFLAGS] in { 2865 def ENQCMD16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 2866 "enqcmd\t{$src, $dst|$dst, $src}", 2867 [(set EFLAGS, (X86enqcmd GR16:$dst, addr:$src))]>, 2868 T8XD, AdSize16, Requires<[HasENQCMD, Not64BitMode]>; 2869 def ENQCMD32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 2870 "enqcmd\t{$src, $dst|$dst, $src}", 2871 [(set EFLAGS, (X86enqcmd GR32:$dst, addr:$src))]>, 2872 T8XD, AdSize32, Requires<[HasENQCMD]>; 2873 def ENQCMD64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 2874 "enqcmd\t{$src, $dst|$dst, $src}", 2875 [(set EFLAGS, (X86enqcmd GR64:$dst, addr:$src))]>, 2876 T8XD, AdSize64, Requires<[HasENQCMD, In64BitMode]>; 2877 2878 def ENQCMDS16 : I<0xF8, MRMSrcMem, (outs), (ins GR16:$dst, i512mem:$src), 2879 "enqcmds\t{$src, $dst|$dst, $src}", 2880 [(set EFLAGS, (X86enqcmds GR16:$dst, addr:$src))]>, 2881 T8XS, AdSize16, Requires<[HasENQCMD, Not64BitMode]>; 2882 def ENQCMDS32 : I<0xF8, MRMSrcMem, (outs), (ins GR32:$dst, i512mem:$src), 2883 "enqcmds\t{$src, $dst|$dst, $src}", 2884 [(set EFLAGS, (X86enqcmds GR32:$dst, addr:$src))]>, 2885 T8XS, AdSize32, Requires<[HasENQCMD]>; 2886 def ENQCMDS64 : I<0xF8, MRMSrcMem, (outs), (ins GR64:$dst, i512mem:$src), 2887 "enqcmds\t{$src, $dst|$dst, $src}", 2888 [(set EFLAGS, (X86enqcmds GR64:$dst, addr:$src))]>, 2889 T8XS, AdSize64, Requires<[HasENQCMD, In64BitMode]>; 2890} 2891 2892//===----------------------------------------------------------------------===// 2893// CLZERO Instruction 2894// 2895let SchedRW = [WriteLoad] in { 2896 let Uses = [EAX] in 2897 def CLZERO32r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, 2898 TB, Requires<[HasCLZERO, Not64BitMode]>; 2899 let Uses = [RAX] in 2900 def CLZERO64r : I<0x01, MRM_FC, (outs), (ins), "clzero", []>, 2901 TB, Requires<[HasCLZERO, In64BitMode]>; 2902} // SchedRW 2903 2904def : InstAlias<"clzero\t{%eax|eax}", (CLZERO32r)>, Requires<[Not64BitMode]>; 2905def : InstAlias<"clzero\t{%rax|rax}", (CLZERO64r)>, Requires<[In64BitMode]>; 2906 2907//===----------------------------------------------------------------------===// 2908// SERIALIZE Instruction 2909// 2910def SERIALIZE : I<0x01, MRM_E8, (outs), (ins), "serialize", 2911 [(int_x86_serialize)]>, PS, 2912 Requires<[HasSERIALIZE]>; 2913 2914//===----------------------------------------------------------------------===// 2915// TSXLDTRK - TSX Suspend Load Address Tracking 2916// 2917let Predicates = [HasTSXLDTRK] in { 2918 def XSUSLDTRK : I<0x01, MRM_E8, (outs), (ins), "xsusldtrk", 2919 [(int_x86_xsusldtrk)]>, XD; 2920 def XRESLDTRK : I<0x01, MRM_E9, (outs), (ins), "xresldtrk", 2921 [(int_x86_xresldtrk)]>, XD; 2922} 2923 2924//===----------------------------------------------------------------------===// 2925// Pattern fragments to auto generate TBM instructions. 2926//===----------------------------------------------------------------------===// 2927 2928let Predicates = [HasTBM] in { 2929 // FIXME: patterns for the load versions are not implemented 2930 def : Pat<(and GR32:$src, (add GR32:$src, 1)), 2931 (BLCFILL32rr GR32:$src)>; 2932 def : Pat<(and GR64:$src, (add GR64:$src, 1)), 2933 (BLCFILL64rr GR64:$src)>; 2934 2935 def : Pat<(or GR32:$src, (not (add GR32:$src, 1))), 2936 (BLCI32rr GR32:$src)>; 2937 def : Pat<(or GR64:$src, (not (add GR64:$src, 1))), 2938 (BLCI64rr GR64:$src)>; 2939 2940 // Extra patterns because opt can optimize the above patterns to this. 2941 def : Pat<(or GR32:$src, (sub -2, GR32:$src)), 2942 (BLCI32rr GR32:$src)>; 2943 def : Pat<(or GR64:$src, (sub -2, GR64:$src)), 2944 (BLCI64rr GR64:$src)>; 2945 2946 def : Pat<(and (not GR32:$src), (add GR32:$src, 1)), 2947 (BLCIC32rr GR32:$src)>; 2948 def : Pat<(and (not GR64:$src), (add GR64:$src, 1)), 2949 (BLCIC64rr GR64:$src)>; 2950 2951 def : Pat<(xor GR32:$src, (add GR32:$src, 1)), 2952 (BLCMSK32rr GR32:$src)>; 2953 def : Pat<(xor GR64:$src, (add GR64:$src, 1)), 2954 (BLCMSK64rr GR64:$src)>; 2955 2956 def : Pat<(or GR32:$src, (add GR32:$src, 1)), 2957 (BLCS32rr GR32:$src)>; 2958 def : Pat<(or GR64:$src, (add GR64:$src, 1)), 2959 (BLCS64rr GR64:$src)>; 2960 2961 def : Pat<(or GR32:$src, (add GR32:$src, -1)), 2962 (BLSFILL32rr GR32:$src)>; 2963 def : Pat<(or GR64:$src, (add GR64:$src, -1)), 2964 (BLSFILL64rr GR64:$src)>; 2965 2966 def : Pat<(or (not GR32:$src), (add GR32:$src, -1)), 2967 (BLSIC32rr GR32:$src)>; 2968 def : Pat<(or (not GR64:$src), (add GR64:$src, -1)), 2969 (BLSIC64rr GR64:$src)>; 2970 2971 def : Pat<(or (not GR32:$src), (add GR32:$src, 1)), 2972 (T1MSKC32rr GR32:$src)>; 2973 def : Pat<(or (not GR64:$src), (add GR64:$src, 1)), 2974 (T1MSKC64rr GR64:$src)>; 2975 2976 def : Pat<(and (not GR32:$src), (add GR32:$src, -1)), 2977 (TZMSK32rr GR32:$src)>; 2978 def : Pat<(and (not GR64:$src), (add GR64:$src, -1)), 2979 (TZMSK64rr GR64:$src)>; 2980 2981 // Patterns to match flag producing ops. 2982 def : Pat<(and_flag_nocf GR32:$src, (add GR32:$src, 1)), 2983 (BLCFILL32rr GR32:$src)>; 2984 def : Pat<(and_flag_nocf GR64:$src, (add GR64:$src, 1)), 2985 (BLCFILL64rr GR64:$src)>; 2986 2987 def : Pat<(or_flag_nocf GR32:$src, (not (add GR32:$src, 1))), 2988 (BLCI32rr GR32:$src)>; 2989 def : Pat<(or_flag_nocf GR64:$src, (not (add GR64:$src, 1))), 2990 (BLCI64rr GR64:$src)>; 2991 2992 // Extra patterns because opt can optimize the above patterns to this. 2993 def : Pat<(or_flag_nocf GR32:$src, (sub -2, GR32:$src)), 2994 (BLCI32rr GR32:$src)>; 2995 def : Pat<(or_flag_nocf GR64:$src, (sub -2, GR64:$src)), 2996 (BLCI64rr GR64:$src)>; 2997 2998 def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, 1)), 2999 (BLCIC32rr GR32:$src)>; 3000 def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, 1)), 3001 (BLCIC64rr GR64:$src)>; 3002 3003 def : Pat<(xor_flag_nocf GR32:$src, (add GR32:$src, 1)), 3004 (BLCMSK32rr GR32:$src)>; 3005 def : Pat<(xor_flag_nocf GR64:$src, (add GR64:$src, 1)), 3006 (BLCMSK64rr GR64:$src)>; 3007 3008 def : Pat<(or_flag_nocf GR32:$src, (add GR32:$src, 1)), 3009 (BLCS32rr GR32:$src)>; 3010 def : Pat<(or_flag_nocf GR64:$src, (add GR64:$src, 1)), 3011 (BLCS64rr GR64:$src)>; 3012 3013 def : Pat<(or_flag_nocf GR32:$src, (add GR32:$src, -1)), 3014 (BLSFILL32rr GR32:$src)>; 3015 def : Pat<(or_flag_nocf GR64:$src, (add GR64:$src, -1)), 3016 (BLSFILL64rr GR64:$src)>; 3017 3018 def : Pat<(or_flag_nocf (not GR32:$src), (add GR32:$src, -1)), 3019 (BLSIC32rr GR32:$src)>; 3020 def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, -1)), 3021 (BLSIC64rr GR64:$src)>; 3022 3023 def : Pat<(or_flag_nocf (not GR32:$src), (add GR32:$src, 1)), 3024 (T1MSKC32rr GR32:$src)>; 3025 def : Pat<(or_flag_nocf (not GR64:$src), (add GR64:$src, 1)), 3026 (T1MSKC64rr GR64:$src)>; 3027 3028 def : Pat<(and_flag_nocf (not GR32:$src), (add GR32:$src, -1)), 3029 (TZMSK32rr GR32:$src)>; 3030 def : Pat<(and_flag_nocf (not GR64:$src), (add GR64:$src, -1)), 3031 (TZMSK64rr GR64:$src)>; 3032} // HasTBM 3033 3034//===----------------------------------------------------------------------===// 3035// Memory Instructions 3036// 3037 3038let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in 3039def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), 3040 "clflushopt\t$src", [(int_x86_clflushopt addr:$src)]>, PD; 3041 3042let Predicates = [HasCLWB], SchedRW = [WriteLoad] in 3043def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src", 3044 [(int_x86_clwb addr:$src)]>, PD, NotMemoryFoldable; 3045 3046let Predicates = [HasCLDEMOTE], SchedRW = [WriteLoad] in 3047def CLDEMOTE : I<0x1C, MRM0m, (outs), (ins i8mem:$src), "cldemote\t$src", 3048 [(int_x86_cldemote addr:$src)]>, PS; 3049 3050//===----------------------------------------------------------------------===// 3051// Subsystems. 3052//===----------------------------------------------------------------------===// 3053 3054include "X86InstrArithmetic.td" 3055include "X86InstrCMovSetCC.td" 3056include "X86InstrExtension.td" 3057include "X86InstrControl.td" 3058include "X86InstrShiftRotate.td" 3059 3060// X87 Floating Point Stack. 3061include "X86InstrFPStack.td" 3062 3063// SIMD support (SSE, MMX and AVX) 3064include "X86InstrFragmentsSIMD.td" 3065 3066// FMA - Fused Multiply-Add support (requires FMA) 3067include "X86InstrFMA.td" 3068 3069// XOP 3070include "X86InstrXOP.td" 3071 3072// SSE, MMX and 3DNow! vector support. 3073include "X86InstrSSE.td" 3074include "X86InstrAVX512.td" 3075include "X86InstrMMX.td" 3076include "X86Instr3DNow.td" 3077 3078// MPX instructions 3079include "X86InstrMPX.td" 3080 3081include "X86InstrVMX.td" 3082include "X86InstrSVM.td" 3083 3084include "X86InstrTSX.td" 3085include "X86InstrSGX.td" 3086 3087// AMX instructions 3088include "X86InstrAMX.td" 3089 3090// System instructions. 3091include "X86InstrSystem.td" 3092 3093// Compiler Pseudo Instructions and Pat Patterns 3094include "X86InstrCompiler.td" 3095include "X86InstrVecCompiler.td" 3096 3097//===----------------------------------------------------------------------===// 3098// Assembler Mnemonic Aliases 3099//===----------------------------------------------------------------------===// 3100 3101def : MnemonicAlias<"call", "callw", "att">, Requires<[In16BitMode]>; 3102def : MnemonicAlias<"call", "calll", "att">, Requires<[In32BitMode]>; 3103def : MnemonicAlias<"call", "callq", "att">, Requires<[In64BitMode]>; 3104 3105def : MnemonicAlias<"cbw", "cbtw", "att">; 3106def : MnemonicAlias<"cwde", "cwtl", "att">; 3107def : MnemonicAlias<"cwd", "cwtd", "att">; 3108def : MnemonicAlias<"cdq", "cltd", "att">; 3109def : MnemonicAlias<"cdqe", "cltq", "att">; 3110def : MnemonicAlias<"cqo", "cqto", "att">; 3111 3112// In 64-bit mode lret maps to lretl; it is not ambiguous with lretq. 3113def : MnemonicAlias<"lret", "lretw", "att">, Requires<[In16BitMode]>; 3114def : MnemonicAlias<"lret", "lretl", "att">, Requires<[Not16BitMode]>; 3115 3116def : MnemonicAlias<"leavel", "leave", "att">, Requires<[Not64BitMode]>; 3117def : MnemonicAlias<"leaveq", "leave", "att">, Requires<[In64BitMode]>; 3118 3119def : MnemonicAlias<"loopz", "loope">; 3120def : MnemonicAlias<"loopnz", "loopne">; 3121 3122def : MnemonicAlias<"pop", "popw", "att">, Requires<[In16BitMode]>; 3123def : MnemonicAlias<"pop", "popl", "att">, Requires<[In32BitMode]>; 3124def : MnemonicAlias<"pop", "popq", "att">, Requires<[In64BitMode]>; 3125def : MnemonicAlias<"popf", "popfw", "att">, Requires<[In16BitMode]>; 3126def : MnemonicAlias<"popf", "popfl", "att">, Requires<[In32BitMode]>; 3127def : MnemonicAlias<"popf", "popfq", "att">, Requires<[In64BitMode]>; 3128def : MnemonicAlias<"popf", "popfq", "intel">, Requires<[In64BitMode]>; 3129def : MnemonicAlias<"popfd", "popfl", "att">; 3130def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In32BitMode]>; 3131def : MnemonicAlias<"popfw", "popf", "intel">, Requires<[In64BitMode]>; 3132 3133// FIXME: This is wrong for "push reg". "push %bx" should turn into pushw in 3134// all modes. However: "push (addr)" and "push $42" should default to 3135// pushl/pushq depending on the current mode. Similar for "pop %bx" 3136def : MnemonicAlias<"push", "pushw", "att">, Requires<[In16BitMode]>; 3137def : MnemonicAlias<"push", "pushl", "att">, Requires<[In32BitMode]>; 3138def : MnemonicAlias<"push", "pushq", "att">, Requires<[In64BitMode]>; 3139def : MnemonicAlias<"pushf", "pushfw", "att">, Requires<[In16BitMode]>; 3140def : MnemonicAlias<"pushf", "pushfl", "att">, Requires<[In32BitMode]>; 3141def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>; 3142def : MnemonicAlias<"pushf", "pushfq", "intel">, Requires<[In64BitMode]>; 3143def : MnemonicAlias<"pushfd", "pushfl", "att">; 3144def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In32BitMode]>; 3145def : MnemonicAlias<"pushfw", "pushf", "intel">, Requires<[In64BitMode]>; 3146 3147def : MnemonicAlias<"popad", "popal", "intel">, Requires<[Not64BitMode]>; 3148def : MnemonicAlias<"pushad", "pushal", "intel">, Requires<[Not64BitMode]>; 3149def : MnemonicAlias<"popa", "popaw", "intel">, Requires<[In16BitMode]>; 3150def : MnemonicAlias<"pusha", "pushaw", "intel">, Requires<[In16BitMode]>; 3151def : MnemonicAlias<"popa", "popal", "intel">, Requires<[In32BitMode]>; 3152def : MnemonicAlias<"pusha", "pushal", "intel">, Requires<[In32BitMode]>; 3153 3154def : MnemonicAlias<"popa", "popaw", "att">, Requires<[In16BitMode]>; 3155def : MnemonicAlias<"pusha", "pushaw", "att">, Requires<[In16BitMode]>; 3156def : MnemonicAlias<"popa", "popal", "att">, Requires<[In32BitMode]>; 3157def : MnemonicAlias<"pusha", "pushal", "att">, Requires<[In32BitMode]>; 3158 3159def : MnemonicAlias<"repe", "rep">; 3160def : MnemonicAlias<"repz", "rep">; 3161def : MnemonicAlias<"repnz", "repne">; 3162 3163def : MnemonicAlias<"ret", "retw", "att">, Requires<[In16BitMode]>; 3164def : MnemonicAlias<"ret", "retl", "att">, Requires<[In32BitMode]>; 3165def : MnemonicAlias<"ret", "retq", "att">, Requires<[In64BitMode]>; 3166 3167// Apply 'ret' behavior to 'retn' 3168def : MnemonicAlias<"retn", "retw", "att">, Requires<[In16BitMode]>; 3169def : MnemonicAlias<"retn", "retl", "att">, Requires<[In32BitMode]>; 3170def : MnemonicAlias<"retn", "retq", "att">, Requires<[In64BitMode]>; 3171def : MnemonicAlias<"retn", "ret", "intel">; 3172 3173def : MnemonicAlias<"sal", "shl", "intel">; 3174def : MnemonicAlias<"salb", "shlb", "att">; 3175def : MnemonicAlias<"salw", "shlw", "att">; 3176def : MnemonicAlias<"sall", "shll", "att">; 3177def : MnemonicAlias<"salq", "shlq", "att">; 3178 3179def : MnemonicAlias<"smovb", "movsb", "att">; 3180def : MnemonicAlias<"smovw", "movsw", "att">; 3181def : MnemonicAlias<"smovl", "movsl", "att">; 3182def : MnemonicAlias<"smovq", "movsq", "att">; 3183 3184def : MnemonicAlias<"ud2a", "ud2", "att">; 3185def : MnemonicAlias<"ud2bw", "ud1w", "att">; 3186def : MnemonicAlias<"ud2bl", "ud1l", "att">; 3187def : MnemonicAlias<"ud2bq", "ud1q", "att">; 3188def : MnemonicAlias<"verrw", "verr", "att">; 3189 3190// MS recognizes 'xacquire'/'xrelease' as 'acquire'/'release' 3191def : MnemonicAlias<"acquire", "xacquire", "intel">; 3192def : MnemonicAlias<"release", "xrelease", "intel">; 3193 3194// System instruction aliases. 3195def : MnemonicAlias<"iret", "iretw", "att">, Requires<[In16BitMode]>; 3196def : MnemonicAlias<"iret", "iretl", "att">, Requires<[Not16BitMode]>; 3197def : MnemonicAlias<"sysret", "sysretl", "att">; 3198def : MnemonicAlias<"sysexit", "sysexitl", "att">; 3199 3200def : MnemonicAlias<"lgdt", "lgdtw", "att">, Requires<[In16BitMode]>; 3201def : MnemonicAlias<"lgdt", "lgdtl", "att">, Requires<[In32BitMode]>; 3202def : MnemonicAlias<"lgdt", "lgdtq", "att">, Requires<[In64BitMode]>; 3203def : MnemonicAlias<"lidt", "lidtw", "att">, Requires<[In16BitMode]>; 3204def : MnemonicAlias<"lidt", "lidtl", "att">, Requires<[In32BitMode]>; 3205def : MnemonicAlias<"lidt", "lidtq", "att">, Requires<[In64BitMode]>; 3206def : MnemonicAlias<"sgdt", "sgdtw", "att">, Requires<[In16BitMode]>; 3207def : MnemonicAlias<"sgdt", "sgdtl", "att">, Requires<[In32BitMode]>; 3208def : MnemonicAlias<"sgdt", "sgdtq", "att">, Requires<[In64BitMode]>; 3209def : MnemonicAlias<"sidt", "sidtw", "att">, Requires<[In16BitMode]>; 3210def : MnemonicAlias<"sidt", "sidtl", "att">, Requires<[In32BitMode]>; 3211def : MnemonicAlias<"sidt", "sidtq", "att">, Requires<[In64BitMode]>; 3212def : MnemonicAlias<"lgdt", "lgdtw", "intel">, Requires<[In16BitMode]>; 3213def : MnemonicAlias<"lgdt", "lgdtd", "intel">, Requires<[In32BitMode]>; 3214def : MnemonicAlias<"lidt", "lidtw", "intel">, Requires<[In16BitMode]>; 3215def : MnemonicAlias<"lidt", "lidtd", "intel">, Requires<[In32BitMode]>; 3216def : MnemonicAlias<"sgdt", "sgdtw", "intel">, Requires<[In16BitMode]>; 3217def : MnemonicAlias<"sgdt", "sgdtd", "intel">, Requires<[In32BitMode]>; 3218def : MnemonicAlias<"sidt", "sidtw", "intel">, Requires<[In16BitMode]>; 3219def : MnemonicAlias<"sidt", "sidtd", "intel">, Requires<[In32BitMode]>; 3220 3221 3222// Floating point stack aliases. 3223def : MnemonicAlias<"fcmovz", "fcmove", "att">; 3224def : MnemonicAlias<"fcmova", "fcmovnbe", "att">; 3225def : MnemonicAlias<"fcmovnae", "fcmovb", "att">; 3226def : MnemonicAlias<"fcmovna", "fcmovbe", "att">; 3227def : MnemonicAlias<"fcmovae", "fcmovnb", "att">; 3228def : MnemonicAlias<"fcomip", "fcompi">; 3229def : MnemonicAlias<"fildq", "fildll", "att">; 3230def : MnemonicAlias<"fistpq", "fistpll", "att">; 3231def : MnemonicAlias<"fisttpq", "fisttpll", "att">; 3232def : MnemonicAlias<"fldcww", "fldcw", "att">; 3233def : MnemonicAlias<"fnstcww", "fnstcw", "att">; 3234def : MnemonicAlias<"fnstsww", "fnstsw", "att">; 3235def : MnemonicAlias<"fucomip", "fucompi">; 3236def : MnemonicAlias<"fwait", "wait">; 3237 3238def : MnemonicAlias<"fxsaveq", "fxsave64", "att">; 3239def : MnemonicAlias<"fxrstorq", "fxrstor64", "att">; 3240def : MnemonicAlias<"xsaveq", "xsave64", "att">; 3241def : MnemonicAlias<"xrstorq", "xrstor64", "att">; 3242def : MnemonicAlias<"xsaveoptq", "xsaveopt64", "att">; 3243def : MnemonicAlias<"xrstorsq", "xrstors64", "att">; 3244def : MnemonicAlias<"xsavecq", "xsavec64", "att">; 3245def : MnemonicAlias<"xsavesq", "xsaves64", "att">; 3246 3247class CondCodeAlias<string Prefix,string Suffix, string OldCond, string NewCond, 3248 string VariantName> 3249 : MnemonicAlias<!strconcat(Prefix, OldCond, Suffix), 3250 !strconcat(Prefix, NewCond, Suffix), VariantName>; 3251 3252/// IntegerCondCodeMnemonicAlias - This multiclass defines a bunch of 3253/// MnemonicAlias's that canonicalize the condition code in a mnemonic, for 3254/// example "setz" -> "sete". 3255multiclass IntegerCondCodeMnemonicAlias<string Prefix, string Suffix, 3256 string V = ""> { 3257 def C : CondCodeAlias<Prefix, Suffix, "c", "b", V>; // setc -> setb 3258 def Z : CondCodeAlias<Prefix, Suffix, "z" , "e", V>; // setz -> sete 3259 def NA : CondCodeAlias<Prefix, Suffix, "na", "be", V>; // setna -> setbe 3260 def NB : CondCodeAlias<Prefix, Suffix, "nb", "ae", V>; // setnb -> setae 3261 def NC : CondCodeAlias<Prefix, Suffix, "nc", "ae", V>; // setnc -> setae 3262 def NG : CondCodeAlias<Prefix, Suffix, "ng", "le", V>; // setng -> setle 3263 def NL : CondCodeAlias<Prefix, Suffix, "nl", "ge", V>; // setnl -> setge 3264 def NZ : CondCodeAlias<Prefix, Suffix, "nz", "ne", V>; // setnz -> setne 3265 def PE : CondCodeAlias<Prefix, Suffix, "pe", "p", V>; // setpe -> setp 3266 def PO : CondCodeAlias<Prefix, Suffix, "po", "np", V>; // setpo -> setnp 3267 3268 def NAE : CondCodeAlias<Prefix, Suffix, "nae", "b", V>; // setnae -> setb 3269 def NBE : CondCodeAlias<Prefix, Suffix, "nbe", "a", V>; // setnbe -> seta 3270 def NGE : CondCodeAlias<Prefix, Suffix, "nge", "l", V>; // setnge -> setl 3271 def NLE : CondCodeAlias<Prefix, Suffix, "nle", "g", V>; // setnle -> setg 3272} 3273 3274// Aliases for set<CC> 3275defm : IntegerCondCodeMnemonicAlias<"set", "">; 3276// Aliases for j<CC> 3277defm : IntegerCondCodeMnemonicAlias<"j", "">; 3278// Aliases for cmov<CC>{w,l,q} 3279defm : IntegerCondCodeMnemonicAlias<"cmov", "w", "att">; 3280defm : IntegerCondCodeMnemonicAlias<"cmov", "l", "att">; 3281defm : IntegerCondCodeMnemonicAlias<"cmov", "q", "att">; 3282// No size suffix for intel-style asm. 3283defm : IntegerCondCodeMnemonicAlias<"cmov", "", "intel">; 3284 3285 3286//===----------------------------------------------------------------------===// 3287// Assembler Instruction Aliases 3288//===----------------------------------------------------------------------===// 3289 3290// aad/aam default to base 10 if no operand is specified. 3291def : InstAlias<"aad", (AAD8i8 10)>, Requires<[Not64BitMode]>; 3292def : InstAlias<"aam", (AAM8i8 10)>, Requires<[Not64BitMode]>; 3293 3294// Disambiguate the mem/imm form of bt-without-a-suffix as btl. 3295// Likewise for btc/btr/bts. 3296def : InstAlias<"bt\t{$imm, $mem|$mem, $imm}", 3297 (BT32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 3298def : InstAlias<"btc\t{$imm, $mem|$mem, $imm}", 3299 (BTC32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 3300def : InstAlias<"btr\t{$imm, $mem|$mem, $imm}", 3301 (BTR32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 3302def : InstAlias<"bts\t{$imm, $mem|$mem, $imm}", 3303 (BTS32mi8 i32mem:$mem, i32u8imm:$imm), 0, "att">; 3304 3305// clr aliases. 3306def : InstAlias<"clr{b}\t$reg", (XOR8rr GR8 :$reg, GR8 :$reg), 0>; 3307def : InstAlias<"clr{w}\t$reg", (XOR16rr GR16:$reg, GR16:$reg), 0>; 3308def : InstAlias<"clr{l}\t$reg", (XOR32rr GR32:$reg, GR32:$reg), 0>; 3309def : InstAlias<"clr{q}\t$reg", (XOR64rr GR64:$reg, GR64:$reg), 0>; 3310 3311// lods aliases. Accept the destination being omitted because it's implicit 3312// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 3313// in the destination. 3314def : InstAlias<"lodsb\t$src", (LODSB srcidx8:$src), 0>; 3315def : InstAlias<"lodsw\t$src", (LODSW srcidx16:$src), 0>; 3316def : InstAlias<"lods{l|d}\t$src", (LODSL srcidx32:$src), 0>; 3317def : InstAlias<"lodsq\t$src", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 3318def : InstAlias<"lods\t{$src, %al|al, $src}", (LODSB srcidx8:$src), 0>; 3319def : InstAlias<"lods\t{$src, %ax|ax, $src}", (LODSW srcidx16:$src), 0>; 3320def : InstAlias<"lods\t{$src, %eax|eax, $src}", (LODSL srcidx32:$src), 0>; 3321def : InstAlias<"lods\t{$src, %rax|rax, $src}", (LODSQ srcidx64:$src), 0>, Requires<[In64BitMode]>; 3322def : InstAlias<"lods\t$src", (LODSB srcidx8:$src), 0, "intel">; 3323def : InstAlias<"lods\t$src", (LODSW srcidx16:$src), 0, "intel">; 3324def : InstAlias<"lods\t$src", (LODSL srcidx32:$src), 0, "intel">; 3325def : InstAlias<"lods\t$src", (LODSQ srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3326 3327 3328// stos aliases. Accept the source being omitted because it's implicit in 3329// the mnemonic, or the mnemonic suffix being omitted because it's implicit 3330// in the source. 3331def : InstAlias<"stosb\t$dst", (STOSB dstidx8:$dst), 0>; 3332def : InstAlias<"stosw\t$dst", (STOSW dstidx16:$dst), 0>; 3333def : InstAlias<"stos{l|d}\t$dst", (STOSL dstidx32:$dst), 0>; 3334def : InstAlias<"stosq\t$dst", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3335def : InstAlias<"stos\t{%al, $dst|$dst, al}", (STOSB dstidx8:$dst), 0>; 3336def : InstAlias<"stos\t{%ax, $dst|$dst, ax}", (STOSW dstidx16:$dst), 0>; 3337def : InstAlias<"stos\t{%eax, $dst|$dst, eax}", (STOSL dstidx32:$dst), 0>; 3338def : InstAlias<"stos\t{%rax, $dst|$dst, rax}", (STOSQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3339def : InstAlias<"stos\t$dst", (STOSB dstidx8:$dst), 0, "intel">; 3340def : InstAlias<"stos\t$dst", (STOSW dstidx16:$dst), 0, "intel">; 3341def : InstAlias<"stos\t$dst", (STOSL dstidx32:$dst), 0, "intel">; 3342def : InstAlias<"stos\t$dst", (STOSQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 3343 3344 3345// scas aliases. Accept the destination being omitted because it's implicit 3346// in the mnemonic, or the mnemonic suffix being omitted because it's implicit 3347// in the destination. 3348def : InstAlias<"scasb\t$dst", (SCASB dstidx8:$dst), 0>; 3349def : InstAlias<"scasw\t$dst", (SCASW dstidx16:$dst), 0>; 3350def : InstAlias<"scas{l|d}\t$dst", (SCASL dstidx32:$dst), 0>; 3351def : InstAlias<"scasq\t$dst", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3352def : InstAlias<"scas\t{$dst, %al|al, $dst}", (SCASB dstidx8:$dst), 0>; 3353def : InstAlias<"scas\t{$dst, %ax|ax, $dst}", (SCASW dstidx16:$dst), 0>; 3354def : InstAlias<"scas\t{$dst, %eax|eax, $dst}", (SCASL dstidx32:$dst), 0>; 3355def : InstAlias<"scas\t{$dst, %rax|rax, $dst}", (SCASQ dstidx64:$dst), 0>, Requires<[In64BitMode]>; 3356def : InstAlias<"scas\t$dst", (SCASB dstidx8:$dst), 0, "intel">; 3357def : InstAlias<"scas\t$dst", (SCASW dstidx16:$dst), 0, "intel">; 3358def : InstAlias<"scas\t$dst", (SCASL dstidx32:$dst), 0, "intel">; 3359def : InstAlias<"scas\t$dst", (SCASQ dstidx64:$dst), 0, "intel">, Requires<[In64BitMode]>; 3360 3361// cmps aliases. Mnemonic suffix being omitted because it's implicit 3362// in the destination. 3363def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 3364def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 3365def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 3366def : InstAlias<"cmps\t{$dst, $src|$src, $dst}", (CMPSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3367 3368// movs aliases. Mnemonic suffix being omitted because it's implicit 3369// in the destination. 3370def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSB dstidx8:$dst, srcidx8:$src), 0, "intel">; 3371def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSW dstidx16:$dst, srcidx16:$src), 0, "intel">; 3372def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSL dstidx32:$dst, srcidx32:$src), 0, "intel">; 3373def : InstAlias<"movs\t{$src, $dst|$dst, $src}", (MOVSQ dstidx64:$dst, srcidx64:$src), 0, "intel">, Requires<[In64BitMode]>; 3374 3375// div and idiv aliases for explicit A register. 3376def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8r GR8 :$src)>; 3377def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16r GR16:$src)>; 3378def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32r GR32:$src)>; 3379def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64r GR64:$src)>; 3380def : InstAlias<"div{b}\t{$src, %al|al, $src}", (DIV8m i8mem :$src)>; 3381def : InstAlias<"div{w}\t{$src, %ax|ax, $src}", (DIV16m i16mem:$src)>; 3382def : InstAlias<"div{l}\t{$src, %eax|eax, $src}", (DIV32m i32mem:$src)>; 3383def : InstAlias<"div{q}\t{$src, %rax|rax, $src}", (DIV64m i64mem:$src)>; 3384def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8r GR8 :$src)>; 3385def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16r GR16:$src)>; 3386def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32r GR32:$src)>; 3387def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64r GR64:$src)>; 3388def : InstAlias<"idiv{b}\t{$src, %al|al, $src}", (IDIV8m i8mem :$src)>; 3389def : InstAlias<"idiv{w}\t{$src, %ax|ax, $src}", (IDIV16m i16mem:$src)>; 3390def : InstAlias<"idiv{l}\t{$src, %eax|eax, $src}", (IDIV32m i32mem:$src)>; 3391def : InstAlias<"idiv{q}\t{$src, %rax|rax, $src}", (IDIV64m i64mem:$src)>; 3392 3393 3394 3395// Various unary fpstack operations default to operating on ST1. 3396// For example, "fxch" -> "fxch %st(1)" 3397def : InstAlias<"faddp", (ADD_FPrST0 ST1), 0>; 3398def: InstAlias<"fadd", (ADD_FPrST0 ST1), 0>; 3399def : InstAlias<"fsub{|r}p", (SUBR_FPrST0 ST1), 0>; 3400def : InstAlias<"fsub{r|}p", (SUB_FPrST0 ST1), 0>; 3401def : InstAlias<"fmul", (MUL_FPrST0 ST1), 0>; 3402def : InstAlias<"fmulp", (MUL_FPrST0 ST1), 0>; 3403def : InstAlias<"fdiv{|r}p", (DIVR_FPrST0 ST1), 0>; 3404def : InstAlias<"fdiv{r|}p", (DIV_FPrST0 ST1), 0>; 3405def : InstAlias<"fxch", (XCH_F ST1), 0>; 3406def : InstAlias<"fcom", (COM_FST0r ST1), 0>; 3407def : InstAlias<"fcomp", (COMP_FST0r ST1), 0>; 3408def : InstAlias<"fcomi", (COM_FIr ST1), 0>; 3409def : InstAlias<"fcompi", (COM_FIPr ST1), 0>; 3410def : InstAlias<"fucom", (UCOM_Fr ST1), 0>; 3411def : InstAlias<"fucomp", (UCOM_FPr ST1), 0>; 3412def : InstAlias<"fucomi", (UCOM_FIr ST1), 0>; 3413def : InstAlias<"fucompi", (UCOM_FIPr ST1), 0>; 3414 3415// Handle fmul/fadd/fsub/fdiv instructions with explicitly written st(0) op. 3416// For example, "fadd %st(4), %st(0)" -> "fadd %st(4)". We also disambiguate 3417// instructions like "fadd %st(0), %st(0)" as "fadd %st(0)" for consistency with 3418// gas. 3419multiclass FpUnaryAlias<string Mnemonic, Instruction Inst, bit EmitAlias = 1> { 3420 def : InstAlias<!strconcat(Mnemonic, "\t$op"), 3421 (Inst RSTi:$op), EmitAlias>; 3422 def : InstAlias<!strconcat(Mnemonic, "\t{%st, %st|st, st}"), 3423 (Inst ST0), EmitAlias>; 3424} 3425 3426defm : FpUnaryAlias<"fadd", ADD_FST0r, 0>; 3427defm : FpUnaryAlias<"faddp", ADD_FPrST0, 0>; 3428defm : FpUnaryAlias<"fsub", SUB_FST0r, 0>; 3429defm : FpUnaryAlias<"fsub{|r}p", SUBR_FPrST0, 0>; 3430defm : FpUnaryAlias<"fsubr", SUBR_FST0r, 0>; 3431defm : FpUnaryAlias<"fsub{r|}p", SUB_FPrST0, 0>; 3432defm : FpUnaryAlias<"fmul", MUL_FST0r, 0>; 3433defm : FpUnaryAlias<"fmulp", MUL_FPrST0, 0>; 3434defm : FpUnaryAlias<"fdiv", DIV_FST0r, 0>; 3435defm : FpUnaryAlias<"fdiv{|r}p", DIVR_FPrST0, 0>; 3436defm : FpUnaryAlias<"fdivr", DIVR_FST0r, 0>; 3437defm : FpUnaryAlias<"fdiv{r|}p", DIV_FPrST0, 0>; 3438defm : FpUnaryAlias<"fcomi", COM_FIr, 0>; 3439defm : FpUnaryAlias<"fucomi", UCOM_FIr, 0>; 3440defm : FpUnaryAlias<"fcompi", COM_FIPr, 0>; 3441defm : FpUnaryAlias<"fucompi", UCOM_FIPr, 0>; 3442 3443 3444// Handle "f{mulp,addp} $op, %st(0)" the same as "f{mulp,addp} $op", since they 3445// commute. We also allow fdiv[r]p/fsubrp even though they don't commute, 3446// solely because gas supports it. 3447def : InstAlias<"faddp\t{$op, %st|st, $op}", (ADD_FPrST0 RSTi:$op), 0>; 3448def : InstAlias<"fmulp\t{$op, %st|st, $op}", (MUL_FPrST0 RSTi:$op), 0>; 3449def : InstAlias<"fsub{|r}p\t{$op, %st|st, $op}", (SUBR_FPrST0 RSTi:$op), 0>; 3450def : InstAlias<"fsub{r|}p\t{$op, %st|st, $op}", (SUB_FPrST0 RSTi:$op), 0>; 3451def : InstAlias<"fdiv{|r}p\t{$op, %st|st, $op}", (DIVR_FPrST0 RSTi:$op), 0>; 3452def : InstAlias<"fdiv{r|}p\t{$op, %st|st, $op}", (DIV_FPrST0 RSTi:$op), 0>; 3453 3454def : InstAlias<"fnstsw" , (FNSTSW16r), 0>; 3455 3456// lcall and ljmp aliases. This seems to be an odd mapping in 64-bit mode, but 3457// this is compatible with what GAS does. 3458def : InstAlias<"lcall\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 3459def : InstAlias<"ljmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg), 0>, Requires<[In32BitMode]>; 3460def : InstAlias<"lcall\t{*}$dst", (FARCALL32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 3461def : InstAlias<"ljmp\t{*}$dst", (FARJMP32m opaquemem:$dst), 0>, Requires<[Not16BitMode]>; 3462def : InstAlias<"lcall\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 3463def : InstAlias<"ljmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg), 0>, Requires<[In16BitMode]>; 3464def : InstAlias<"lcall\t{*}$dst", (FARCALL16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 3465def : InstAlias<"ljmp\t{*}$dst", (FARJMP16m opaquemem:$dst), 0>, Requires<[In16BitMode]>; 3466 3467def : InstAlias<"jmp\t{*}$dst", (JMP64m i64mem:$dst), 0, "att">, Requires<[In64BitMode]>; 3468def : InstAlias<"jmp\t{*}$dst", (JMP32m i32mem:$dst), 0, "att">, Requires<[In32BitMode]>; 3469def : InstAlias<"jmp\t{*}$dst", (JMP16m i16mem:$dst), 0, "att">, Requires<[In16BitMode]>; 3470 3471 3472// "imul <imm>, B" is an alias for "imul <imm>, B, B". 3473def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri GR16:$r, GR16:$r, i16imm:$imm), 0>; 3474def : InstAlias<"imul{w}\t{$imm, $r|$r, $imm}", (IMUL16rri8 GR16:$r, GR16:$r, i16i8imm:$imm), 0>; 3475def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri GR32:$r, GR32:$r, i32imm:$imm), 0>; 3476def : InstAlias<"imul{l}\t{$imm, $r|$r, $imm}", (IMUL32rri8 GR32:$r, GR32:$r, i32i8imm:$imm), 0>; 3477def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri32 GR64:$r, GR64:$r, i64i32imm:$imm), 0>; 3478def : InstAlias<"imul{q}\t{$imm, $r|$r, $imm}", (IMUL64rri8 GR64:$r, GR64:$r, i64i8imm:$imm), 0>; 3479 3480// ins aliases. Accept the mnemonic suffix being omitted because it's implicit 3481// in the destination. 3482def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSB dstidx8:$dst), 0, "intel">; 3483def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSW dstidx16:$dst), 0, "intel">; 3484def : InstAlias<"ins\t{%dx, $dst|$dst, dx}", (INSL dstidx32:$dst), 0, "intel">; 3485 3486// outs aliases. Accept the mnemonic suffix being omitted because it's implicit 3487// in the source. 3488def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSB srcidx8:$src), 0, "intel">; 3489def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSW srcidx16:$src), 0, "intel">; 3490def : InstAlias<"outs\t{$src, %dx|dx, $src}", (OUTSL srcidx32:$src), 0, "intel">; 3491 3492// inb %dx -> inb %al, %dx 3493def : InstAlias<"inb\t{%dx|dx}", (IN8rr), 0>; 3494def : InstAlias<"inw\t{%dx|dx}", (IN16rr), 0>; 3495def : InstAlias<"inl\t{%dx|dx}", (IN32rr), 0>; 3496def : InstAlias<"inb\t$port", (IN8ri u8imm:$port), 0>; 3497def : InstAlias<"inw\t$port", (IN16ri u8imm:$port), 0>; 3498def : InstAlias<"inl\t$port", (IN32ri u8imm:$port), 0>; 3499 3500 3501// jmp and call aliases for lcall and ljmp. jmp $42,$5 -> ljmp 3502def : InstAlias<"call\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 3503def : InstAlias<"jmp\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[In16BitMode]>; 3504def : InstAlias<"call\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 3505def : InstAlias<"jmp\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[In32BitMode]>; 3506def : InstAlias<"callw\t$seg, $off", (FARCALL16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3507def : InstAlias<"jmpw\t$seg, $off", (FARJMP16i i16imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3508def : InstAlias<"calll\t$seg, $off", (FARCALL32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3509def : InstAlias<"jmpl\t$seg, $off", (FARJMP32i i32imm:$off, i16imm:$seg)>, Requires<[Not64BitMode]>; 3510 3511// Match 'movq <largeimm>, <reg>' as an alias for movabsq. 3512def : InstAlias<"mov{q}\t{$imm, $reg|$reg, $imm}", (MOV64ri GR64:$reg, i64imm:$imm), 0>; 3513 3514// Match 'movd GR64, MMX' as an alias for movq to be compatible with gas, 3515// which supports this due to an old AMD documentation bug when 64-bit mode was 3516// created. 3517def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 3518 (MMX_MOVD64to64rr VR64:$dst, GR64:$src), 0>; 3519def : InstAlias<"movd\t{$src, $dst|$dst, $src}", 3520 (MMX_MOVD64from64rr GR64:$dst, VR64:$src), 0>; 3521 3522// movsx aliases 3523def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rr8 GR16:$dst, GR8:$src), 0, "att">; 3524def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 3525def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr8 GR32:$dst, GR8:$src), 0, "att">; 3526def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX32rr16 GR32:$dst, GR16:$src), 0, "att">; 3527def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr8 GR64:$dst, GR8:$src), 0, "att">; 3528def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr16 GR64:$dst, GR16:$src), 0, "att">; 3529def : InstAlias<"movsx\t{$src, $dst|$dst, $src}", (MOVSX64rr32 GR64:$dst, GR32:$src), 0, "att">; 3530 3531// movzx aliases 3532def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rr8 GR16:$dst, GR8:$src), 0, "att">; 3533def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX16rm8 GR16:$dst, i8mem:$src), 0, "att">; 3534def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr8 GR32:$dst, GR8:$src), 0, "att">; 3535def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX32rr16 GR32:$dst, GR16:$src), 0, "att">; 3536def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr8 GR64:$dst, GR8:$src), 0, "att">; 3537def : InstAlias<"movzx\t{$src, $dst|$dst, $src}", (MOVZX64rr16 GR64:$dst, GR16:$src), 0, "att">; 3538// Note: No GR32->GR64 movzx form. 3539 3540// outb %dx -> outb %al, %dx 3541def : InstAlias<"outb\t{%dx|dx}", (OUT8rr), 0>; 3542def : InstAlias<"outw\t{%dx|dx}", (OUT16rr), 0>; 3543def : InstAlias<"outl\t{%dx|dx}", (OUT32rr), 0>; 3544def : InstAlias<"outb\t$port", (OUT8ir u8imm:$port), 0>; 3545def : InstAlias<"outw\t$port", (OUT16ir u8imm:$port), 0>; 3546def : InstAlias<"outl\t$port", (OUT32ir u8imm:$port), 0>; 3547 3548// 'sldt <mem>' can be encoded with either sldtw or sldtq with the same 3549// effect (both store to a 16-bit mem). Force to sldtw to avoid ambiguity 3550// errors, since its encoding is the most compact. 3551def : InstAlias<"sldt $mem", (SLDT16m i16mem:$mem), 0>; 3552 3553// shld/shrd op,op -> shld op, op, CL 3554def : InstAlias<"shld{w}\t{$r2, $r1|$r1, $r2}", (SHLD16rrCL GR16:$r1, GR16:$r2), 0>; 3555def : InstAlias<"shld{l}\t{$r2, $r1|$r1, $r2}", (SHLD32rrCL GR32:$r1, GR32:$r2), 0>; 3556def : InstAlias<"shld{q}\t{$r2, $r1|$r1, $r2}", (SHLD64rrCL GR64:$r1, GR64:$r2), 0>; 3557def : InstAlias<"shrd{w}\t{$r2, $r1|$r1, $r2}", (SHRD16rrCL GR16:$r1, GR16:$r2), 0>; 3558def : InstAlias<"shrd{l}\t{$r2, $r1|$r1, $r2}", (SHRD32rrCL GR32:$r1, GR32:$r2), 0>; 3559def : InstAlias<"shrd{q}\t{$r2, $r1|$r1, $r2}", (SHRD64rrCL GR64:$r1, GR64:$r2), 0>; 3560 3561def : InstAlias<"shld{w}\t{$reg, $mem|$mem, $reg}", (SHLD16mrCL i16mem:$mem, GR16:$reg), 0>; 3562def : InstAlias<"shld{l}\t{$reg, $mem|$mem, $reg}", (SHLD32mrCL i32mem:$mem, GR32:$reg), 0>; 3563def : InstAlias<"shld{q}\t{$reg, $mem|$mem, $reg}", (SHLD64mrCL i64mem:$mem, GR64:$reg), 0>; 3564def : InstAlias<"shrd{w}\t{$reg, $mem|$mem, $reg}", (SHRD16mrCL i16mem:$mem, GR16:$reg), 0>; 3565def : InstAlias<"shrd{l}\t{$reg, $mem|$mem, $reg}", (SHRD32mrCL i32mem:$mem, GR32:$reg), 0>; 3566def : InstAlias<"shrd{q}\t{$reg, $mem|$mem, $reg}", (SHRD64mrCL i64mem:$mem, GR64:$reg), 0>; 3567 3568/* FIXME: This is disabled because the asm matcher is currently incapable of 3569 * matching a fixed immediate like $1. 3570// "shl X, $1" is an alias for "shl X". 3571multiclass ShiftRotateByOneAlias<string Mnemonic, string Opc> { 3572 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 3573 (!cast<Instruction>(!strconcat(Opc, "8r1")) GR8:$op)>; 3574 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 3575 (!cast<Instruction>(!strconcat(Opc, "16r1")) GR16:$op)>; 3576 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 3577 (!cast<Instruction>(!strconcat(Opc, "32r1")) GR32:$op)>; 3578 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 3579 (!cast<Instruction>(!strconcat(Opc, "64r1")) GR64:$op)>; 3580 def : InstAlias<!strconcat(Mnemonic, "b $op, $$1"), 3581 (!cast<Instruction>(!strconcat(Opc, "8m1")) i8mem:$op)>; 3582 def : InstAlias<!strconcat(Mnemonic, "w $op, $$1"), 3583 (!cast<Instruction>(!strconcat(Opc, "16m1")) i16mem:$op)>; 3584 def : InstAlias<!strconcat(Mnemonic, "l $op, $$1"), 3585 (!cast<Instruction>(!strconcat(Opc, "32m1")) i32mem:$op)>; 3586 def : InstAlias<!strconcat(Mnemonic, "q $op, $$1"), 3587 (!cast<Instruction>(!strconcat(Opc, "64m1")) i64mem:$op)>; 3588} 3589 3590defm : ShiftRotateByOneAlias<"rcl", "RCL">; 3591defm : ShiftRotateByOneAlias<"rcr", "RCR">; 3592defm : ShiftRotateByOneAlias<"rol", "ROL">; 3593defm : ShiftRotateByOneAlias<"ror", "ROR">; 3594FIXME */ 3595 3596// test: We accept "testX <reg>, <mem>" and "testX <mem>, <reg>" as synonyms. 3597def : InstAlias<"test{b}\t{$mem, $val|$val, $mem}", 3598 (TEST8mr i8mem :$mem, GR8 :$val), 0>; 3599def : InstAlias<"test{w}\t{$mem, $val|$val, $mem}", 3600 (TEST16mr i16mem:$mem, GR16:$val), 0>; 3601def : InstAlias<"test{l}\t{$mem, $val|$val, $mem}", 3602 (TEST32mr i32mem:$mem, GR32:$val), 0>; 3603def : InstAlias<"test{q}\t{$mem, $val|$val, $mem}", 3604 (TEST64mr i64mem:$mem, GR64:$val), 0>; 3605 3606// xchg: We accept "xchgX <reg>, <mem>" and "xchgX <mem>, <reg>" as synonyms. 3607def : InstAlias<"xchg{b}\t{$mem, $val|$val, $mem}", 3608 (XCHG8rm GR8 :$val, i8mem :$mem), 0>; 3609def : InstAlias<"xchg{w}\t{$mem, $val|$val, $mem}", 3610 (XCHG16rm GR16:$val, i16mem:$mem), 0>; 3611def : InstAlias<"xchg{l}\t{$mem, $val|$val, $mem}", 3612 (XCHG32rm GR32:$val, i32mem:$mem), 0>; 3613def : InstAlias<"xchg{q}\t{$mem, $val|$val, $mem}", 3614 (XCHG64rm GR64:$val, i64mem:$mem), 0>; 3615 3616// xchg: We accept "xchgX <reg>, %eax" and "xchgX %eax, <reg>" as synonyms. 3617def : InstAlias<"xchg{w}\t{%ax, $src|$src, ax}", (XCHG16ar GR16:$src), 0>; 3618def : InstAlias<"xchg{l}\t{%eax, $src|$src, eax}", (XCHG32ar GR32:$src), 0>; 3619def : InstAlias<"xchg{q}\t{%rax, $src|$src, rax}", (XCHG64ar GR64:$src), 0>; 3620 3621// In 64-bit mode, xchg %eax, %eax can't be encoded with the 0x90 opcode we 3622// would get by default because it's defined as NOP. But xchg %eax, %eax implies 3623// implicit zeroing of the upper 32 bits. So alias to the longer encoding. 3624def : InstAlias<"xchg{l}\t{%eax, %eax|eax, eax}", 3625 (XCHG32rr EAX, EAX), 0>, Requires<[In64BitMode]>; 3626 3627// xchg %rax, %rax is a nop in x86-64 and can be encoded as such. Without this 3628// we emit an unneeded REX.w prefix. 3629def : InstAlias<"xchg{q}\t{%rax, %rax|rax, rax}", (NOOP), 0>; 3630 3631// These aliases exist to get the parser to prioritize matching 8-bit 3632// immediate encodings over matching the implicit ax/eax/rax encodings. By 3633// explicitly mentioning the A register here, these entries will be ordered 3634// first due to the more explicit immediate type. 3635def : InstAlias<"adc{w}\t{$imm, %ax|ax, $imm}", (ADC16ri8 AX, i16i8imm:$imm), 0>; 3636def : InstAlias<"add{w}\t{$imm, %ax|ax, $imm}", (ADD16ri8 AX, i16i8imm:$imm), 0>; 3637def : InstAlias<"and{w}\t{$imm, %ax|ax, $imm}", (AND16ri8 AX, i16i8imm:$imm), 0>; 3638def : InstAlias<"cmp{w}\t{$imm, %ax|ax, $imm}", (CMP16ri8 AX, i16i8imm:$imm), 0>; 3639def : InstAlias<"or{w}\t{$imm, %ax|ax, $imm}", (OR16ri8 AX, i16i8imm:$imm), 0>; 3640def : InstAlias<"sbb{w}\t{$imm, %ax|ax, $imm}", (SBB16ri8 AX, i16i8imm:$imm), 0>; 3641def : InstAlias<"sub{w}\t{$imm, %ax|ax, $imm}", (SUB16ri8 AX, i16i8imm:$imm), 0>; 3642def : InstAlias<"xor{w}\t{$imm, %ax|ax, $imm}", (XOR16ri8 AX, i16i8imm:$imm), 0>; 3643 3644def : InstAlias<"adc{l}\t{$imm, %eax|eax, $imm}", (ADC32ri8 EAX, i32i8imm:$imm), 0>; 3645def : InstAlias<"add{l}\t{$imm, %eax|eax, $imm}", (ADD32ri8 EAX, i32i8imm:$imm), 0>; 3646def : InstAlias<"and{l}\t{$imm, %eax|eax, $imm}", (AND32ri8 EAX, i32i8imm:$imm), 0>; 3647def : InstAlias<"cmp{l}\t{$imm, %eax|eax, $imm}", (CMP32ri8 EAX, i32i8imm:$imm), 0>; 3648def : InstAlias<"or{l}\t{$imm, %eax|eax, $imm}", (OR32ri8 EAX, i32i8imm:$imm), 0>; 3649def : InstAlias<"sbb{l}\t{$imm, %eax|eax, $imm}", (SBB32ri8 EAX, i32i8imm:$imm), 0>; 3650def : InstAlias<"sub{l}\t{$imm, %eax|eax, $imm}", (SUB32ri8 EAX, i32i8imm:$imm), 0>; 3651def : InstAlias<"xor{l}\t{$imm, %eax|eax, $imm}", (XOR32ri8 EAX, i32i8imm:$imm), 0>; 3652 3653def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>; 3654def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>; 3655def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>; 3656def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>; 3657def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>; 3658def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>; 3659def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>; 3660def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>; 3661