1//===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains small standalone helper functions and enum definitions for 10// the X86 target useful for the compiler back-end and the MC libraries. 11// As such, it deliberately does not include references to LLVM core 12// code gen types, passes, etc.. 13// 14//===----------------------------------------------------------------------===// 15 16#ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 17#define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H 18 19#include "X86MCTargetDesc.h" 20#include "llvm/MC/MCInstrDesc.h" 21#include "llvm/Support/DataTypes.h" 22#include "llvm/Support/ErrorHandling.h" 23 24namespace llvm { 25 26namespace X86 { 27 // Enums for memory operand decoding. Each memory operand is represented with 28 // a 5 operand sequence in the form: 29 // [BaseReg, ScaleAmt, IndexReg, Disp, Segment] 30 // These enums help decode this. 31 enum { 32 AddrBaseReg = 0, 33 AddrScaleAmt = 1, 34 AddrIndexReg = 2, 35 AddrDisp = 3, 36 37 /// AddrSegmentReg - The operand # of the segment in the memory operand. 38 AddrSegmentReg = 4, 39 40 /// AddrNumOperands - Total number of operands in a memory reference. 41 AddrNumOperands = 5 42 }; 43 44 /// AVX512 static rounding constants. These need to match the values in 45 /// avx512fintrin.h. 46 enum STATIC_ROUNDING { 47 TO_NEAREST_INT = 0, 48 TO_NEG_INF = 1, 49 TO_POS_INF = 2, 50 TO_ZERO = 3, 51 CUR_DIRECTION = 4, 52 NO_EXC = 8 53 }; 54 55 /// The constants to describe instr prefixes if there are 56 enum IPREFIXES { 57 IP_NO_PREFIX = 0, 58 IP_HAS_OP_SIZE = 1, 59 IP_HAS_AD_SIZE = 2, 60 IP_HAS_REPEAT_NE = 4, 61 IP_HAS_REPEAT = 8, 62 IP_HAS_LOCK = 16, 63 IP_HAS_NOTRACK = 32, 64 IP_USE_VEX3 = 64, 65 }; 66 67 enum OperandType : unsigned { 68 /// AVX512 embedded rounding control. This should only have values 0-3. 69 OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET, 70 OPERAND_COND_CODE, 71 }; 72 73 // X86 specific condition code. These correspond to X86_*_COND in 74 // X86InstrInfo.td. They must be kept in synch. 75 enum CondCode { 76 COND_O = 0, 77 COND_NO = 1, 78 COND_B = 2, 79 COND_AE = 3, 80 COND_E = 4, 81 COND_NE = 5, 82 COND_BE = 6, 83 COND_A = 7, 84 COND_S = 8, 85 COND_NS = 9, 86 COND_P = 10, 87 COND_NP = 11, 88 COND_L = 12, 89 COND_GE = 13, 90 COND_LE = 14, 91 COND_G = 15, 92 LAST_VALID_COND = COND_G, 93 94 // Artificial condition codes. These are used by analyzeBranch 95 // to indicate a block terminated with two conditional branches that together 96 // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE, 97 // which can't be represented on x86 with a single condition. These 98 // are never used in MachineInstrs and are inverses of one another. 99 COND_NE_OR_P, 100 COND_E_AND_NP, 101 102 COND_INVALID 103 }; 104 105 // The classification for the first instruction in macro fusion. 106 enum class FirstMacroFusionInstKind { 107 // TEST 108 Test, 109 // CMP 110 Cmp, 111 // AND 112 And, 113 // ADD, SUB 114 AddSub, 115 // INC, DEC 116 IncDec, 117 // Not valid as a first macro fusion instruction 118 Invalid 119 }; 120 121 enum class SecondMacroFusionInstKind { 122 // JA, JB and variants. 123 AB, 124 // JE, JL, JG and variants. 125 ELG, 126 // JS, JP, JO and variants 127 SPO, 128 // Not a fusible jump. 129 Invalid, 130 }; 131 132 /// \returns the type of the first instruction in macro-fusion. 133 inline FirstMacroFusionInstKind 134 classifyFirstOpcodeInMacroFusion(unsigned Opcode) { 135 switch (Opcode) { 136 default: 137 return FirstMacroFusionInstKind::Invalid; 138 // TEST 139 case X86::TEST16i16: 140 case X86::TEST16mr: 141 case X86::TEST16ri: 142 case X86::TEST16rr: 143 case X86::TEST32i32: 144 case X86::TEST32mr: 145 case X86::TEST32ri: 146 case X86::TEST32rr: 147 case X86::TEST64i32: 148 case X86::TEST64mr: 149 case X86::TEST64ri32: 150 case X86::TEST64rr: 151 case X86::TEST8i8: 152 case X86::TEST8mr: 153 case X86::TEST8ri: 154 case X86::TEST8rr: 155 return FirstMacroFusionInstKind::Test; 156 case X86::AND16i16: 157 case X86::AND16ri: 158 case X86::AND16ri8: 159 case X86::AND16rm: 160 case X86::AND16rr: 161 case X86::AND16rr_REV: 162 case X86::AND32i32: 163 case X86::AND32ri: 164 case X86::AND32ri8: 165 case X86::AND32rm: 166 case X86::AND32rr: 167 case X86::AND32rr_REV: 168 case X86::AND64i32: 169 case X86::AND64ri32: 170 case X86::AND64ri8: 171 case X86::AND64rm: 172 case X86::AND64rr: 173 case X86::AND64rr_REV: 174 case X86::AND8i8: 175 case X86::AND8ri: 176 case X86::AND8ri8: 177 case X86::AND8rm: 178 case X86::AND8rr: 179 case X86::AND8rr_REV: 180 return FirstMacroFusionInstKind::And; 181 // CMP 182 case X86::CMP16i16: 183 case X86::CMP16mr: 184 case X86::CMP16ri: 185 case X86::CMP16ri8: 186 case X86::CMP16rm: 187 case X86::CMP16rr: 188 case X86::CMP16rr_REV: 189 case X86::CMP32i32: 190 case X86::CMP32mr: 191 case X86::CMP32ri: 192 case X86::CMP32ri8: 193 case X86::CMP32rm: 194 case X86::CMP32rr: 195 case X86::CMP32rr_REV: 196 case X86::CMP64i32: 197 case X86::CMP64mr: 198 case X86::CMP64ri32: 199 case X86::CMP64ri8: 200 case X86::CMP64rm: 201 case X86::CMP64rr: 202 case X86::CMP64rr_REV: 203 case X86::CMP8i8: 204 case X86::CMP8mr: 205 case X86::CMP8ri: 206 case X86::CMP8ri8: 207 case X86::CMP8rm: 208 case X86::CMP8rr: 209 case X86::CMP8rr_REV: 210 return FirstMacroFusionInstKind::Cmp; 211 // ADD 212 case X86::ADD16i16: 213 case X86::ADD16ri: 214 case X86::ADD16ri8: 215 case X86::ADD16rm: 216 case X86::ADD16rr: 217 case X86::ADD16rr_REV: 218 case X86::ADD32i32: 219 case X86::ADD32ri: 220 case X86::ADD32ri8: 221 case X86::ADD32rm: 222 case X86::ADD32rr: 223 case X86::ADD32rr_REV: 224 case X86::ADD64i32: 225 case X86::ADD64ri32: 226 case X86::ADD64ri8: 227 case X86::ADD64rm: 228 case X86::ADD64rr: 229 case X86::ADD64rr_REV: 230 case X86::ADD8i8: 231 case X86::ADD8ri: 232 case X86::ADD8ri8: 233 case X86::ADD8rm: 234 case X86::ADD8rr: 235 case X86::ADD8rr_REV: 236 // SUB 237 case X86::SUB16i16: 238 case X86::SUB16ri: 239 case X86::SUB16ri8: 240 case X86::SUB16rm: 241 case X86::SUB16rr: 242 case X86::SUB16rr_REV: 243 case X86::SUB32i32: 244 case X86::SUB32ri: 245 case X86::SUB32ri8: 246 case X86::SUB32rm: 247 case X86::SUB32rr: 248 case X86::SUB32rr_REV: 249 case X86::SUB64i32: 250 case X86::SUB64ri32: 251 case X86::SUB64ri8: 252 case X86::SUB64rm: 253 case X86::SUB64rr: 254 case X86::SUB64rr_REV: 255 case X86::SUB8i8: 256 case X86::SUB8ri: 257 case X86::SUB8ri8: 258 case X86::SUB8rm: 259 case X86::SUB8rr: 260 case X86::SUB8rr_REV: 261 return FirstMacroFusionInstKind::AddSub; 262 // INC 263 case X86::INC16r: 264 case X86::INC16r_alt: 265 case X86::INC32r: 266 case X86::INC32r_alt: 267 case X86::INC64r: 268 case X86::INC8r: 269 // DEC 270 case X86::DEC16r: 271 case X86::DEC16r_alt: 272 case X86::DEC32r: 273 case X86::DEC32r_alt: 274 case X86::DEC64r: 275 case X86::DEC8r: 276 return FirstMacroFusionInstKind::IncDec; 277 } 278 } 279 280 /// \returns the type of the second instruction in macro-fusion. 281 inline SecondMacroFusionInstKind 282 classifySecondCondCodeInMacroFusion(X86::CondCode CC) { 283 if (CC == X86::COND_INVALID) 284 return SecondMacroFusionInstKind::Invalid; 285 286 switch (CC) { 287 default: 288 return SecondMacroFusionInstKind::Invalid; 289 // JE,JZ 290 case X86::COND_E: 291 // JNE,JNZ 292 case X86::COND_NE: 293 // JL,JNGE 294 case X86::COND_L: 295 // JLE,JNG 296 case X86::COND_LE: 297 // JG,JNLE 298 case X86::COND_G: 299 // JGE,JNL 300 case X86::COND_GE: 301 return SecondMacroFusionInstKind::ELG; 302 // JB,JC 303 case X86::COND_B: 304 // JNA,JBE 305 case X86::COND_BE: 306 // JA,JNBE 307 case X86::COND_A: 308 // JAE,JNC,JNB 309 case X86::COND_AE: 310 return SecondMacroFusionInstKind::AB; 311 // JS 312 case X86::COND_S: 313 // JNS 314 case X86::COND_NS: 315 // JP,JPE 316 case X86::COND_P: 317 // JNP,JPO 318 case X86::COND_NP: 319 // JO 320 case X86::COND_O: 321 // JNO 322 case X86::COND_NO: 323 return SecondMacroFusionInstKind::SPO; 324 } 325 } 326 327 /// \param FirstKind kind of the first instruction in macro fusion. 328 /// \param SecondKind kind of the second instruction in macro fusion. 329 /// 330 /// \returns true if the two instruction can be macro fused. 331 inline bool isMacroFused(FirstMacroFusionInstKind FirstKind, 332 SecondMacroFusionInstKind SecondKind) { 333 switch (FirstKind) { 334 case X86::FirstMacroFusionInstKind::Test: 335 case X86::FirstMacroFusionInstKind::And: 336 return true; 337 case X86::FirstMacroFusionInstKind::Cmp: 338 case X86::FirstMacroFusionInstKind::AddSub: 339 return SecondKind == X86::SecondMacroFusionInstKind::AB || 340 SecondKind == X86::SecondMacroFusionInstKind::ELG; 341 case X86::FirstMacroFusionInstKind::IncDec: 342 return SecondKind == X86::SecondMacroFusionInstKind::ELG; 343 case X86::FirstMacroFusionInstKind::Invalid: 344 return false; 345 } 346 llvm_unreachable("unknown fusion type"); 347 } 348 349 /// Defines the possible values of the branch boundary alignment mask. 350 enum AlignBranchBoundaryKind : uint8_t { 351 AlignBranchNone = 0, 352 AlignBranchFused = 1U << 0, 353 AlignBranchJcc = 1U << 1, 354 AlignBranchJmp = 1U << 2, 355 AlignBranchCall = 1U << 3, 356 AlignBranchRet = 1U << 4, 357 AlignBranchIndirect = 1U << 5 358 }; 359 360 /// Defines the encoding values for segment override prefix. 361 enum EncodingOfSegmentOverridePrefix : uint8_t { 362 CS_Encoding = 0x2E, 363 DS_Encoding = 0x3E, 364 ES_Encoding = 0x26, 365 FS_Encoding = 0x64, 366 GS_Encoding = 0x65, 367 SS_Encoding = 0x36 368 }; 369 370 /// Given a segment register, return the encoding of the segment override 371 /// prefix for it. 372 inline EncodingOfSegmentOverridePrefix 373 getSegmentOverridePrefixForReg(unsigned Reg) { 374 switch (Reg) { 375 default: 376 llvm_unreachable("Unknown segment register!"); 377 case X86::CS: 378 return CS_Encoding; 379 case X86::DS: 380 return DS_Encoding; 381 case X86::ES: 382 return ES_Encoding; 383 case X86::FS: 384 return FS_Encoding; 385 case X86::GS: 386 return GS_Encoding; 387 case X86::SS: 388 return SS_Encoding; 389 } 390 } 391 392} // end namespace X86; 393 394/// X86II - This namespace holds all of the target specific flags that 395/// instruction info tracks. 396/// 397namespace X86II { 398 /// Target Operand Flag enum. 399 enum TOF { 400 //===------------------------------------------------------------------===// 401 // X86 Specific MachineOperand flags. 402 403 MO_NO_FLAG, 404 405 /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a 406 /// relocation of: 407 /// SYMBOL_LABEL + [. - PICBASELABEL] 408 MO_GOT_ABSOLUTE_ADDRESS, 409 410 /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the 411 /// immediate should get the value of the symbol minus the PIC base label: 412 /// SYMBOL_LABEL - PICBASELABEL 413 MO_PIC_BASE_OFFSET, 414 415 /// MO_GOT - On a symbol operand this indicates that the immediate is the 416 /// offset to the GOT entry for the symbol name from the base of the GOT. 417 /// 418 /// See the X86-64 ELF ABI supplement for more details. 419 /// SYMBOL_LABEL @GOT 420 MO_GOT, 421 422 /// MO_GOTOFF - On a symbol operand this indicates that the immediate is 423 /// the offset to the location of the symbol name from the base of the GOT. 424 /// 425 /// See the X86-64 ELF ABI supplement for more details. 426 /// SYMBOL_LABEL @GOTOFF 427 MO_GOTOFF, 428 429 /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is 430 /// offset to the GOT entry for the symbol name from the current code 431 /// location. 432 /// 433 /// See the X86-64 ELF ABI supplement for more details. 434 /// SYMBOL_LABEL @GOTPCREL 435 MO_GOTPCREL, 436 437 /// MO_PLT - On a symbol operand this indicates that the immediate is 438 /// offset to the PLT entry of symbol name from the current code location. 439 /// 440 /// See the X86-64 ELF ABI supplement for more details. 441 /// SYMBOL_LABEL @PLT 442 MO_PLT, 443 444 /// MO_TLSGD - On a symbol operand this indicates that the immediate is 445 /// the offset of the GOT entry with the TLS index structure that contains 446 /// the module number and variable offset for the symbol. Used in the 447 /// general dynamic TLS access model. 448 /// 449 /// See 'ELF Handling for Thread-Local Storage' for more details. 450 /// SYMBOL_LABEL @TLSGD 451 MO_TLSGD, 452 453 /// MO_TLSLD - On a symbol operand this indicates that the immediate is 454 /// the offset of the GOT entry with the TLS index for the module that 455 /// contains the symbol. When this index is passed to a call to 456 /// __tls_get_addr, the function will return the base address of the TLS 457 /// block for the symbol. Used in the x86-64 local dynamic TLS access model. 458 /// 459 /// See 'ELF Handling for Thread-Local Storage' for more details. 460 /// SYMBOL_LABEL @TLSLD 461 MO_TLSLD, 462 463 /// MO_TLSLDM - On a symbol operand this indicates that the immediate is 464 /// the offset of the GOT entry with the TLS index for the module that 465 /// contains the symbol. When this index is passed to a call to 466 /// ___tls_get_addr, the function will return the base address of the TLS 467 /// block for the symbol. Used in the IA32 local dynamic TLS access model. 468 /// 469 /// See 'ELF Handling for Thread-Local Storage' for more details. 470 /// SYMBOL_LABEL @TLSLDM 471 MO_TLSLDM, 472 473 /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is 474 /// the offset of the GOT entry with the thread-pointer offset for the 475 /// symbol. Used in the x86-64 initial exec TLS access model. 476 /// 477 /// See 'ELF Handling for Thread-Local Storage' for more details. 478 /// SYMBOL_LABEL @GOTTPOFF 479 MO_GOTTPOFF, 480 481 /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is 482 /// the absolute address of the GOT entry with the negative thread-pointer 483 /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access 484 /// model. 485 /// 486 /// See 'ELF Handling for Thread-Local Storage' for more details. 487 /// SYMBOL_LABEL @INDNTPOFF 488 MO_INDNTPOFF, 489 490 /// MO_TPOFF - On a symbol operand this indicates that the immediate is 491 /// the thread-pointer offset for the symbol. Used in the x86-64 local 492 /// exec TLS access model. 493 /// 494 /// See 'ELF Handling for Thread-Local Storage' for more details. 495 /// SYMBOL_LABEL @TPOFF 496 MO_TPOFF, 497 498 /// MO_DTPOFF - On a symbol operand this indicates that the immediate is 499 /// the offset of the GOT entry with the TLS offset of the symbol. Used 500 /// in the local dynamic TLS access model. 501 /// 502 /// See 'ELF Handling for Thread-Local Storage' for more details. 503 /// SYMBOL_LABEL @DTPOFF 504 MO_DTPOFF, 505 506 /// MO_NTPOFF - On a symbol operand this indicates that the immediate is 507 /// the negative thread-pointer offset for the symbol. Used in the IA32 508 /// local exec TLS access model. 509 /// 510 /// See 'ELF Handling for Thread-Local Storage' for more details. 511 /// SYMBOL_LABEL @NTPOFF 512 MO_NTPOFF, 513 514 /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is 515 /// the offset of the GOT entry with the negative thread-pointer offset for 516 /// the symbol. Used in the PIC IA32 initial exec TLS access model. 517 /// 518 /// See 'ELF Handling for Thread-Local Storage' for more details. 519 /// SYMBOL_LABEL @GOTNTPOFF 520 MO_GOTNTPOFF, 521 522 /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the 523 /// reference is actually to the "__imp_FOO" symbol. This is used for 524 /// dllimport linkage on windows. 525 MO_DLLIMPORT, 526 527 /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the 528 /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a 529 /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 530 MO_DARWIN_NONLAZY, 531 532 /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates 533 /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is 534 /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub. 535 MO_DARWIN_NONLAZY_PIC_BASE, 536 537 /// MO_TLVP - On a symbol operand this indicates that the immediate is 538 /// some TLS offset. 539 /// 540 /// This is the TLS offset for the Darwin TLS mechanism. 541 MO_TLVP, 542 543 /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate 544 /// is some TLS offset from the picbase. 545 /// 546 /// This is the 32-bit TLS offset for Darwin TLS in PIC mode. 547 MO_TLVP_PIC_BASE, 548 549 /// MO_SECREL - On a symbol operand this indicates that the immediate is 550 /// the offset from beginning of section. 551 /// 552 /// This is the TLS offset for the COFF/Windows TLS mechanism. 553 MO_SECREL, 554 555 /// MO_ABS8 - On a symbol operand this indicates that the symbol is known 556 /// to be an absolute symbol in range [0,128), so we can use the @ABS8 557 /// symbol modifier. 558 MO_ABS8, 559 560 /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the 561 /// reference is actually to the ".refptr.FOO" symbol. This is used for 562 /// stub symbols on windows. 563 MO_COFFSTUB, 564 }; 565 566 enum : uint64_t { 567 //===------------------------------------------------------------------===// 568 // Instruction encodings. These are the standard/most common forms for X86 569 // instructions. 570 // 571 572 // PseudoFrm - This represents an instruction that is a pseudo instruction 573 // or one that has not been implemented yet. It is illegal to code generate 574 // it, but tolerated for intermediate implementation stages. 575 Pseudo = 0, 576 577 /// Raw - This form is for instructions that don't have any operands, so 578 /// they are just a fixed opcode value, like 'leave'. 579 RawFrm = 1, 580 581 /// AddRegFrm - This form is used for instructions like 'push r32' that have 582 /// their one register operand added to their opcode. 583 AddRegFrm = 2, 584 585 /// RawFrmMemOffs - This form is for instructions that store an absolute 586 /// memory offset as an immediate with a possible segment override. 587 RawFrmMemOffs = 3, 588 589 /// RawFrmSrc - This form is for instructions that use the source index 590 /// register SI/ESI/RSI with a possible segment override. 591 RawFrmSrc = 4, 592 593 /// RawFrmDst - This form is for instructions that use the destination index 594 /// register DI/EDI/RDI. 595 RawFrmDst = 5, 596 597 /// RawFrmDstSrc - This form is for instructions that use the source index 598 /// register SI/ESI/RSI with a possible segment override, and also the 599 /// destination index register DI/EDI/RDI. 600 RawFrmDstSrc = 6, 601 602 /// RawFrmImm8 - This is used for the ENTER instruction, which has two 603 /// immediates, the first of which is a 16-bit immediate (specified by 604 /// the imm encoding) and the second is a 8-bit fixed value. 605 RawFrmImm8 = 7, 606 607 /// RawFrmImm16 - This is used for CALL FAR instructions, which have two 608 /// immediates, the first of which is a 16 or 32-bit immediate (specified by 609 /// the imm encoding) and the second is a 16-bit fixed value. In the AMD 610 /// manual, this operand is described as pntr16:32 and pntr16:16 611 RawFrmImm16 = 8, 612 613 /// AddCCFrm - This form is used for Jcc that encode the condition code 614 /// in the lower 4 bits of the opcode. 615 AddCCFrm = 9, 616 617 /// PrefixByte - This form is used for instructions that represent a prefix 618 /// byte like data16 or rep. 619 PrefixByte = 10, 620 621 /// MRM[0-7][rm] - These forms are used to represent instructions that use 622 /// a Mod/RM byte, and use the middle field to hold extended opcode 623 /// information. In the intel manual these are represented as /0, /1, ... 624 /// 625 626 // Instructions operate on a register Reg/Opcode operand not the r/m field. 627 MRMr0 = 21, 628 629 /// MRMSrcMem - But force to use the SIB field. 630 MRMSrcMemFSIB = 22, 631 632 /// MRMDestMem - But force to use the SIB field. 633 MRMDestMemFSIB = 23, 634 635 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte 636 /// to specify a destination, which in this case is memory. 637 /// 638 MRMDestMem = 24, 639 640 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte 641 /// to specify a source, which in this case is memory. 642 /// 643 MRMSrcMem = 25, 644 645 /// MRMSrcMem4VOp3 - This form is used for instructions that encode 646 /// operand 3 with VEX.VVVV and load from memory. 647 /// 648 MRMSrcMem4VOp3 = 26, 649 650 /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM 651 /// byte to specify the fourth source, which in this case is memory. 652 /// 653 MRMSrcMemOp4 = 27, 654 655 /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM 656 /// byte to specify the operands and also encodes a condition code. 657 /// 658 MRMSrcMemCC = 28, 659 660 /// MRMXm - This form is used for instructions that use the Mod/RM byte 661 /// to specify a memory source, but doesn't use the middle field. And has 662 /// a condition code. 663 /// 664 MRMXmCC = 30, 665 666 /// MRMXm - This form is used for instructions that use the Mod/RM byte 667 /// to specify a memory source, but doesn't use the middle field. 668 /// 669 MRMXm = 31, 670 671 // Next, instructions that operate on a memory r/m operand... 672 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, // Format /0 /1 /2 /3 673 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, // Format /4 /5 /6 /7 674 675 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte 676 /// to specify a destination, which in this case is a register. 677 /// 678 MRMDestReg = 40, 679 680 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte 681 /// to specify a source, which in this case is a register. 682 /// 683 MRMSrcReg = 41, 684 685 /// MRMSrcReg4VOp3 - This form is used for instructions that encode 686 /// operand 3 with VEX.VVVV and do not load from memory. 687 /// 688 MRMSrcReg4VOp3 = 42, 689 690 /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM 691 /// byte to specify the fourth source, which in this case is a register. 692 /// 693 MRMSrcRegOp4 = 43, 694 695 /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM 696 /// byte to specify the operands and also encodes a condition code 697 /// 698 MRMSrcRegCC = 44, 699 700 /// MRMXCCr - This form is used for instructions that use the Mod/RM byte 701 /// to specify a register source, but doesn't use the middle field. And has 702 /// a condition code. 703 /// 704 MRMXrCC = 46, 705 706 /// MRMXr - This form is used for instructions that use the Mod/RM byte 707 /// to specify a register source, but doesn't use the middle field. 708 /// 709 MRMXr = 47, 710 711 // Instructions that operate on a register r/m operand... 712 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, // Format /0 /1 /2 /3 713 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, // Format /4 /5 /6 /7 714 715 // Instructions that operate that have mod=11 and an opcode but ignore r/m. 716 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, // Format /0 /1 /2 /3 717 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, // Format /4 /5 /6 /7 718 719 /// MRM_XX - A mod/rm byte of exactly 0xXX. 720 MRM_C0 = 64, MRM_C1 = 65, MRM_C2 = 66, MRM_C3 = 67, 721 MRM_C4 = 68, MRM_C5 = 69, MRM_C6 = 70, MRM_C7 = 71, 722 MRM_C8 = 72, MRM_C9 = 73, MRM_CA = 74, MRM_CB = 75, 723 MRM_CC = 76, MRM_CD = 77, MRM_CE = 78, MRM_CF = 79, 724 MRM_D0 = 80, MRM_D1 = 81, MRM_D2 = 82, MRM_D3 = 83, 725 MRM_D4 = 84, MRM_D5 = 85, MRM_D6 = 86, MRM_D7 = 87, 726 MRM_D8 = 88, MRM_D9 = 89, MRM_DA = 90, MRM_DB = 91, 727 MRM_DC = 92, MRM_DD = 93, MRM_DE = 94, MRM_DF = 95, 728 MRM_E0 = 96, MRM_E1 = 97, MRM_E2 = 98, MRM_E3 = 99, 729 MRM_E4 = 100, MRM_E5 = 101, MRM_E6 = 102, MRM_E7 = 103, 730 MRM_E8 = 104, MRM_E9 = 105, MRM_EA = 106, MRM_EB = 107, 731 MRM_EC = 108, MRM_ED = 109, MRM_EE = 110, MRM_EF = 111, 732 MRM_F0 = 112, MRM_F1 = 113, MRM_F2 = 114, MRM_F3 = 115, 733 MRM_F4 = 116, MRM_F5 = 117, MRM_F6 = 118, MRM_F7 = 119, 734 MRM_F8 = 120, MRM_F9 = 121, MRM_FA = 122, MRM_FB = 123, 735 MRM_FC = 124, MRM_FD = 125, MRM_FE = 126, MRM_FF = 127, 736 737 FormMask = 127, 738 739 //===------------------------------------------------------------------===// 740 // Actual flags... 741 742 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix. 743 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in 744 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66 745 // prefix in 16-bit mode. 746 OpSizeShift = 7, 747 OpSizeMask = 0x3 << OpSizeShift, 748 749 OpSizeFixed = 0 << OpSizeShift, 750 OpSize16 = 1 << OpSizeShift, 751 OpSize32 = 2 << OpSizeShift, 752 753 // AsSize - AdSizeX implies this instruction determines its need of 0x67 754 // prefix from a normal ModRM memory operand. The other types indicate that 755 // an operand is encoded with a specific width and a prefix is needed if 756 // it differs from the current mode. 757 AdSizeShift = OpSizeShift + 2, 758 AdSizeMask = 0x3 << AdSizeShift, 759 760 AdSizeX = 0 << AdSizeShift, 761 AdSize16 = 1 << AdSizeShift, 762 AdSize32 = 2 << AdSizeShift, 763 AdSize64 = 3 << AdSizeShift, 764 765 //===------------------------------------------------------------------===// 766 // OpPrefix - There are several prefix bytes that are used as opcode 767 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is 768 // no prefix. 769 // 770 OpPrefixShift = AdSizeShift + 2, 771 OpPrefixMask = 0x3 << OpPrefixShift, 772 773 // PD - Prefix code for packed double precision vector floating point 774 // operations performed in the SSE registers. 775 PD = 1 << OpPrefixShift, 776 777 // XS, XD - These prefix codes are for single and double precision scalar 778 // floating point operations performed in the SSE registers. 779 XS = 2 << OpPrefixShift, XD = 3 << OpPrefixShift, 780 781 //===------------------------------------------------------------------===// 782 // OpMap - This field determines which opcode map this instruction 783 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc. 784 // 785 OpMapShift = OpPrefixShift + 2, 786 OpMapMask = 0x7 << OpMapShift, 787 788 // OB - OneByte - Set if this instruction has a one byte opcode. 789 OB = 0 << OpMapShift, 790 791 // TB - TwoByte - Set if this instruction has a two byte opcode, which 792 // starts with a 0x0F byte before the real opcode. 793 TB = 1 << OpMapShift, 794 795 // T8, TA - Prefix after the 0x0F prefix. 796 T8 = 2 << OpMapShift, TA = 3 << OpMapShift, 797 798 // XOP8 - Prefix to include use of imm byte. 799 XOP8 = 4 << OpMapShift, 800 801 // XOP9 - Prefix to exclude use of imm byte. 802 XOP9 = 5 << OpMapShift, 803 804 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions. 805 XOPA = 6 << OpMapShift, 806 807 /// ThreeDNow - This indicates that the instruction uses the 808 /// wacky 0x0F 0x0F prefix for 3DNow! instructions. The manual documents 809 /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction 810 /// storing a classifier in the imm8 field. To simplify our implementation, 811 /// we handle this by storeing the classifier in the opcode field and using 812 /// this flag to indicate that the encoder should do the wacky 3DNow! thing. 813 ThreeDNow = 7 << OpMapShift, 814 815 //===------------------------------------------------------------------===// 816 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode. 817 // They are used to specify GPRs and SSE registers, 64-bit operand size, 818 // etc. We only cares about REX.W and REX.R bits and only the former is 819 // statically determined. 820 // 821 REXShift = OpMapShift + 3, 822 REX_W = 1 << REXShift, 823 824 //===------------------------------------------------------------------===// 825 // This three-bit field describes the size of an immediate operand. Zero is 826 // unused so that we can tell if we forgot to set a value. 827 ImmShift = REXShift + 1, 828 ImmMask = 15 << ImmShift, 829 Imm8 = 1 << ImmShift, 830 Imm8PCRel = 2 << ImmShift, 831 Imm8Reg = 3 << ImmShift, 832 Imm16 = 4 << ImmShift, 833 Imm16PCRel = 5 << ImmShift, 834 Imm32 = 6 << ImmShift, 835 Imm32PCRel = 7 << ImmShift, 836 Imm32S = 8 << ImmShift, 837 Imm64 = 9 << ImmShift, 838 839 //===------------------------------------------------------------------===// 840 // FP Instruction Classification... Zero is non-fp instruction. 841 842 // FPTypeMask - Mask for all of the FP types... 843 FPTypeShift = ImmShift + 4, 844 FPTypeMask = 7 << FPTypeShift, 845 846 // NotFP - The default, set for instructions that do not use FP registers. 847 NotFP = 0 << FPTypeShift, 848 849 // ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0 850 ZeroArgFP = 1 << FPTypeShift, 851 852 // OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst 853 OneArgFP = 2 << FPTypeShift, 854 855 // OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a 856 // result back to ST(0). For example, fcos, fsqrt, etc. 857 // 858 OneArgFPRW = 3 << FPTypeShift, 859 860 // TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an 861 // explicit argument, storing the result to either ST(0) or the implicit 862 // argument. For example: fadd, fsub, fmul, etc... 863 TwoArgFP = 4 << FPTypeShift, 864 865 // CompareFP - 2 arg FP instructions which implicitly read ST(0) and an 866 // explicit argument, but have no destination. Example: fucom, fucomi, ... 867 CompareFP = 5 << FPTypeShift, 868 869 // CondMovFP - "2 operand" floating point conditional move instructions. 870 CondMovFP = 6 << FPTypeShift, 871 872 // SpecialFP - Special instruction forms. Dispatch by opcode explicitly. 873 SpecialFP = 7 << FPTypeShift, 874 875 // Lock prefix 876 LOCKShift = FPTypeShift + 3, 877 LOCK = 1 << LOCKShift, 878 879 // REP prefix 880 REPShift = LOCKShift + 1, 881 REP = 1 << REPShift, 882 883 // Execution domain for SSE instructions. 884 // 0 means normal, non-SSE instruction. 885 SSEDomainShift = REPShift + 1, 886 887 // Encoding 888 EncodingShift = SSEDomainShift + 2, 889 EncodingMask = 0x3 << EncodingShift, 890 891 // VEX - encoding using 0xC4/0xC5 892 VEX = 1 << EncodingShift, 893 894 /// XOP - Opcode prefix used by XOP instructions. 895 XOP = 2 << EncodingShift, 896 897 // VEX_EVEX - Specifies that this instruction use EVEX form which provides 898 // syntax support up to 32 512-bit register operands and up to 7 16-bit 899 // mask operands as well as source operand data swizzling/memory operand 900 // conversion, eviction hint, and rounding mode. 901 EVEX = 3 << EncodingShift, 902 903 // Opcode 904 OpcodeShift = EncodingShift + 2, 905 906 /// VEX_W - Has a opcode specific functionality, but is used in the same 907 /// way as REX_W is for regular SSE instructions. 908 VEX_WShift = OpcodeShift + 8, 909 VEX_W = 1ULL << VEX_WShift, 910 911 /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2 912 /// address instructions in SSE are represented as 3 address ones in AVX 913 /// and the additional register is encoded in VEX_VVVV prefix. 914 VEX_4VShift = VEX_WShift + 1, 915 VEX_4V = 1ULL << VEX_4VShift, 916 917 /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current 918 /// instruction uses 256-bit wide registers. This is usually auto detected 919 /// if a VR256 register is used, but some AVX instructions also have this 920 /// field marked when using a f256 memory references. 921 VEX_LShift = VEX_4VShift + 1, 922 VEX_L = 1ULL << VEX_LShift, 923 924 // EVEX_K - Set if this instruction requires masking 925 EVEX_KShift = VEX_LShift + 1, 926 EVEX_K = 1ULL << EVEX_KShift, 927 928 // EVEX_Z - Set if this instruction has EVEX.Z field set. 929 EVEX_ZShift = EVEX_KShift + 1, 930 EVEX_Z = 1ULL << EVEX_ZShift, 931 932 // EVEX_L2 - Set if this instruction has EVEX.L' field set. 933 EVEX_L2Shift = EVEX_ZShift + 1, 934 EVEX_L2 = 1ULL << EVEX_L2Shift, 935 936 // EVEX_B - Set if this instruction has EVEX.B field set. 937 EVEX_BShift = EVEX_L2Shift + 1, 938 EVEX_B = 1ULL << EVEX_BShift, 939 940 // The scaling factor for the AVX512's 8-bit compressed displacement. 941 CD8_Scale_Shift = EVEX_BShift + 1, 942 CD8_Scale_Mask = 127ULL << CD8_Scale_Shift, 943 944 /// Explicitly specified rounding control 945 EVEX_RCShift = CD8_Scale_Shift + 7, 946 EVEX_RC = 1ULL << EVEX_RCShift, 947 948 // NOTRACK prefix 949 NoTrackShift = EVEX_RCShift + 1, 950 NOTRACK = 1ULL << NoTrackShift 951 }; 952 953 /// \returns true if the instruction with given opcode is a prefix. 954 inline bool isPrefix(uint64_t TSFlags) { 955 return (TSFlags & X86II::FormMask) == PrefixByte; 956 } 957 958 /// \returns true if the instruction with given opcode is a pseudo. 959 inline bool isPseudo(uint64_t TSFlags) { 960 return (TSFlags & X86II::FormMask) == Pseudo; 961 } 962 963 /// \returns the "base" X86 opcode for the specified machine 964 /// instruction. 965 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) { 966 return TSFlags >> X86II::OpcodeShift; 967 } 968 969 inline bool hasImm(uint64_t TSFlags) { 970 return (TSFlags & X86II::ImmMask) != 0; 971 } 972 973 /// Decode the "size of immediate" field from the TSFlags field of the 974 /// specified instruction. 975 inline unsigned getSizeOfImm(uint64_t TSFlags) { 976 switch (TSFlags & X86II::ImmMask) { 977 default: llvm_unreachable("Unknown immediate size"); 978 case X86II::Imm8: 979 case X86II::Imm8PCRel: 980 case X86II::Imm8Reg: return 1; 981 case X86II::Imm16: 982 case X86II::Imm16PCRel: return 2; 983 case X86II::Imm32: 984 case X86II::Imm32S: 985 case X86II::Imm32PCRel: return 4; 986 case X86II::Imm64: return 8; 987 } 988 } 989 990 /// \returns true if the immediate of the specified instruction's TSFlags 991 /// indicates that it is pc relative. 992 inline bool isImmPCRel(uint64_t TSFlags) { 993 switch (TSFlags & X86II::ImmMask) { 994 default: llvm_unreachable("Unknown immediate size"); 995 case X86II::Imm8PCRel: 996 case X86II::Imm16PCRel: 997 case X86II::Imm32PCRel: 998 return true; 999 case X86II::Imm8: 1000 case X86II::Imm8Reg: 1001 case X86II::Imm16: 1002 case X86II::Imm32: 1003 case X86II::Imm32S: 1004 case X86II::Imm64: 1005 return false; 1006 } 1007 } 1008 1009 /// \returns true if the immediate of the specified instruction's 1010 /// TSFlags indicates that it is signed. 1011 inline bool isImmSigned(uint64_t TSFlags) { 1012 switch (TSFlags & X86II::ImmMask) { 1013 default: llvm_unreachable("Unknown immediate signedness"); 1014 case X86II::Imm32S: 1015 return true; 1016 case X86II::Imm8: 1017 case X86II::Imm8PCRel: 1018 case X86II::Imm8Reg: 1019 case X86II::Imm16: 1020 case X86II::Imm16PCRel: 1021 case X86II::Imm32: 1022 case X86II::Imm32PCRel: 1023 case X86II::Imm64: 1024 return false; 1025 } 1026 } 1027 1028 /// Compute whether all of the def operands are repeated in the uses and 1029 /// therefore should be skipped. 1030 /// This determines the start of the unique operand list. We need to determine 1031 /// if all of the defs have a corresponding tied operand in the uses. 1032 /// Unfortunately, the tied operand information is encoded in the uses not 1033 /// the defs so we have to use some heuristics to find which operands to 1034 /// query. 1035 inline unsigned getOperandBias(const MCInstrDesc& Desc) { 1036 unsigned NumDefs = Desc.getNumDefs(); 1037 unsigned NumOps = Desc.getNumOperands(); 1038 switch (NumDefs) { 1039 default: llvm_unreachable("Unexpected number of defs"); 1040 case 0: 1041 return 0; 1042 case 1: 1043 // Common two addr case. 1044 if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0) 1045 return 1; 1046 // Check for AVX-512 scatter which has a TIED_TO in the second to last 1047 // operand. 1048 if (NumOps == 8 && 1049 Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0) 1050 return 1; 1051 return 0; 1052 case 2: 1053 // XCHG/XADD have two destinations and two sources. 1054 if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 1055 Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1) 1056 return 2; 1057 // Check for gather. AVX-512 has the second tied operand early. AVX2 1058 // has it as the last op. 1059 if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 && 1060 (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 || 1061 Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1)) 1062 return 2; 1063 return 0; 1064 } 1065 } 1066 1067 /// The function returns the MCInst operand # for the first field of the 1068 /// memory operand. If the instruction doesn't have a 1069 /// memory operand, this returns -1. 1070 /// 1071 /// Note that this ignores tied operands. If there is a tied register which 1072 /// is duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only 1073 /// counted as one operand. 1074 /// 1075 inline int getMemoryOperandNo(uint64_t TSFlags) { 1076 bool HasVEX_4V = TSFlags & X86II::VEX_4V; 1077 bool HasEVEX_K = TSFlags & X86II::EVEX_K; 1078 1079 switch (TSFlags & X86II::FormMask) { 1080 default: llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!"); 1081 case X86II::Pseudo: 1082 case X86II::RawFrm: 1083 case X86II::AddRegFrm: 1084 case X86II::RawFrmImm8: 1085 case X86II::RawFrmImm16: 1086 case X86II::RawFrmMemOffs: 1087 case X86II::RawFrmSrc: 1088 case X86II::RawFrmDst: 1089 case X86II::RawFrmDstSrc: 1090 case X86II::AddCCFrm: 1091 case X86II::PrefixByte: 1092 return -1; 1093 case X86II::MRMDestMem: 1094 case X86II::MRMDestMemFSIB: 1095 return 0; 1096 case X86II::MRMSrcMem: 1097 case X86II::MRMSrcMemFSIB: 1098 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 1099 // mask register. 1100 return 1 + HasVEX_4V + HasEVEX_K; 1101 case X86II::MRMSrcMem4VOp3: 1102 // Skip registers encoded in reg. 1103 return 1 + HasEVEX_K; 1104 case X86II::MRMSrcMemOp4: 1105 // Skip registers encoded in reg, VEX_VVVV, and I8IMM. 1106 return 3; 1107 case X86II::MRMSrcMemCC: 1108 // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a 1109 // mask register. 1110 return 1; 1111 case X86II::MRMDestReg: 1112 case X86II::MRMSrcReg: 1113 case X86II::MRMSrcReg4VOp3: 1114 case X86II::MRMSrcRegOp4: 1115 case X86II::MRMSrcRegCC: 1116 case X86II::MRMXrCC: 1117 case X86II::MRMr0: 1118 case X86II::MRMXr: 1119 case X86II::MRM0r: case X86II::MRM1r: 1120 case X86II::MRM2r: case X86II::MRM3r: 1121 case X86II::MRM4r: case X86II::MRM5r: 1122 case X86II::MRM6r: case X86II::MRM7r: 1123 return -1; 1124 case X86II::MRM0X: case X86II::MRM1X: 1125 case X86II::MRM2X: case X86II::MRM3X: 1126 case X86II::MRM4X: case X86II::MRM5X: 1127 case X86II::MRM6X: case X86II::MRM7X: 1128 return -1; 1129 case X86II::MRMXmCC: 1130 case X86II::MRMXm: 1131 case X86II::MRM0m: case X86II::MRM1m: 1132 case X86II::MRM2m: case X86II::MRM3m: 1133 case X86II::MRM4m: case X86II::MRM5m: 1134 case X86II::MRM6m: case X86II::MRM7m: 1135 // Start from 0, skip registers encoded in VEX_VVVV or a mask register. 1136 return 0 + HasVEX_4V + HasEVEX_K; 1137 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2: 1138 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C5: 1139 case X86II::MRM_C6: case X86II::MRM_C7: case X86II::MRM_C8: 1140 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB: 1141 case X86II::MRM_CC: case X86II::MRM_CD: case X86II::MRM_CE: 1142 case X86II::MRM_CF: case X86II::MRM_D0: case X86II::MRM_D1: 1143 case X86II::MRM_D2: case X86II::MRM_D3: case X86II::MRM_D4: 1144 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D7: 1145 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA: 1146 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD: 1147 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0: 1148 case X86II::MRM_E1: case X86II::MRM_E2: case X86II::MRM_E3: 1149 case X86II::MRM_E4: case X86II::MRM_E5: case X86II::MRM_E6: 1150 case X86II::MRM_E7: case X86II::MRM_E8: case X86II::MRM_E9: 1151 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC: 1152 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_EF: 1153 case X86II::MRM_F0: case X86II::MRM_F1: case X86II::MRM_F2: 1154 case X86II::MRM_F3: case X86II::MRM_F4: case X86II::MRM_F5: 1155 case X86II::MRM_F6: case X86II::MRM_F7: case X86II::MRM_F8: 1156 case X86II::MRM_F9: case X86II::MRM_FA: case X86II::MRM_FB: 1157 case X86II::MRM_FC: case X86II::MRM_FD: case X86II::MRM_FE: 1158 case X86II::MRM_FF: 1159 return -1; 1160 } 1161 } 1162 1163 /// \returns true if the MachineOperand is a x86-64 extended (r8 or 1164 /// higher) register, e.g. r8, xmm8, xmm13, etc. 1165 inline bool isX86_64ExtendedReg(unsigned RegNo) { 1166 if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || 1167 (RegNo >= X86::YMM8 && RegNo <= X86::YMM31) || 1168 (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31)) 1169 return true; 1170 1171 switch (RegNo) { 1172 default: break; 1173 case X86::R8: case X86::R9: case X86::R10: case X86::R11: 1174 case X86::R12: case X86::R13: case X86::R14: case X86::R15: 1175 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: 1176 case X86::R12D: case X86::R13D: case X86::R14D: case X86::R15D: 1177 case X86::R8W: case X86::R9W: case X86::R10W: case X86::R11W: 1178 case X86::R12W: case X86::R13W: case X86::R14W: case X86::R15W: 1179 case X86::R8B: case X86::R9B: case X86::R10B: case X86::R11B: 1180 case X86::R12B: case X86::R13B: case X86::R14B: case X86::R15B: 1181 case X86::CR8: case X86::CR9: case X86::CR10: case X86::CR11: 1182 case X86::CR12: case X86::CR13: case X86::CR14: case X86::CR15: 1183 case X86::DR8: case X86::DR9: case X86::DR10: case X86::DR11: 1184 case X86::DR12: case X86::DR13: case X86::DR14: case X86::DR15: 1185 return true; 1186 } 1187 return false; 1188 } 1189 1190 /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher) 1191 /// registers, e.g. zmm21, etc. 1192 static inline bool is32ExtendedReg(unsigned RegNo) { 1193 return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) || 1194 (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) || 1195 (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31)); 1196 } 1197 1198 1199 inline bool isX86_64NonExtLowByteReg(unsigned reg) { 1200 return (reg == X86::SPL || reg == X86::BPL || 1201 reg == X86::SIL || reg == X86::DIL); 1202 } 1203 1204 /// \returns true if this is a masked instruction. 1205 inline bool isKMasked(uint64_t TSFlags) { 1206 return (TSFlags & X86II::EVEX_K) != 0; 1207 } 1208 1209 /// \returns true if this is a merge masked instruction. 1210 inline bool isKMergeMasked(uint64_t TSFlags) { 1211 return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0; 1212 } 1213} 1214 1215} // end namespace llvm; 1216 1217#endif 1218