1//===-- VERegisterInfo.td - VE Register defs ---------------*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the VE register file 11//===----------------------------------------------------------------------===// 12 13class VEReg<bits<7> enc, string n, list<Register> subregs = [], 14 list<string> altNames = [], list<Register> aliases = []> 15 : Register<n, altNames> { 16 let HWEncoding{15-7} = 0; 17 let HWEncoding{6-0} = enc; 18 let Namespace = "VE"; 19 let SubRegs = subregs; 20 let Aliases = aliases; 21} 22 23class VEMiscReg<bits<6> enc, string n>: Register<n> { 24 let HWEncoding{15-6} = 0; 25 let HWEncoding{5-0} = enc; 26 let Namespace = "VE"; 27} 28 29let Namespace = "VE" in { 30 def sub_i8 : SubRegIndex<8, 56>; // Low 8 bit (56..63) 31 def sub_i16 : SubRegIndex<16, 48>; // Low 16 bit (48..63) 32 def sub_i32 : SubRegIndex<32, 32>; // Low 32 bit (32..63) 33 def sub_f32 : SubRegIndex<32>; // High 32 bit (0..31) 34 def sub_even : SubRegIndex<64>; // High 64 bit (0..63) 35 def sub_odd : SubRegIndex<64, 64>; // Low 64 bit (64..127) 36 def AsmName : RegAltNameIndex; 37} 38 39//----------------------------------------------------------------------------- 40// Miscellaneous Registers 41//----------------------------------------------------------------------------- 42 43def USRCC : VEMiscReg<0, "usrcc">; // User clock counter 44def PSW : VEMiscReg<1, "psw">; // Program status word 45def SAR : VEMiscReg<2, "sar">; // Store address register 46def PMMR : VEMiscReg<7, "pmmr">; // Performance monitor mode register 47 48// Performance monitor configuration registers 49foreach I = 0-3 in 50 def PMCR#I : VEMiscReg<!add(8,I), "pmcr"#I>; 51 52// Performance monitor counter 53foreach I = 0-14 in 54 def PMC#I : VEMiscReg<!add(16,I), "pmc"#I>; 55 56// Register classes. 57def MISC : RegisterClass<"VE", [i64], 64, 58 (add USRCC, PSW, SAR, PMMR, 59 (sequence "PMCR%u", 0, 3), 60 (sequence "PMC%u", 0, 14))>; 61 62//----------------------------------------------------------------------------- 63// Instruction Counter Register 64//----------------------------------------------------------------------------- 65 66def IC : VEMiscReg<62, "ic">; 67 68//----------------------------------------------------------------------------- 69// Gneric Registers 70//----------------------------------------------------------------------------- 71 72let RegAltNameIndices = [AsmName] in { 73 74// Generic integer registers - 8 bits wide 75foreach I = 0-63 in 76 def SB#I : VEReg<I, "sb"#I, [], ["s"#I]>, DwarfRegNum<[I]>; 77 78// Generic integer registers - 16 bits wide 79let SubRegIndices = [sub_i8] in 80foreach I = 0-63 in 81 def SH#I : VEReg<I, "sh"#I, [!cast<VEReg>("SB"#I)], ["s"#I]>, 82 DwarfRegNum<[I]>; 83 84// Generic integer registers - 32 bits wide 85let SubRegIndices = [sub_i16] in 86foreach I = 0-63 in 87 def SW#I : VEReg<I, "sw"#I, [!cast<VEReg>("SH"#I)], ["s"#I]>, 88 DwarfRegNum<[I]>; 89 90// Generic floating point registers - 32 bits wide 91// NOTE: Mark SF#I as alias of SW#I temporary to avoid register allocation 92// problem. 93foreach I = 0-63 in 94 def SF#I : VEReg<I, "sf"#I, [], ["s"#I], [!cast<VEReg>("SW"#I)]>, 95 DwarfRegNum<[I]>; 96 97// Generic integer registers - 64 bits wide 98let SubRegIndices = [sub_i32, sub_f32], CoveredBySubRegs = 1 in 99foreach I = 0-63 in 100 def SX#I : VEReg<I, "s"#I, [!cast<VEReg>("SW"#I), !cast<VEReg>("SF"#I)], 101 ["s"#I]>, DwarfRegNum<[I]>; 102 103// Aliases of the S* registers used to hold 128-bit for values (long doubles). 104// Following foreach represents something like: 105// def Q0 : VEReg<0, "q0", [SX0, SX1], ["s0"]>; 106// def Q1 : VEReg<2, "q2", [SX2, SX3], ["s2"]>; 107// ... 108let SubRegIndices = [sub_even, sub_odd], CoveredBySubRegs = 1 in 109foreach I = 0-31 in 110 def Q#I : VEReg<!shl(I,1), "q"#I, 111 [!cast<VEReg>("SX"#!shl(I,1)), 112 !cast<VEReg>("SX"#!add(!shl(I,1),1))], 113 ["s"#!shl(I,1)]>; 114 115} // RegAltNameIndices = [AsmName] 116 117// Register classes. 118// 119// The register order is defined in terms of the preferred 120// allocation order. 121def I8 : RegisterClass<"VE", [i8], 8, 122 (add (sequence "SB%u", 0, 7), 123 (sequence "SB%u", 34, 63), 124 (sequence "SB%u", 8, 33))>; 125def I16 : RegisterClass<"VE", [i16], 16, 126 (add (sequence "SH%u", 0, 7), 127 (sequence "SH%u", 34, 63), 128 (sequence "SH%u", 8, 33))>; 129def I32 : RegisterClass<"VE", [i32], 32, 130 (add (sequence "SW%u", 0, 7), 131 (sequence "SW%u", 34, 63), 132 (sequence "SW%u", 8, 33))>; 133def I64 : RegisterClass<"VE", [i64, f64], 64, 134 (add (sequence "SX%u", 0, 7), 135 (sequence "SX%u", 34, 63), 136 (sequence "SX%u", 8, 33))>; 137def F32 : RegisterClass<"VE", [f32], 32, 138 (add (sequence "SF%u", 0, 7), 139 (sequence "SF%u", 34, 63), 140 (sequence "SF%u", 8, 33))>; 141def F128 : RegisterClass<"VE", [f128], 128, 142 (add (sequence "Q%u", 0, 3), 143 (sequence "Q%u", 17, 31), 144 (sequence "Q%u", 4, 16))>; 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