1//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file contains small standalone enum definitions for the RISCV target 10// useful for the compiler back-end and the MC libraries. 11// 12//===----------------------------------------------------------------------===// 13#ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H 14#define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H 15 16#include "RISCVRegisterInfo.h" 17#include "MCTargetDesc/RISCVMCTargetDesc.h" 18#include "llvm/ADT/StringRef.h" 19#include "llvm/ADT/StringSwitch.h" 20#include "llvm/MC/MCInstrDesc.h" 21#include "llvm/MC/SubtargetFeature.h" 22 23namespace llvm { 24 25// RISCVII - This namespace holds all of the target specific flags that 26// instruction info tracks. All definitions must match RISCVInstrFormats.td. 27namespace RISCVII { 28enum { 29 InstFormatPseudo = 0, 30 InstFormatR = 1, 31 InstFormatR4 = 2, 32 InstFormatI = 3, 33 InstFormatS = 4, 34 InstFormatB = 5, 35 InstFormatU = 6, 36 InstFormatJ = 7, 37 InstFormatCR = 8, 38 InstFormatCI = 9, 39 InstFormatCSS = 10, 40 InstFormatCIW = 11, 41 InstFormatCL = 12, 42 InstFormatCS = 13, 43 InstFormatCA = 14, 44 InstFormatCB = 15, 45 InstFormatCJ = 16, 46 InstFormatOther = 17, 47 48 InstFormatMask = 31, 49}; 50 51// RISC-V Specific Machine Operand Flags 52enum { 53 MO_None = 0, 54 MO_CALL = 1, 55 MO_PLT = 2, 56 MO_LO = 3, 57 MO_HI = 4, 58 MO_PCREL_LO = 5, 59 MO_PCREL_HI = 6, 60 MO_GOT_HI = 7, 61 MO_TPREL_LO = 8, 62 MO_TPREL_HI = 9, 63 MO_TPREL_ADD = 10, 64 MO_TLS_GOT_HI = 11, 65 MO_TLS_GD_HI = 12, 66 67 // Used to differentiate between target-specific "direct" flags and "bitmask" 68 // flags. A machine operand can only have one "direct" flag, but can have 69 // multiple "bitmask" flags. 70 MO_DIRECT_FLAG_MASK = 15 71}; 72} // namespace RISCVII 73 74namespace RISCVOp { 75enum OperandType : unsigned { 76 OPERAND_FIRST_RISCV_IMM = MCOI::OPERAND_FIRST_TARGET, 77 OPERAND_UIMM4 = OPERAND_FIRST_RISCV_IMM, 78 OPERAND_UIMM5, 79 OPERAND_UIMM12, 80 OPERAND_SIMM12, 81 OPERAND_SIMM13_LSB0, 82 OPERAND_UIMM20, 83 OPERAND_SIMM21_LSB0, 84 OPERAND_UIMMLOG2XLEN, 85 OPERAND_LAST_RISCV_IMM = OPERAND_UIMMLOG2XLEN 86}; 87} // namespace RISCVOp 88 89// Describes the predecessor/successor bits used in the FENCE instruction. 90namespace RISCVFenceField { 91enum FenceField { 92 I = 8, 93 O = 4, 94 R = 2, 95 W = 1 96}; 97} 98 99// Describes the supported floating point rounding mode encodings. 100namespace RISCVFPRndMode { 101enum RoundingMode { 102 RNE = 0, 103 RTZ = 1, 104 RDN = 2, 105 RUP = 3, 106 RMM = 4, 107 DYN = 7, 108 Invalid 109}; 110 111inline static StringRef roundingModeToString(RoundingMode RndMode) { 112 switch (RndMode) { 113 default: 114 llvm_unreachable("Unknown floating point rounding mode"); 115 case RISCVFPRndMode::RNE: 116 return "rne"; 117 case RISCVFPRndMode::RTZ: 118 return "rtz"; 119 case RISCVFPRndMode::RDN: 120 return "rdn"; 121 case RISCVFPRndMode::RUP: 122 return "rup"; 123 case RISCVFPRndMode::RMM: 124 return "rmm"; 125 case RISCVFPRndMode::DYN: 126 return "dyn"; 127 } 128} 129 130inline static RoundingMode stringToRoundingMode(StringRef Str) { 131 return StringSwitch<RoundingMode>(Str) 132 .Case("rne", RISCVFPRndMode::RNE) 133 .Case("rtz", RISCVFPRndMode::RTZ) 134 .Case("rdn", RISCVFPRndMode::RDN) 135 .Case("rup", RISCVFPRndMode::RUP) 136 .Case("rmm", RISCVFPRndMode::RMM) 137 .Case("dyn", RISCVFPRndMode::DYN) 138 .Default(RISCVFPRndMode::Invalid); 139} 140 141inline static bool isValidRoundingMode(unsigned Mode) { 142 switch (Mode) { 143 default: 144 return false; 145 case RISCVFPRndMode::RNE: 146 case RISCVFPRndMode::RTZ: 147 case RISCVFPRndMode::RDN: 148 case RISCVFPRndMode::RUP: 149 case RISCVFPRndMode::RMM: 150 case RISCVFPRndMode::DYN: 151 return true; 152 } 153} 154} // namespace RISCVFPRndMode 155 156namespace RISCVSysReg { 157struct SysReg { 158 const char *Name; 159 unsigned Encoding; 160 const char *AltName; 161 // FIXME: add these additional fields when needed. 162 // Privilege Access: Read, Write, Read-Only. 163 // unsigned ReadWrite; 164 // Privilege Mode: User, System or Machine. 165 // unsigned Mode; 166 // Check field name. 167 // unsigned Extra; 168 // Register number without the privilege bits. 169 // unsigned Number; 170 FeatureBitset FeaturesRequired; 171 bool isRV32Only; 172 173 bool haveRequiredFeatures(FeatureBitset ActiveFeatures) const { 174 // Not in 32-bit mode. 175 if (isRV32Only && ActiveFeatures[RISCV::Feature64Bit]) 176 return false; 177 // No required feature associated with the system register. 178 if (FeaturesRequired.none()) 179 return true; 180 return (FeaturesRequired & ActiveFeatures) == FeaturesRequired; 181 } 182}; 183 184#define GET_SysRegsList_DECL 185#include "RISCVGenSystemOperands.inc" 186} // end namespace RISCVSysReg 187 188namespace RISCVABI { 189 190enum ABI { 191 ABI_ILP32, 192 ABI_ILP32F, 193 ABI_ILP32D, 194 ABI_ILP32E, 195 ABI_LP64, 196 ABI_LP64F, 197 ABI_LP64D, 198 ABI_Unknown 199}; 200 201// Returns the target ABI, or else a StringError if the requested ABIName is 202// not supported for the given TT and FeatureBits combination. 203ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits, 204 StringRef ABIName); 205 206ABI getTargetABI(StringRef ABIName); 207 208// Returns the register used to hold the stack pointer after realignment. 209Register getBPReg(); 210 211} // namespace RISCVABI 212 213namespace RISCVFeatures { 214 215// Validates if the given combination of features are valid for the target 216// triple. Exits with report_fatal_error if not. 217void validate(const Triple &TT, const FeatureBitset &FeatureBits); 218 219} // namespace RISCVFeatures 220 221} // namespace llvm 222 223#endif 224