1//===-- PPCRegisterInfo.td - The PowerPC Register File -----*- tablegen -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9//
10//===----------------------------------------------------------------------===//
11
12let Namespace = "PPC" in {
13def sub_lt : SubRegIndex<1>;
14def sub_gt : SubRegIndex<1, 1>;
15def sub_eq : SubRegIndex<1, 2>;
16def sub_un : SubRegIndex<1, 3>;
17def sub_32 : SubRegIndex<32>;
18def sub_64 : SubRegIndex<64>;
19}
20
21
22class PPCReg<string n> : Register<n> {
23  let Namespace = "PPC";
24}
25
26// We identify all our registers with a 5-bit ID, for consistency's sake.
27
28// GPR - One of the 32 32-bit general-purpose registers
29class GPR<bits<5> num, string n> : PPCReg<n> {
30  let HWEncoding{4-0} = num;
31}
32
33// GP8 - One of the 32 64-bit general-purpose registers
34class GP8<GPR SubReg, string n> : PPCReg<n> {
35  let HWEncoding = SubReg.HWEncoding;
36  let SubRegs = [SubReg];
37  let SubRegIndices = [sub_32];
38}
39
40// SPE - One of the 32 64-bit general-purpose registers (SPE)
41class SPE<GPR SubReg, string n> : PPCReg<n> {
42  let HWEncoding = SubReg.HWEncoding;
43  let SubRegs = [SubReg];
44  let SubRegIndices = [sub_32];
45}
46
47// SPR - One of the 32-bit special-purpose registers
48class SPR<bits<10> num, string n> : PPCReg<n> {
49  let HWEncoding{9-0} = num;
50}
51
52// FPR - One of the 32 64-bit floating-point registers
53class FPR<bits<5> num, string n> : PPCReg<n> {
54  let HWEncoding{4-0} = num;
55}
56
57// QFPR - One of the 32 256-bit floating-point vector registers (used for QPX)
58class QFPR<FPR SubReg, string n> : PPCReg<n> {
59  let HWEncoding = SubReg.HWEncoding;
60  let SubRegs = [SubReg];
61  let SubRegIndices = [sub_64];
62}
63
64// VF - One of the 32 64-bit floating-point subregisters of the vector
65// registers (used by VSX).
66class VF<bits<5> num, string n> : PPCReg<n> {
67  let HWEncoding{4-0} = num;
68  let HWEncoding{5} = 1;
69}
70
71// VR - One of the 32 128-bit vector registers
72class VR<VF SubReg, string n> : PPCReg<n> {
73  let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
74  let HWEncoding{5} = 0;
75  let SubRegs = [SubReg];
76  let SubRegIndices = [sub_64];
77}
78
79// VSRL - One of the 32 128-bit VSX registers that overlap with the scalar
80// floating-point registers.
81class VSRL<FPR SubReg, string n> : PPCReg<n> {
82  let HWEncoding = SubReg.HWEncoding;
83  let SubRegs = [SubReg];
84  let SubRegIndices = [sub_64];
85}
86
87// VSXReg - One of the VSX registers in the range vs32-vs63 with numbering
88// and encoding to match.
89class VSXReg<bits<6> num, string n> : PPCReg<n> {
90  let HWEncoding{5-0} = num;
91}
92
93// CR - One of the 8 4-bit condition registers
94class CR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
95  let HWEncoding{2-0} = num;
96  let SubRegs = subregs;
97}
98
99// CRBIT - One of the 32 1-bit condition register fields
100class CRBIT<bits<5> num, string n> : PPCReg<n> {
101  let HWEncoding{4-0} = num;
102}
103
104// General-purpose registers
105foreach Index = 0-31 in {
106  def R#Index : GPR<Index, "r"#Index>, DwarfRegNum<[-2, Index]>;
107}
108
109// 64-bit General-purpose registers
110foreach Index = 0-31 in {
111  def X#Index : GP8<!cast<GPR>("R"#Index), "r"#Index>,
112                    DwarfRegNum<[Index, -2]>;
113}
114
115// SPE registers
116foreach Index = 0-31 in {
117  def S#Index : SPE<!cast<GPR>("R"#Index), "r"#Index>,
118                    DwarfRegNum<[!add(Index, 1200), !add(Index, 1200)]>;
119}
120
121// Floating-point registers
122foreach Index = 0-31 in {
123  def F#Index : FPR<Index, "f"#Index>,
124                DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
125}
126
127// 64-bit Floating-point subregisters of Altivec registers
128// Note: the register names are v0-v31 or vs32-vs63 depending on the use.
129//       Custom C++ code is used to produce the correct name and encoding.
130foreach Index = 0-31 in {
131  def VF#Index : VF<Index, "v" #Index>,
132                 DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
133}
134
135// QPX Floating-point registers
136foreach Index = 0-31 in {
137  def QF#Index : QFPR<!cast<FPR>("F"#Index), "q"#Index>,
138                 DwarfRegNum<[!add(Index, 32), !add(Index, 32)]>;
139}
140
141// Vector registers
142foreach Index = 0-31 in {
143  def V#Index : VR<!cast<VF>("VF"#Index), "v"#Index>,
144                DwarfRegNum<[!add(Index, 77), !add(Index, 77)]>;
145}
146
147// VSX registers
148foreach Index = 0-31 in {
149  def VSL#Index : VSRL<!cast<FPR>("F"#Index), "vs"#Index>,
150                  DwarfRegAlias<!cast<FPR>("F"#Index)>;
151}
152
153// Dummy VSX registers, this defines string: "vs32"-"vs63", and is only used for
154// asm printing.
155foreach Index = 32-63 in {
156  def VSX#Index : VSXReg<Index, "vs"#Index>;
157}
158
159// The representation of r0 when treated as the constant 0.
160def ZERO  : GPR<0, "0">,    DwarfRegAlias<R0>;
161def ZERO8 : GP8<ZERO, "0">, DwarfRegAlias<X0>;
162
163// Representations of the frame pointer used by ISD::FRAMEADDR.
164def FP   : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
165def FP8  : GP8<FP, "**FRAME POINTER**">;
166
167// Representations of the base pointer used by setjmp.
168def BP   : GPR<0 /* arbitrary */, "**BASE POINTER**">;
169def BP8  : GP8<BP, "**BASE POINTER**">;
170
171// Condition register bits
172def CR0LT : CRBIT< 0, "0">;
173def CR0GT : CRBIT< 1, "1">;
174def CR0EQ : CRBIT< 2, "2">;
175def CR0UN : CRBIT< 3, "3">;
176def CR1LT : CRBIT< 4, "4">;
177def CR1GT : CRBIT< 5, "5">;
178def CR1EQ : CRBIT< 6, "6">;
179def CR1UN : CRBIT< 7, "7">;
180def CR2LT : CRBIT< 8, "8">;
181def CR2GT : CRBIT< 9, "9">;
182def CR2EQ : CRBIT<10, "10">;
183def CR2UN : CRBIT<11, "11">;
184def CR3LT : CRBIT<12, "12">;
185def CR3GT : CRBIT<13, "13">;
186def CR3EQ : CRBIT<14, "14">;
187def CR3UN : CRBIT<15, "15">;
188def CR4LT : CRBIT<16, "16">;
189def CR4GT : CRBIT<17, "17">;
190def CR4EQ : CRBIT<18, "18">;
191def CR4UN : CRBIT<19, "19">;
192def CR5LT : CRBIT<20, "20">;
193def CR5GT : CRBIT<21, "21">;
194def CR5EQ : CRBIT<22, "22">;
195def CR5UN : CRBIT<23, "23">;
196def CR6LT : CRBIT<24, "24">;
197def CR6GT : CRBIT<25, "25">;
198def CR6EQ : CRBIT<26, "26">;
199def CR6UN : CRBIT<27, "27">;
200def CR7LT : CRBIT<28, "28">;
201def CR7GT : CRBIT<29, "29">;
202def CR7EQ : CRBIT<30, "30">;
203def CR7UN : CRBIT<31, "31">;
204
205// Condition registers
206let SubRegIndices = [sub_lt, sub_gt, sub_eq, sub_un] in {
207def CR0 : CR<0, "cr0", [CR0LT, CR0GT, CR0EQ, CR0UN]>, DwarfRegNum<[68, 68]>;
208def CR1 : CR<1, "cr1", [CR1LT, CR1GT, CR1EQ, CR1UN]>, DwarfRegNum<[69, 69]>;
209def CR2 : CR<2, "cr2", [CR2LT, CR2GT, CR2EQ, CR2UN]>, DwarfRegNum<[70, 70]>;
210def CR3 : CR<3, "cr3", [CR3LT, CR3GT, CR3EQ, CR3UN]>, DwarfRegNum<[71, 71]>;
211def CR4 : CR<4, "cr4", [CR4LT, CR4GT, CR4EQ, CR4UN]>, DwarfRegNum<[72, 72]>;
212def CR5 : CR<5, "cr5", [CR5LT, CR5GT, CR5EQ, CR5UN]>, DwarfRegNum<[73, 73]>;
213def CR6 : CR<6, "cr6", [CR6LT, CR6GT, CR6EQ, CR6UN]>, DwarfRegNum<[74, 74]>;
214def CR7 : CR<7, "cr7", [CR7LT, CR7GT, CR7EQ, CR7UN]>, DwarfRegNum<[75, 75]>;
215}
216
217// Link register
218def LR  : SPR<8, "lr">, DwarfRegNum<[-2, 65]>;
219//let Aliases = [LR] in
220def LR8 : SPR<8, "lr">, DwarfRegNum<[65, -2]>;
221
222// Count register
223def CTR  : SPR<9, "ctr">, DwarfRegNum<[-2, 66]>;
224def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66, -2]>;
225
226// VRsave register
227def VRSAVE: SPR<256, "vrsave">, DwarfRegNum<[109]>;
228
229// SPE extra registers
230// SPE Accumulator for multiply-accumulate SPE operations.  Never directly
231// accessed, so there's no real encoding for it.
232def SPEACC: DwarfRegNum<[99, 111]>;
233def SPEFSCR: SPR<512, "spefscr">, DwarfRegNum<[612, 112]>;
234
235def XER: SPR<1, "xer">, DwarfRegNum<[76]>;
236
237// Carry bit.  In the architecture this is really bit 0 of the XER register
238// (which really is SPR register 1);  this is the only bit interesting to a
239// compiler.
240def CARRY: SPR<1, "xer">, DwarfRegNum<[76]> {
241  let Aliases = [XER];
242}
243
244// FP rounding mode:  bits 30 and 31 of the FP status and control register
245// This is not allocated as a normal register; it appears only in
246// Uses and Defs.  The ABI says it needs to be preserved by a function,
247// but this is not achieved by saving and restoring it as with
248// most registers, it has to be done in code; to make this work all the
249// return and call instructions are described as Uses of RM, so instructions
250// that do nothing but change RM will not get deleted.
251def RM: PPCReg<"**ROUNDING MODE**">;
252
253/// Register classes
254// Allocate volatiles first
255// then nonvolatiles in reverse order since stmw/lmw save from rN to r31
256def GPRC : RegisterClass<"PPC", [i32,f32], 32, (add (sequence "R%u", 2, 12),
257                                                    (sequence "R%u", 30, 13),
258                                                    R31, R0, R1, FP, BP)> {
259  // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
260  // put it at the end of the list.
261  let AltOrders = [(add (sub GPRC, R2), R2)];
262  let AltOrderSelect = [{
263    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
264  }];
265}
266
267def G8RC : RegisterClass<"PPC", [i64], 64, (add (sequence "X%u", 2, 12),
268                                                (sequence "X%u", 30, 14),
269                                                X31, X13, X0, X1, FP8, BP8)> {
270  // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
271  // put it at the end of the list.
272  let AltOrders = [(add (sub G8RC, X2), X2)];
273  let AltOrderSelect = [{
274    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
275  }];
276}
277
278// For some instructions r0 is special (representing the value 0 instead of
279// the value in the r0 register), and we use these register subclasses to
280// prevent r0 from being allocated for use by those instructions.
281def GPRC_NOR0 : RegisterClass<"PPC", [i32,f32], 32, (add (sub GPRC, R0), ZERO)> {
282  // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
283  // put it at the end of the list.
284  let AltOrders = [(add (sub GPRC_NOR0, R2), R2)];
285  let AltOrderSelect = [{
286    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
287  }];
288}
289
290def G8RC_NOX0 : RegisterClass<"PPC", [i64], 64, (add (sub G8RC, X0), ZERO8)> {
291  // On non-Darwin PPC64 systems, R2 can be allocated, but must be restored, so
292  // put it at the end of the list.
293  let AltOrders = [(add (sub G8RC_NOX0, X2), X2)];
294  let AltOrderSelect = [{
295    return MF.getSubtarget<PPCSubtarget>().is64BitELFABI();
296  }];
297}
298
299def SPERC : RegisterClass<"PPC", [f64], 64, (add (sequence "S%u", 2, 12),
300                                                (sequence "S%u", 30, 13),
301                                                S31, S0, S1)>;
302
303// Allocate volatiles first, then non-volatiles in reverse order. With the SVR4
304// ABI the size of the Floating-point register save area is determined by the
305// allocated non-volatile register with the lowest register number, as FP
306// register N is spilled to offset 8 * (32 - N) below the back chain word of the
307// previous stack frame. By allocating non-volatiles in reverse order we make
308// sure that the Floating-point register save area is always as small as
309// possible because there aren't any unused spill slots.
310def F8RC : RegisterClass<"PPC", [f64], 64, (add (sequence "F%u", 0, 13),
311                                                (sequence "F%u", 31, 14))>;
312def F4RC : RegisterClass<"PPC", [f32], 32, (add F8RC)>;
313
314def VRRC : RegisterClass<"PPC",
315                         [v16i8,v8i16,v4i32,v2i64,v1i128,v4f32,v2f64, f128],
316                         128,
317                         (add V2, V3, V4, V5, V0, V1, V6, V7, V8, V9, V10, V11,
318                             V12, V13, V14, V15, V16, V17, V18, V19, V31, V30,
319                             V29, V28, V27, V26, V25, V24, V23, V22, V21, V20)>;
320
321// VSX register classes (the allocation order mirrors that of the corresponding
322// subregister classes).
323def VSLRC : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
324                          (add (sequence "VSL%u", 0, 13),
325                               (sequence "VSL%u", 31, 14))>;
326def VSRC  : RegisterClass<"PPC", [v4i32,v4f32,v2f64,v2i64], 128,
327                          (add VSLRC, VRRC)>;
328
329// Register classes for the 64-bit "scalar" VSX subregisters.
330def VFRC :  RegisterClass<"PPC", [f64], 64,
331                          (add VF2, VF3, VF4, VF5, VF0, VF1, VF6, VF7,
332                               VF8, VF9, VF10, VF11, VF12, VF13, VF14,
333                               VF15, VF16, VF17, VF18, VF19, VF31, VF30,
334                               VF29, VF28, VF27, VF26, VF25, VF24, VF23,
335                               VF22, VF21, VF20)>;
336def VSFRC : RegisterClass<"PPC", [f64], 64, (add F8RC, VFRC)>;
337
338// Allow spilling GPR's into caller-saved VSR's.
339def SPILLTOVSRRC : RegisterClass<"PPC", [i64, f64], 64, (add G8RC, (sub VSFRC,
340				(sequence "VF%u", 31, 20),
341				(sequence "F%u", 31, 14)))>;
342
343// Register class for single precision scalars in VSX registers
344def VSSRC : RegisterClass<"PPC", [f32], 32, (add VSFRC)>;
345
346// For QPX
347def QFRC : RegisterClass<"PPC", [v4f64], 256, (add (sequence "QF%u", 0, 13),
348                                                (sequence "QF%u", 31, 14))>;
349def QSRC : RegisterClass<"PPC", [v4f32], 128, (add QFRC)>;
350def QBRC : RegisterClass<"PPC", [v4i1], 256, (add QFRC)> {
351  // These are actually stored as floating-point values where a positive
352  // number is true and anything else (including NaN) is false.
353  let Size = 256;
354}
355
356def CRBITRC : RegisterClass<"PPC", [i1], 32,
357  (add CR2LT, CR2GT, CR2EQ, CR2UN,
358       CR3LT, CR3GT, CR3EQ, CR3UN,
359       CR4LT, CR4GT, CR4EQ, CR4UN,
360       CR5LT, CR5GT, CR5EQ, CR5UN,
361       CR6LT, CR6GT, CR6EQ, CR6UN,
362       CR7LT, CR7GT, CR7EQ, CR7UN,
363       CR1LT, CR1GT, CR1EQ, CR1UN,
364       CR0LT, CR0GT, CR0EQ, CR0UN)> {
365  let Size = 32;
366  let AltOrders = [(sub CRBITRC, CR2LT, CR2GT, CR2EQ, CR2UN, CR3LT, CR3GT,
367                        CR3EQ, CR3UN, CR4LT, CR4GT, CR4EQ, CR4UN)];
368  let AltOrderSelect = [{
369    return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
370           MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
371  }];
372}
373
374def CRRC : RegisterClass<"PPC", [i32], 32,
375  (add CR0, CR1, CR5, CR6,
376       CR7, CR2, CR3, CR4)> {
377  let AltOrders = [(sub CRRC, CR2, CR3, CR4)];
378  let AltOrderSelect = [{
379    return MF.getSubtarget<PPCSubtarget>().isELFv2ABI() &&
380           MF.getInfo<PPCFunctionInfo>()->isNonVolatileCRDisabled();
381  }];
382}
383// The CTR registers are not allocatable because they're used by the
384// decrement-and-branch instructions, and thus need to stay live across
385// multiple basic blocks.
386def CTRRC : RegisterClass<"PPC", [i32], 32, (add CTR)> {
387  let isAllocatable = 0;
388}
389def CTRRC8 : RegisterClass<"PPC", [i64], 64, (add CTR8)> {
390  let isAllocatable = 0;
391}
392
393def VRSAVERC : RegisterClass<"PPC", [i32], 32, (add VRSAVE)>;
394def CARRYRC : RegisterClass<"PPC", [i32], 32, (add CARRY, XER)> {
395  let CopyCost = -1;
396}
397
398