1//===-- AVRMCCodeEmitter.h - Convert AVR Code to Machine Code -------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the AVRMCCodeEmitter class.
10//
11//===----------------------------------------------------------------------===//
12//
13
14#ifndef LLVM_AVR_CODE_EMITTER_H
15#define LLVM_AVR_CODE_EMITTER_H
16
17#include "AVRFixupKinds.h"
18
19#include "llvm/MC/MCCodeEmitter.h"
20#include "llvm/Support/DataTypes.h"
21
22#define GET_INSTRINFO_OPERAND_TYPES_ENUM
23#include "AVRGenInstrInfo.inc"
24
25namespace llvm {
26
27class MCContext;
28class MCExpr;
29class MCFixup;
30class MCInst;
31class MCInstrInfo;
32class MCOperand;
33class MCSubtargetInfo;
34class raw_ostream;
35
36/// Writes AVR machine code to a stream.
37class AVRMCCodeEmitter : public MCCodeEmitter {
38public:
39  AVRMCCodeEmitter(const MCInstrInfo &MCII, MCContext &Ctx)
40      : MCII(MCII), Ctx(Ctx) {}
41
42private:
43  /// Finishes up encoding an LD/ST instruction.
44  /// The purpose of this function is to set an bit in the instruction
45  /// which follows no logical pattern. See the implementation for details.
46  unsigned loadStorePostEncoder(const MCInst &MI, unsigned EncodedValue,
47                                const MCSubtargetInfo &STI) const;
48
49  /// Gets the encoding for a conditional branch target.
50  template <AVR::Fixups Fixup>
51  unsigned encodeRelCondBrTarget(const MCInst &MI, unsigned OpNo,
52                                 SmallVectorImpl<MCFixup> &Fixups,
53                                 const MCSubtargetInfo &STI) const;
54
55  /// Encodes the `PTRREGS` operand to a load or store instruction.
56  unsigned encodeLDSTPtrReg(const MCInst &MI, unsigned OpNo,
57                            SmallVectorImpl<MCFixup> &Fixups,
58                            const MCSubtargetInfo &STI) const;
59
60  /// Encodes a `register+immediate` operand for `LDD`/`STD`.
61  unsigned encodeMemri(const MCInst &MI, unsigned OpNo,
62                       SmallVectorImpl<MCFixup> &Fixups,
63                       const MCSubtargetInfo &STI) const;
64
65  /// Takes the complement of a number (~0 - val).
66  unsigned encodeComplement(const MCInst &MI, unsigned OpNo,
67                            SmallVectorImpl<MCFixup> &Fixups,
68                            const MCSubtargetInfo &STI) const;
69
70  /// Encodes an immediate value with a given fixup.
71  /// \tparam Offset The offset into the instruction for the fixup.
72  template <AVR::Fixups Fixup, unsigned Offset>
73  unsigned encodeImm(const MCInst &MI, unsigned OpNo,
74                     SmallVectorImpl<MCFixup> &Fixups,
75                     const MCSubtargetInfo &STI) const;
76
77  /// Gets the encoding of the target for the `CALL k` instruction.
78  unsigned encodeCallTarget(const MCInst &MI, unsigned OpNo,
79                            SmallVectorImpl<MCFixup> &Fixups,
80                            const MCSubtargetInfo &STI) const;
81
82  /// TableGen'ed function to get the binary encoding for an instruction.
83  uint64_t getBinaryCodeForInstr(const MCInst &MI,
84                                 SmallVectorImpl<MCFixup> &Fixups,
85                                 const MCSubtargetInfo &STI) const;
86
87  unsigned getExprOpValue(const MCExpr *Expr, SmallVectorImpl<MCFixup> &Fixups,
88                          const MCSubtargetInfo &STI) const;
89
90  /// Returns the binary encoding of operand.
91  ///
92  /// If the machine operand requires relocation, the relocation is recorded
93  /// and zero is returned.
94  unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
95                             SmallVectorImpl<MCFixup> &Fixups,
96                             const MCSubtargetInfo &STI) const;
97
98  void emitInstruction(uint64_t Val, unsigned Size, const MCSubtargetInfo &STI,
99                       raw_ostream &OS) const;
100
101  void encodeInstruction(const MCInst &MI, raw_ostream &OS,
102                         SmallVectorImpl<MCFixup> &Fixups,
103                         const MCSubtargetInfo &STI) const override;
104
105  AVRMCCodeEmitter(const AVRMCCodeEmitter &) = delete;
106  void operator=(const AVRMCCodeEmitter &) = delete;
107
108  const MCInstrInfo &MCII;
109  MCContext &Ctx;
110};
111
112} // end namespace of llvm.
113
114#endif // LLVM_AVR_CODE_EMITTER_H
115
116