1//===-- ArchSpec.h ----------------------------------------------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#ifndef LLDB_UTILITY_ARCHSPEC_H
10#define LLDB_UTILITY_ARCHSPEC_H
11
12#include "lldb/Utility/CompletionRequest.h"
13#include "lldb/Utility/ConstString.h"
14#include "lldb/lldb-enumerations.h"
15#include "lldb/lldb-forward.h"
16#include "lldb/lldb-private-enumerations.h"
17#include "llvm/ADT/StringRef.h"
18#include "llvm/ADT/Triple.h"
19#include "llvm/Support/YAMLTraits.h"
20#include <cstddef>
21#include <cstdint>
22#include <string>
23
24namespace lldb_private {
25
26/// \class ArchSpec ArchSpec.h "lldb/Utility/ArchSpec.h" An architecture
27/// specification class.
28///
29/// A class designed to be created from a cpu type and subtype, a
30/// string representation, or an llvm::Triple.  Keeping all of the conversions
31/// of strings to architecture enumeration values confined to this class
32/// allows new architecture support to be added easily.
33class ArchSpec {
34public:
35  enum MIPSSubType {
36    eMIPSSubType_unknown,
37    eMIPSSubType_mips32,
38    eMIPSSubType_mips32r2,
39    eMIPSSubType_mips32r6,
40    eMIPSSubType_mips32el,
41    eMIPSSubType_mips32r2el,
42    eMIPSSubType_mips32r6el,
43    eMIPSSubType_mips64,
44    eMIPSSubType_mips64r2,
45    eMIPSSubType_mips64r6,
46    eMIPSSubType_mips64el,
47    eMIPSSubType_mips64r2el,
48    eMIPSSubType_mips64r6el,
49  };
50
51  // Masks for the ases word of an ABI flags structure.
52  enum MIPSASE {
53    eMIPSAse_dsp = 0x00000001,       // DSP ASE
54    eMIPSAse_dspr2 = 0x00000002,     // DSP R2 ASE
55    eMIPSAse_eva = 0x00000004,       // Enhanced VA Scheme
56    eMIPSAse_mcu = 0x00000008,       // MCU (MicroController) ASE
57    eMIPSAse_mdmx = 0x00000010,      // MDMX ASE
58    eMIPSAse_mips3d = 0x00000020,    // MIPS-3D ASE
59    eMIPSAse_mt = 0x00000040,        // MT ASE
60    eMIPSAse_smartmips = 0x00000080, // SmartMIPS ASE
61    eMIPSAse_virt = 0x00000100,      // VZ ASE
62    eMIPSAse_msa = 0x00000200,       // MSA ASE
63    eMIPSAse_mips16 = 0x00000400,    // MIPS16 ASE
64    eMIPSAse_micromips = 0x00000800, // MICROMIPS ASE
65    eMIPSAse_xpa = 0x00001000,       // XPA ASE
66    eMIPSAse_mask = 0x00001fff,
67    eMIPSABI_O32 = 0x00002000,
68    eMIPSABI_N32 = 0x00004000,
69    eMIPSABI_N64 = 0x00008000,
70    eMIPSABI_O64 = 0x00020000,
71    eMIPSABI_EABI32 = 0x00040000,
72    eMIPSABI_EABI64 = 0x00080000,
73    eMIPSABI_mask = 0x000ff000
74  };
75
76  // MIPS Floating point ABI Values
77  enum MIPS_ABI_FP {
78    eMIPS_ABI_FP_ANY = 0x00000000,
79    eMIPS_ABI_FP_DOUBLE = 0x00100000, // hard float / -mdouble-float
80    eMIPS_ABI_FP_SINGLE = 0x00200000, // hard float / -msingle-float
81    eMIPS_ABI_FP_SOFT = 0x00300000,   // soft float
82    eMIPS_ABI_FP_OLD_64 = 0x00400000, // -mips32r2 -mfp64
83    eMIPS_ABI_FP_XX = 0x00500000,     // -mfpxx
84    eMIPS_ABI_FP_64 = 0x00600000,     // -mips32r2 -mfp64
85    eMIPS_ABI_FP_64A = 0x00700000,    // -mips32r2 -mfp64 -mno-odd-spreg
86    eMIPS_ABI_FP_mask = 0x00700000
87  };
88
89  // ARM specific e_flags
90  enum ARMeflags {
91    eARM_abi_soft_float = 0x00000200,
92    eARM_abi_hard_float = 0x00000400
93  };
94
95  enum Core {
96    eCore_arm_generic,
97    eCore_arm_armv4,
98    eCore_arm_armv4t,
99    eCore_arm_armv5,
100    eCore_arm_armv5e,
101    eCore_arm_armv5t,
102    eCore_arm_armv6,
103    eCore_arm_armv6m,
104    eCore_arm_armv7,
105    eCore_arm_armv7l,
106    eCore_arm_armv7f,
107    eCore_arm_armv7s,
108    eCore_arm_armv7k,
109    eCore_arm_armv7m,
110    eCore_arm_armv7em,
111    eCore_arm_xscale,
112
113    eCore_thumb,
114    eCore_thumbv4t,
115    eCore_thumbv5,
116    eCore_thumbv5e,
117    eCore_thumbv6,
118    eCore_thumbv6m,
119    eCore_thumbv7,
120    eCore_thumbv7s,
121    eCore_thumbv7k,
122    eCore_thumbv7f,
123    eCore_thumbv7m,
124    eCore_thumbv7em,
125    eCore_arm_arm64,
126    eCore_arm_armv8,
127    eCore_arm_armv8l,
128    eCore_arm_arm64_32,
129    eCore_arm_aarch64,
130
131    eCore_mips32,
132    eCore_mips32r2,
133    eCore_mips32r3,
134    eCore_mips32r5,
135    eCore_mips32r6,
136    eCore_mips32el,
137    eCore_mips32r2el,
138    eCore_mips32r3el,
139    eCore_mips32r5el,
140    eCore_mips32r6el,
141    eCore_mips64,
142    eCore_mips64r2,
143    eCore_mips64r3,
144    eCore_mips64r5,
145    eCore_mips64r6,
146    eCore_mips64el,
147    eCore_mips64r2el,
148    eCore_mips64r3el,
149    eCore_mips64r5el,
150    eCore_mips64r6el,
151
152    eCore_ppc_generic,
153    eCore_ppc_ppc601,
154    eCore_ppc_ppc602,
155    eCore_ppc_ppc603,
156    eCore_ppc_ppc603e,
157    eCore_ppc_ppc603ev,
158    eCore_ppc_ppc604,
159    eCore_ppc_ppc604e,
160    eCore_ppc_ppc620,
161    eCore_ppc_ppc750,
162    eCore_ppc_ppc7400,
163    eCore_ppc_ppc7450,
164    eCore_ppc_ppc970,
165
166    eCore_ppc64le_generic,
167    eCore_ppc64_generic,
168    eCore_ppc64_ppc970_64,
169
170    eCore_s390x_generic,
171
172    eCore_sparc_generic,
173
174    eCore_sparc9_generic,
175
176    eCore_x86_32_i386,
177    eCore_x86_32_i486,
178    eCore_x86_32_i486sx,
179    eCore_x86_32_i686,
180
181    eCore_x86_64_x86_64,
182    eCore_x86_64_x86_64h, // Haswell enabled x86_64
183    eCore_hexagon_generic,
184    eCore_hexagon_hexagonv4,
185    eCore_hexagon_hexagonv5,
186
187    eCore_uknownMach32,
188    eCore_uknownMach64,
189
190    eCore_arc, // little endian ARC
191
192    eCore_avr,
193
194    eCore_wasm32,
195
196    kNumCores,
197
198    kCore_invalid,
199    // The following constants are used for wildcard matching only
200    kCore_any,
201    kCore_arm_any,
202    kCore_ppc_any,
203    kCore_ppc64_any,
204    kCore_x86_32_any,
205    kCore_x86_64_any,
206    kCore_hexagon_any,
207
208    kCore_arm_first = eCore_arm_generic,
209    kCore_arm_last = eCore_arm_xscale,
210
211    kCore_thumb_first = eCore_thumb,
212    kCore_thumb_last = eCore_thumbv7em,
213
214    kCore_ppc_first = eCore_ppc_generic,
215    kCore_ppc_last = eCore_ppc_ppc970,
216
217    kCore_ppc64_first = eCore_ppc64_generic,
218    kCore_ppc64_last = eCore_ppc64_ppc970_64,
219
220    kCore_x86_32_first = eCore_x86_32_i386,
221    kCore_x86_32_last = eCore_x86_32_i686,
222
223    kCore_x86_64_first = eCore_x86_64_x86_64,
224    kCore_x86_64_last = eCore_x86_64_x86_64h,
225
226    kCore_hexagon_first = eCore_hexagon_generic,
227    kCore_hexagon_last = eCore_hexagon_hexagonv5,
228
229    kCore_mips32_first = eCore_mips32,
230    kCore_mips32_last = eCore_mips32r6,
231
232    kCore_mips32el_first = eCore_mips32el,
233    kCore_mips32el_last = eCore_mips32r6el,
234
235    kCore_mips64_first = eCore_mips64,
236    kCore_mips64_last = eCore_mips64r6,
237
238    kCore_mips64el_first = eCore_mips64el,
239    kCore_mips64el_last = eCore_mips64r6el,
240
241    kCore_mips_first = eCore_mips32,
242    kCore_mips_last = eCore_mips64r6el
243
244  };
245
246  /// Default constructor.
247  ///
248  /// Default constructor that initializes the object with invalid cpu type
249  /// and subtype values.
250  ArchSpec();
251
252  /// Constructor over triple.
253  ///
254  /// Constructs an ArchSpec with properties consistent with the given Triple.
255  explicit ArchSpec(const llvm::Triple &triple);
256  explicit ArchSpec(const char *triple_cstr);
257  explicit ArchSpec(llvm::StringRef triple_str);
258  /// Constructor over architecture name.
259  ///
260  /// Constructs an ArchSpec with properties consistent with the given object
261  /// type and architecture name.
262  explicit ArchSpec(ArchitectureType arch_type, uint32_t cpu_type,
263                    uint32_t cpu_subtype);
264
265  /// Destructor.
266  ~ArchSpec();
267
268  /// Returns true if the OS, vendor and environment fields of the triple are
269  /// unset. The triple is expected to be normalized
270  /// (llvm::Triple::normalize).
271  static bool ContainsOnlyArch(const llvm::Triple &normalized_triple);
272
273  static void ListSupportedArchNames(StringList &list);
274  static void AutoComplete(CompletionRequest &request);
275
276  /// Returns a static string representing the current architecture.
277  ///
278  /// \return A static string corresponding to the current
279  ///         architecture.
280  const char *GetArchitectureName() const;
281
282  /// if MIPS architecture return true.
283  ///
284  ///  \return a boolean value.
285  bool IsMIPS() const;
286
287  /// Returns a string representing current architecture as a target CPU for
288  /// tools like compiler, disassembler etc.
289  ///
290  /// \return A string representing target CPU for the current
291  ///         architecture.
292  std::string GetClangTargetCPU() const;
293
294  /// Return a string representing target application ABI.
295  ///
296  /// \return A string representing target application ABI.
297  std::string GetTargetABI() const;
298
299  /// Clears the object state.
300  ///
301  /// Clears the object state back to a default invalid state.
302  void Clear();
303
304  /// Returns the size in bytes of an address of the current architecture.
305  ///
306  /// \return The byte size of an address of the current architecture.
307  uint32_t GetAddressByteSize() const;
308
309  /// Returns a machine family for the current architecture.
310  ///
311  /// \return An LLVM arch type.
312  llvm::Triple::ArchType GetMachine() const;
313
314  /// Returns the distribution id of the architecture.
315  ///
316  /// This will be something like "ubuntu", "fedora", etc. on Linux.
317  ///
318  /// \return A ConstString ref containing the distribution id,
319  ///         potentially empty.
320  ConstString GetDistributionId() const;
321
322  /// Set the distribution id of the architecture.
323  ///
324  /// This will be something like "ubuntu", "fedora", etc. on Linux. This
325  /// should be the same value returned by HostInfo::GetDistributionId ().
326  void SetDistributionId(const char *distribution_id);
327
328  /// Tests if this ArchSpec is valid.
329  ///
330  /// \return True if the current architecture is valid, false
331  ///         otherwise.
332  bool IsValid() const {
333    return m_core >= eCore_arm_generic && m_core < kNumCores;
334  }
335  explicit operator bool() const { return IsValid(); }
336
337  bool TripleVendorWasSpecified() const {
338    return !m_triple.getVendorName().empty();
339  }
340
341  bool TripleOSWasSpecified() const { return !m_triple.getOSName().empty(); }
342
343  bool TripleEnvironmentWasSpecified() const {
344    return m_triple.hasEnvironment();
345  }
346
347  /// Merges fields from another ArchSpec into this ArchSpec.
348  ///
349  /// This will use the supplied ArchSpec to fill in any fields of the triple
350  /// in this ArchSpec which were unspecified.  This can be used to refine a
351  /// generic ArchSpec with a more specific one. For example, if this
352  /// ArchSpec's triple is something like i386-unknown-unknown-unknown, and we
353  /// have a triple which is x64-pc-windows-msvc, then merging that triple
354  /// into this one will result in the triple i386-pc-windows-msvc.
355  ///
356  void MergeFrom(const ArchSpec &other);
357
358  /// Change the architecture object type, CPU type and OS type.
359  ///
360  /// \param[in] arch_type The object type of this ArchSpec.
361  ///
362  /// \param[in] cpu The required CPU type.
363  ///
364  /// \param[in] os The optional OS type
365  /// The default value of 0 was chosen to from the ELF spec value
366  /// ELFOSABI_NONE.  ELF is the only one using this parameter.  If another
367  /// format uses this parameter and 0 does not work, use a value over
368  /// 255 because in the ELF header this is value is only a byte.
369  ///
370  /// \return True if the object, and CPU were successfully set.
371  ///
372  /// As a side effect, the vendor value is usually set to unknown. The
373  /// exceptions are
374  ///   aarch64-apple-ios
375  ///   arm-apple-ios
376  ///   thumb-apple-ios
377  ///   x86-apple-
378  ///   x86_64-apple-
379  ///
380  /// As a side effect, the os value is usually set to unknown The exceptions
381  /// are
382  ///   *-*-aix
383  ///   aarch64-apple-ios
384  ///   arm-apple-ios
385  ///   thumb-apple-ios
386  ///   powerpc-apple-darwin
387  ///   *-*-freebsd
388  ///   *-*-linux
389  ///   *-*-netbsd
390  ///   *-*-openbsd
391  ///   *-*-solaris
392  bool SetArchitecture(ArchitectureType arch_type, uint32_t cpu, uint32_t sub,
393                       uint32_t os = 0);
394
395  /// Returns the byte order for the architecture specification.
396  ///
397  /// \return The endian enumeration for the current endianness of
398  ///     the architecture specification
399  lldb::ByteOrder GetByteOrder() const;
400
401  /// Sets this ArchSpec's byte order.
402  ///
403  /// In the common case there is no need to call this method as the byte
404  /// order can almost always be determined by the architecture. However, many
405  /// CPU's are bi-endian (ARM, Alpha, PowerPC, etc) and the default/assumed
406  /// byte order may be incorrect.
407  void SetByteOrder(lldb::ByteOrder byte_order) { m_byte_order = byte_order; }
408
409  uint32_t GetMinimumOpcodeByteSize() const;
410
411  uint32_t GetMaximumOpcodeByteSize() const;
412
413  Core GetCore() const { return m_core; }
414
415  uint32_t GetMachOCPUType() const;
416
417  uint32_t GetMachOCPUSubType() const;
418
419  /// Architecture data byte width accessor
420  ///
421  /// \return the size in 8-bit (host) bytes of a minimum addressable unit
422  /// from the Architecture's data bus
423  uint32_t GetDataByteSize() const;
424
425  /// Architecture code byte width accessor
426  ///
427  /// \return the size in 8-bit (host) bytes of a minimum addressable unit
428  /// from the Architecture's code bus
429  uint32_t GetCodeByteSize() const;
430
431  /// Architecture triple accessor.
432  ///
433  /// \return A triple describing this ArchSpec.
434  llvm::Triple &GetTriple() { return m_triple; }
435
436  /// Architecture triple accessor.
437  ///
438  /// \return A triple describing this ArchSpec.
439  const llvm::Triple &GetTriple() const { return m_triple; }
440
441  void DumpTriple(llvm::raw_ostream &s) const;
442
443  /// Architecture triple setter.
444  ///
445  /// Configures this ArchSpec according to the given triple.  If the triple
446  /// has unknown components in all of the vendor, OS, and the optional
447  /// environment field (i.e. "i386-unknown-unknown") then default values are
448  /// taken from the host.  Architecture and environment components are used
449  /// to further resolve the CPU type and subtype, endian characteristics,
450  /// etc.
451  ///
452  /// \return A triple describing this ArchSpec.
453  bool SetTriple(const llvm::Triple &triple);
454
455  bool SetTriple(llvm::StringRef triple_str);
456
457  /// Returns the default endianness of the architecture.
458  ///
459  /// \return The endian enumeration for the default endianness of
460  ///         the architecture.
461  lldb::ByteOrder GetDefaultEndian() const;
462
463  /// Returns true if 'char' is a signed type by default in the architecture
464  /// false otherwise
465  ///
466  /// \return True if 'char' is a signed type by default on the
467  ///         architecture and false otherwise.
468  bool CharIsSignedByDefault() const;
469
470  /// Compare an ArchSpec to another ArchSpec, requiring an exact cpu type
471  /// match between them. e.g. armv7s is not an exact match with armv7 - this
472  /// would return false
473  ///
474  /// \return true if the two ArchSpecs match.
475  bool IsExactMatch(const ArchSpec &rhs) const;
476
477  /// Compare an ArchSpec to another ArchSpec, requiring a compatible cpu type
478  /// match between them. e.g. armv7s is compatible with armv7 - this method
479  /// would return true
480  ///
481  /// \return true if the two ArchSpecs are compatible
482  bool IsCompatibleMatch(const ArchSpec &rhs) const;
483
484  bool IsFullySpecifiedTriple() const;
485
486  void PiecewiseTripleCompare(const ArchSpec &other, bool &arch_different,
487                              bool &vendor_different, bool &os_different,
488                              bool &os_version_different,
489                              bool &env_different) const;
490
491  /// Detect whether this architecture uses thumb code exclusively
492  ///
493  /// Some embedded ARM chips (e.g. the ARM Cortex M0-7 line) can only execute
494  /// the Thumb instructions, never Arm.  We should normally pick up
495  /// arm/thumbness from their the processor status bits (cpsr/xpsr) or hints
496  /// on each function - but when doing bare-boards low level debugging
497  /// (especially common with these embedded processors), we may not have
498  /// those things easily accessible.
499  ///
500  /// \return true if this is an arm ArchSpec which can only execute Thumb
501  ///         instructions
502  bool IsAlwaysThumbInstructions() const;
503
504  uint32_t GetFlags() const { return m_flags; }
505
506  void SetFlags(uint32_t flags) { m_flags = flags; }
507
508  void SetFlags(std::string elf_abi);
509
510protected:
511  bool IsEqualTo(const ArchSpec &rhs, bool exact_match) const;
512  void UpdateCore();
513
514  llvm::Triple m_triple;
515  Core m_core = kCore_invalid;
516  lldb::ByteOrder m_byte_order = lldb::eByteOrderInvalid;
517
518  // Additional arch flags which we cannot get from triple and core For MIPS
519  // these are application specific extensions like micromips, mips16 etc.
520  uint32_t m_flags = 0;
521
522  ConstString m_distribution_id;
523
524  // Called when m_def or m_entry are changed.  Fills in all remaining members
525  // with default values.
526  void CoreUpdated(bool update_triple);
527};
528
529/// \fn bool operator< (const ArchSpec& lhs, const ArchSpec& rhs) Less than
530/// operator.
531///
532/// Tests two ArchSpec objects to see if \a lhs is less than \a rhs.
533///
534/// \param[in] lhs The Left Hand Side ArchSpec object to compare. \param[in]
535/// rhs The Left Hand Side ArchSpec object to compare.
536///
537/// \return true if \a lhs is less than \a rhs
538bool operator<(const ArchSpec &lhs, const ArchSpec &rhs);
539bool operator==(const ArchSpec &lhs, const ArchSpec &rhs);
540
541bool ParseMachCPUDashSubtypeTriple(llvm::StringRef triple_str, ArchSpec &arch);
542
543} // namespace lldb_private
544
545namespace llvm {
546namespace yaml {
547template <> struct ScalarTraits<lldb_private::ArchSpec> {
548  static void output(const lldb_private::ArchSpec &, void *, raw_ostream &);
549  static StringRef input(StringRef, void *, lldb_private::ArchSpec &);
550  static QuotingType mustQuote(StringRef S) { return QuotingType::Double; }
551};
552} // namespace yaml
553} // namespace llvm
554
555LLVM_YAML_IS_SEQUENCE_VECTOR(lldb_private::ArchSpec)
556
557#endif // LLDB_UTILITY_ARCHSPEC_H
558