1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2010 Hudson River Trading LLC 5 * Written by: John H. Baldwin <jhb@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * This driver provides a pseudo-bus to enumerate the PCI buses 32 * present on a system using a QPI chipset. It creates a qpi0 bus that 33 * is a child of nexus0 and then creates Host-PCI bridges as a 34 * child of that. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD$"); 39 40#include <sys/param.h> 41#include <sys/bus.h> 42#include <sys/kernel.h> 43#include <sys/malloc.h> 44#include <sys/module.h> 45#include <sys/rman.h> 46#include <sys/systm.h> 47 48#include <machine/cputypes.h> 49#include <machine/md_var.h> 50#include <x86/legacyvar.h> 51#include <x86/pci_cfgreg.h> 52#include <x86/specialreg.h> 53 54#include <dev/pci/pcireg.h> 55#include <dev/pci/pcivar.h> 56#include <dev/pci/pcib_private.h> 57#include "pcib_if.h" 58 59struct qpi_device { 60 int qd_pcibus; 61}; 62 63static MALLOC_DEFINE(M_QPI, "qpidrv", "qpi system device"); 64 65static void 66qpi_identify(driver_t *driver, device_t parent) 67{ 68 int do_qpi; 69 70 /* Check CPUID to ensure this is an i7 CPU of some sort. */ 71 if (cpu_vendor_id != CPU_VENDOR_INTEL || 72 CPUID_TO_FAMILY(cpu_id) != 0x6) 73 return; 74 75 /* Only discover buses with configuration devices if allowed by user */ 76 do_qpi = 0; 77 TUNABLE_INT_FETCH("hw.attach_intel_csr_pci", &do_qpi); 78 if (!do_qpi) 79 return; 80 81 /* PCI config register access is required. */ 82 if (pci_cfgregopen() == 0) 83 return; 84 85 /* Add a qpi bus device. */ 86 if (BUS_ADD_CHILD(parent, 20, "qpi", -1) == NULL) 87 panic("Failed to add qpi bus"); 88} 89 90static int 91qpi_probe(device_t dev) 92{ 93 94 device_set_desc(dev, "QPI system bus"); 95 return (BUS_PROBE_SPECIFIC); 96} 97 98/* 99 * Look for a PCI bus with the specified bus address. If one is found, 100 * add a pcib device and return 0. Otherwise, return an error code. 101 */ 102static int 103qpi_probe_pcib(device_t dev, int bus) 104{ 105 struct qpi_device *qdev; 106 device_t child; 107 uint32_t devid; 108 int s; 109 110 /* 111 * If a PCI bus already exists for this bus number, then 112 * fail. 113 */ 114 if (pci_find_bsf(bus, 0, 0) != NULL) 115 return (EEXIST); 116 117 /* 118 * Attempt to read the device id for every slot, function 0 on 119 * the bus. If all read values are 0xffffffff this means that 120 * the bus is not present. 121 */ 122 for (s = 0; s <= PCI_SLOTMAX; s++) { 123 devid = pci_cfgregread(bus, s, 0, PCIR_DEVVENDOR, 4); 124 if (devid != 0xffffffff) 125 break; 126 } 127 if (devid == 0xffffffff) 128 return (ENOENT); 129 130 if ((devid & 0xffff) != 0x8086) { 131 if (bootverbose) 132 device_printf(dev, 133 "Device at pci%d.%d.0 has non-Intel vendor 0x%x\n", 134 bus, s, devid & 0xffff); 135 return (ENXIO); 136 } 137 138 child = BUS_ADD_CHILD(dev, 0, "pcib", -1); 139 if (child == NULL) 140 panic("%s: failed to add pci bus %d", device_get_nameunit(dev), 141 bus); 142 qdev = malloc(sizeof(struct qpi_device), M_QPI, M_WAITOK); 143 qdev->qd_pcibus = bus; 144 device_set_ivars(child, qdev); 145 return (0); 146} 147 148static int 149qpi_attach(device_t dev) 150{ 151 int bus; 152 153 /* 154 * Each processor socket has a dedicated PCI bus, sometimes 155 * not enumerated by ACPI. Probe all unattached buses from 0 156 * to 255. 157 */ 158 for (bus = PCI_BUSMAX; bus >= 0; bus--) 159 qpi_probe_pcib(dev, bus); 160 161 return (bus_generic_attach(dev)); 162} 163 164static int 165qpi_print_child(device_t bus, device_t child) 166{ 167 struct qpi_device *qdev; 168 int retval = 0; 169 170 qdev = device_get_ivars(child); 171 retval += bus_print_child_header(bus, child); 172 if (qdev->qd_pcibus != -1) 173 retval += printf(" pcibus %d", qdev->qd_pcibus); 174 retval += bus_print_child_footer(bus, child); 175 176 return (retval); 177} 178 179static int 180qpi_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 181{ 182 struct qpi_device *qdev; 183 184 qdev = device_get_ivars(child); 185 switch (which) { 186 case PCIB_IVAR_BUS: 187 *result = qdev->qd_pcibus; 188 break; 189 default: 190 return (ENOENT); 191 } 192 return (0); 193} 194 195static device_method_t qpi_methods[] = { 196 /* Device interface */ 197 DEVMETHOD(device_identify, qpi_identify), 198 DEVMETHOD(device_probe, qpi_probe), 199 DEVMETHOD(device_attach, qpi_attach), 200 DEVMETHOD(device_shutdown, bus_generic_shutdown), 201 DEVMETHOD(device_suspend, bus_generic_suspend), 202 DEVMETHOD(device_resume, bus_generic_resume), 203 204 /* Bus interface */ 205 DEVMETHOD(bus_print_child, qpi_print_child), 206 DEVMETHOD(bus_add_child, bus_generic_add_child), 207 DEVMETHOD(bus_read_ivar, qpi_read_ivar), 208 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 209 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 210 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 211 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 212 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 213 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 214 215 { 0, 0 } 216}; 217 218static devclass_t qpi_devclass; 219 220DEFINE_CLASS_0(qpi, qpi_driver, qpi_methods, 0); 221DRIVER_MODULE(qpi, nexus, qpi_driver, qpi_devclass, 0, 0); 222 223static int 224qpi_pcib_probe(device_t dev) 225{ 226 227 device_set_desc(dev, "QPI Host-PCI bridge"); 228 return (BUS_PROBE_SPECIFIC); 229} 230 231static int 232qpi_pcib_attach(device_t dev) 233{ 234 235 device_add_child(dev, "pci", -1); 236 return (bus_generic_attach(dev)); 237} 238 239static int 240qpi_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 241{ 242 243 switch (which) { 244 case PCIB_IVAR_DOMAIN: 245 *result = 0; 246 return (0); 247 case PCIB_IVAR_BUS: 248 *result = pcib_get_bus(dev); 249 return (0); 250 default: 251 return (ENOENT); 252 } 253} 254 255#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 256static struct resource * 257qpi_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 258 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 259{ 260 261 if (type == PCI_RES_BUS) 262 return (pci_domain_alloc_bus(0, child, rid, start, end, count, 263 flags)); 264 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 265 count, flags)); 266} 267#endif 268 269static int 270qpi_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 271 uint32_t *data) 272{ 273 device_t bus; 274 275 bus = device_get_parent(pcib); 276 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data)); 277} 278 279static device_method_t qpi_pcib_methods[] = { 280 /* Device interface */ 281 DEVMETHOD(device_probe, qpi_pcib_probe), 282 DEVMETHOD(device_attach, qpi_pcib_attach), 283 DEVMETHOD(device_shutdown, bus_generic_shutdown), 284 DEVMETHOD(device_suspend, bus_generic_suspend), 285 DEVMETHOD(device_resume, bus_generic_resume), 286 287 /* Bus interface */ 288 DEVMETHOD(bus_read_ivar, qpi_pcib_read_ivar), 289#if defined(NEW_PCIB) && defined(PCI_RES_BUS) 290 DEVMETHOD(bus_alloc_resource, qpi_pcib_alloc_resource), 291 DEVMETHOD(bus_adjust_resource, legacy_pcib_adjust_resource), 292 DEVMETHOD(bus_release_resource, legacy_pcib_release_resource), 293#else 294 DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource), 295 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 296#endif 297 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 298 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 299 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 300 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 301 302 /* pcib interface */ 303 DEVMETHOD(pcib_maxslots, pcib_maxslots), 304 DEVMETHOD(pcib_read_config, legacy_pcib_read_config), 305 DEVMETHOD(pcib_write_config, legacy_pcib_write_config), 306 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi), 307 DEVMETHOD(pcib_release_msi, pcib_release_msi), 308 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix), 309 DEVMETHOD(pcib_release_msix, pcib_release_msix), 310 DEVMETHOD(pcib_map_msi, qpi_pcib_map_msi), 311 312 DEVMETHOD_END 313}; 314 315static devclass_t qpi_pcib_devclass; 316 317DEFINE_CLASS_0(pcib, qpi_pcib_driver, qpi_pcib_methods, 0); 318DRIVER_MODULE(pcib, qpi, qpi_pcib_driver, qpi_pcib_devclass, 0, 0); 319