1/*- 2 * Copyright (c) 1995 Bruce D. Evans. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32#ifndef _X86_X86_VAR_H_ 33#define _X86_X86_VAR_H_ 34 35/* 36 * Miscellaneous machine-dependent declarations. 37 */ 38 39extern long Maxmem; 40extern u_int basemem; 41extern int busdma_swi_pending; 42extern u_int cpu_exthigh; 43extern u_int cpu_feature; 44extern u_int cpu_feature2; 45extern u_int amd_feature; 46extern u_int amd_feature2; 47extern u_int amd_rascap; 48extern u_int amd_pminfo; 49extern u_int amd_extended_feature_extensions; 50extern u_int via_feature_rng; 51extern u_int via_feature_xcrypt; 52extern u_int cpu_clflush_line_size; 53extern u_int cpu_stdext_feature; 54extern u_int cpu_stdext_feature2; 55extern u_int cpu_stdext_feature3; 56extern uint64_t cpu_ia32_arch_caps; 57extern u_int cpu_fxsr; 58extern u_int cpu_high; 59extern u_int cpu_id; 60extern u_int cpu_max_ext_state_size; 61extern u_int cpu_mxcsr_mask; 62extern u_int cpu_procinfo; 63extern u_int cpu_procinfo2; 64extern char cpu_vendor[]; 65extern u_int cpu_vendor_id; 66extern u_int cpu_mon_mwait_flags; 67extern u_int cpu_mon_min_size; 68extern u_int cpu_mon_max_size; 69extern u_int cpu_maxphyaddr; 70extern u_int hv_high; 71extern char hv_vendor[]; 72extern char kstack[]; 73extern char sigcode[]; 74extern int szsigcode; 75extern int vm_page_dump_size; 76extern int workaround_erratum383; 77extern int _udatasel; 78extern int _ucodesel; 79extern int _ucode32sel; 80extern int _ufssel; 81extern int _ugssel; 82extern int use_xsave; 83extern uint64_t xsave_mask; 84extern u_int max_apic_id; 85extern int pti; 86extern int hw_ibrs_ibpb_active; 87extern int hw_mds_disable; 88extern int hw_ssb_active; 89extern int x86_taa_enable; 90extern int cpu_flush_rsb_ctxsw; 91extern int x86_rngds_mitg_enable; 92extern int cpu_amdc1e_bug; 93 94struct pcb; 95struct thread; 96struct reg; 97struct fpreg; 98struct dbreg; 99struct dumperinfo; 100struct trapframe; 101 102/* 103 * The interface type of the interrupt handler entry point cannot be 104 * expressed in C. Use simplest non-variadic function type as an 105 * approximation. 106 */ 107typedef void alias_for_inthand_t(void); 108 109/* 110 * Returns the maximum physical address that can be used with the 111 * current system. 112 */ 113static __inline vm_paddr_t 114cpu_getmaxphyaddr(void) 115{ 116#if defined(__i386__) && !defined(PAE) 117 return (0xffffffff); 118#else 119 return ((1ULL << cpu_maxphyaddr) - 1); 120#endif 121} 122 123bool acpi_get_fadt_bootflags(uint16_t *flagsp); 124void *alloc_fpusave(int flags); 125void busdma_swi(void); 126u_int cpu_auxmsr(void); 127bool cpu_mwait_usable(void); 128void cpu_probe_amdc1e(void); 129void cpu_setregs(void); 130void x86_clear_dbregs(struct pcb *pcb); 131bool disable_wp(void); 132void restore_wp(bool old_wp); 133void dump_add_page(vm_paddr_t); 134void dump_drop_page(vm_paddr_t); 135void finishidentcpu(void); 136void identify_cpu1(void); 137void identify_cpu2(void); 138void identify_cpu_fixup_bsp(void); 139void identify_hypervisor(void); 140void initializecpu(void); 141void initializecpucache(void); 142bool fix_cpuid(void); 143void fillw(int /*u_short*/ pat, void *base, size_t cnt); 144int is_physical_memory(vm_paddr_t addr); 145int isa_nmi(int cd); 146void handle_ibrs_entry(void); 147void handle_ibrs_exit(void); 148void hw_ibrs_recalculate(bool all_cpus); 149void hw_mds_recalculate(void); 150void hw_ssb_recalculate(bool all_cpus); 151void x86_taa_recalculate(void); 152void x86_rngds_mitg_recalculate(bool all_cpus); 153void nmi_call_kdb(u_int cpu, u_int type, struct trapframe *frame); 154void nmi_call_kdb_smp(u_int type, struct trapframe *frame); 155void nmi_handle_intr(u_int type, struct trapframe *frame); 156void pagecopy(void *from, void *to); 157void printcpuinfo(void); 158int pti_get_default(void); 159int user_dbreg_trap(register_t dr6); 160int minidumpsys(struct dumperinfo *); 161struct pcb *get_pcb_td(struct thread *td); 162 163#define MSR_OP_ANDNOT 0x00000001 164#define MSR_OP_OR 0x00000002 165#define MSR_OP_WRITE 0x00000003 166#define MSR_OP_LOCAL 0x10000000 167#define MSR_OP_SCHED 0x20000000 168#define MSR_OP_RENDEZVOUS 0x30000000 169void x86_msr_op(u_int msr, u_int op, uint64_t arg1); 170 171#endif 172