1/*- 2 * Copyright (c) 2015-2017 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * Portions of this software were developed by SRI International and the 6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract 7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Portions of this software were developed by the University of Cambridge 10 * Computer Laboratory as part of the CTSRD Project, with support from the 11 * UK Higher Education Innovation Fund (HEIF). 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $FreeBSD$ 35 */ 36 37#ifndef _MACHINE_RISCVREG_H_ 38#define _MACHINE_RISCVREG_H_ 39 40#define EXCP_MASK (~EXCP_INTR) 41#define EXCP_MISALIGNED_FETCH 0 42#define EXCP_FAULT_FETCH 1 43#define EXCP_ILLEGAL_INSTRUCTION 2 44#define EXCP_BREAKPOINT 3 45#define EXCP_MISALIGNED_LOAD 4 46#define EXCP_FAULT_LOAD 5 47#define EXCP_MISALIGNED_STORE 6 48#define EXCP_FAULT_STORE 7 49#define EXCP_USER_ECALL 8 50#define EXCP_SUPERVISOR_ECALL 9 51#define EXCP_HYPERVISOR_ECALL 10 52#define EXCP_MACHINE_ECALL 11 53#define EXCP_INST_PAGE_FAULT 12 54#define EXCP_LOAD_PAGE_FAULT 13 55#define EXCP_STORE_PAGE_FAULT 15 56#define EXCP_INTR (1ul << 63) 57 58#define SSTATUS_UIE (1 << 0) 59#define SSTATUS_SIE (1 << 1) 60#define SSTATUS_UPIE (1 << 4) 61#define SSTATUS_SPIE (1 << 5) 62#define SSTATUS_SPIE_SHIFT 5 63#define SSTATUS_SPP (1 << 8) 64#define SSTATUS_SPP_SHIFT 8 65#define SSTATUS_FS_SHIFT 13 66#define SSTATUS_FS_OFF (0x0 << SSTATUS_FS_SHIFT) 67#define SSTATUS_FS_INITIAL (0x1 << SSTATUS_FS_SHIFT) 68#define SSTATUS_FS_CLEAN (0x2 << SSTATUS_FS_SHIFT) 69#define SSTATUS_FS_DIRTY (0x3 << SSTATUS_FS_SHIFT) 70#define SSTATUS_FS_MASK (0x3 << SSTATUS_FS_SHIFT) 71#define SSTATUS_XS_SHIFT 15 72#define SSTATUS_XS_MASK (0x3 << SSTATUS_XS_SHIFT) 73#define SSTATUS_SUM (1 << 18) 74#if __riscv_xlen == 64 75#define SSTATUS_SD (1ul << 63) 76#else 77#define SSTATUS_SD (1 << 31) 78#endif 79 80#define MSTATUS_UIE (1 << 0) 81#define MSTATUS_SIE (1 << 1) 82#define MSTATUS_HIE (1 << 2) 83#define MSTATUS_MIE (1 << 3) 84#define MSTATUS_UPIE (1 << 4) 85#define MSTATUS_SPIE (1 << 5) 86#define MSTATUS_SPIE_SHIFT 5 87#define MSTATUS_HPIE (1 << 6) 88#define MSTATUS_MPIE (1 << 7) 89#define MSTATUS_MPIE_SHIFT 7 90#define MSTATUS_SPP (1 << 8) 91#define MSTATUS_SPP_SHIFT 8 92#define MSTATUS_HPP_MASK 0x3 93#define MSTATUS_HPP_SHIFT 9 94#define MSTATUS_MPP_MASK 0x3 95#define MSTATUS_MPP_SHIFT 11 96#define MSTATUS_FS_MASK 0x3 97#define MSTATUS_FS_SHIFT 13 98#define MSTATUS_XS_MASK 0x3 99#define MSTATUS_XS_SHIFT 15 100#define MSTATUS_MPRV (1 << 17) 101#define MSTATUS_PUM (1 << 18) 102#define MSTATUS_VM_MASK 0x1f 103#define MSTATUS_VM_SHIFT 24 104#define MSTATUS_VM_MBARE 0 105#define MSTATUS_VM_MBB 1 106#define MSTATUS_VM_MBBID 2 107#define MSTATUS_VM_SV32 8 108#define MSTATUS_VM_SV39 9 109#define MSTATUS_VM_SV48 10 110#define MSTATUS_VM_SV57 11 111#define MSTATUS_VM_SV64 12 112#if __riscv_xlen == 64 113#define MSTATUS_SD (1ul << 63) 114#else 115#define MSTATUS_SD (1 << 31) 116#endif 117 118#define MSTATUS_PRV_U 0 /* user */ 119#define MSTATUS_PRV_S 1 /* supervisor */ 120#define MSTATUS_PRV_H 2 /* hypervisor */ 121#define MSTATUS_PRV_M 3 /* machine */ 122 123#define MIE_USIE (1 << 0) 124#define MIE_SSIE (1 << 1) 125#define MIE_HSIE (1 << 2) 126#define MIE_MSIE (1 << 3) 127#define MIE_UTIE (1 << 4) 128#define MIE_STIE (1 << 5) 129#define MIE_HTIE (1 << 6) 130#define MIE_MTIE (1 << 7) 131 132#define MIP_USIP (1 << 0) 133#define MIP_SSIP (1 << 1) 134#define MIP_HSIP (1 << 2) 135#define MIP_MSIP (1 << 3) 136#define MIP_UTIP (1 << 4) 137#define MIP_STIP (1 << 5) 138#define MIP_HTIP (1 << 6) 139#define MIP_MTIP (1 << 7) 140 141#define SIE_USIE (1 << 0) 142#define SIE_SSIE (1 << 1) 143#define SIE_UTIE (1 << 4) 144#define SIE_STIE (1 << 5) 145#define SIE_UEIE (1 << 8) 146#define SIE_SEIE (1 << 9) 147 148#define MIP_SEIP (1 << 9) 149 150/* Note: sip register has no SIP_STIP bit in Spike simulator */ 151#define SIP_SSIP (1 << 1) 152#define SIP_STIP (1 << 5) 153 154#define SATP_PPN_S 0 155#define SATP_PPN_M (0xfffffffffff << SATP_PPN_S) 156#define SATP_ASID_S 44 157#define SATP_ASID_M (0xffff << SATP_ASID_S) 158#define SATP_MODE_S 60 159#define SATP_MODE_M (0xf << SATP_MODE_S) 160#define SATP_MODE_SV39 (8ULL << SATP_MODE_S) 161#define SATP_MODE_SV48 (9ULL << SATP_MODE_S) 162 163#define XLEN __riscv_xlen 164#define XLEN_BYTES (XLEN / 8) 165#define INSN_SIZE 4 166#define INSN_C_SIZE 2 167 168#define X_RA 1 169#define X_SP 2 170#define X_GP 3 171#define X_TP 4 172#define X_T0 5 173#define X_T1 6 174#define X_T2 7 175#define X_T3 28 176 177#define RD_SHIFT 7 178#define RD_MASK (0x1f << RD_SHIFT) 179#define RS1_SHIFT 15 180#define RS1_MASK (0x1f << RS1_SHIFT) 181#define RS1_SP (X_SP << RS1_SHIFT) 182#define RS2_SHIFT 20 183#define RS2_MASK (0x1f << RS2_SHIFT) 184#define RS2_RA (X_RA << RS2_SHIFT) 185#define IMM_SHIFT 20 186#define IMM_MASK (0xfff << IMM_SHIFT) 187 188#define RS2_C_SHIFT 2 189#define RS2_C_MASK (0x1f << RS2_C_SHIFT) 190#define RS2_C_RA (X_RA << RS2_C_SHIFT) 191 192#define CSR_ZIMM(val) \ 193 (__builtin_constant_p(val) && ((u_long)(val) < 32)) 194 195#define csr_swap(csr, val) \ 196({ if (CSR_ZIMM(val)) \ 197 __asm __volatile("csrrwi %0, " #csr ", %1" \ 198 : "=r" (val) : "i" (val)); \ 199 else \ 200 __asm __volatile("csrrw %0, " #csr ", %1" \ 201 : "=r" (val) : "r" (val)); \ 202 val; \ 203}) 204 205#define csr_write(csr, val) \ 206({ if (CSR_ZIMM(val)) \ 207 __asm __volatile("csrwi " #csr ", %0" :: "i" (val)); \ 208 else \ 209 __asm __volatile("csrw " #csr ", %0" :: "r" (val)); \ 210}) 211 212#define csr_set(csr, val) \ 213({ if (CSR_ZIMM(val)) \ 214 __asm __volatile("csrsi " #csr ", %0" :: "i" (val)); \ 215 else \ 216 __asm __volatile("csrs " #csr ", %0" :: "r" (val)); \ 217}) 218 219#define csr_clear(csr, val) \ 220({ if (CSR_ZIMM(val)) \ 221 __asm __volatile("csrci " #csr ", %0" :: "i" (val)); \ 222 else \ 223 __asm __volatile("csrc " #csr ", %0" :: "r" (val)); \ 224}) 225 226#define csr_read(csr) \ 227({ u_long val; \ 228 __asm __volatile("csrr %0, " #csr : "=r" (val)); \ 229 val; \ 230}) 231 232#if __riscv_xlen == 32 233#define csr_read64(csr) \ 234({ uint64_t val; \ 235 uint32_t high, low; \ 236 __asm __volatile("1: " \ 237 "csrr t0, " #csr "h\n" \ 238 "csrr %0, " #csr "\n" \ 239 "csrr %1, " #csr "h\n" \ 240 "bne t0, %1, 1b" \ 241 : "=r" (low), "=r" (high) \ 242 : \ 243 : "t0"); \ 244 val = (low | ((uint64_t)high << 32)); \ 245 val; \ 246}) 247#else 248#define csr_read64(csr) ((uint64_t)csr_read(csr)) 249#endif 250 251#endif /* !_MACHINE_RISCVREG_H_ */ 252