1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2001 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $NetBSD: spr.h,v 1.25 2002/08/14 15:38:40 matt Exp $ 29 * $FreeBSD$ 30 */ 31#ifndef _POWERPC_SPR_H_ 32#define _POWERPC_SPR_H_ 33 34#ifndef _LOCORE 35#define mtspr(reg, val) \ 36 __asm __volatile("mtspr %0,%1" : : "K"(reg), "r"(val)) 37#define mfspr(reg) \ 38 ( { register_t val; \ 39 __asm __volatile("mfspr %0,%1" : "=r"(val) : "K"(reg)); \ 40 val; } ) 41 42 43#ifndef __powerpc64__ 44 45/* The following routines allow manipulation of the full 64-bit width 46 * of SPRs on 64 bit CPUs in bridge mode */ 47 48#define mtspr64(reg,valhi,vallo,scratch) \ 49 __asm __volatile(" \ 50 mfmsr %0; \ 51 insrdi %0,%5,1,0; \ 52 mtmsrd %0; \ 53 isync; \ 54 \ 55 sld %1,%1,%4; \ 56 or %1,%1,%2; \ 57 mtspr %3,%1; \ 58 srd %1,%1,%4; \ 59 \ 60 clrldi %0,%0,1; \ 61 mtmsrd %0; \ 62 isync;" \ 63 : "=r"(scratch), "=r"(valhi) : "r"(vallo), "K"(reg), "r"(32), "r"(1)) 64 65#define mfspr64upper(reg,scratch) \ 66 ( { register_t val; \ 67 __asm __volatile(" \ 68 mfmsr %0; \ 69 insrdi %0,%4,1,0; \ 70 mtmsrd %0; \ 71 isync; \ 72 \ 73 mfspr %1,%2; \ 74 srd %1,%1,%3; \ 75 \ 76 clrldi %0,%0,1; \ 77 mtmsrd %0; \ 78 isync;" \ 79 : "=r"(scratch), "=r"(val) : "K"(reg), "r"(32), "r"(1)); \ 80 val; } ) 81 82#endif 83 84#endif /* _LOCORE */ 85 86/* 87 * Special Purpose Register declarations. 88 * 89 * The first column in the comments indicates which PowerPC 90 * architectures the SPR is valid on - 4 for 4xx series, 91 * 6 for 6xx/7xx series and 8 for 8xx and 8xxx series. 92 */ 93 94#define SPR_MQ 0x000 /* .6. 601 MQ register */ 95#define SPR_XER 0x001 /* 468 Fixed Point Exception Register */ 96#define SPR_RTCU_R 0x004 /* .6. 601 RTC Upper - Read */ 97#define SPR_RTCL_R 0x005 /* .6. 601 RTC Lower - Read */ 98#define SPR_LR 0x008 /* 468 Link Register */ 99#define SPR_CTR 0x009 /* 468 Count Register */ 100#define SPR_DSCR 0x011 /* Data Stream Control Register */ 101#define SPR_DSISR 0x012 /* .68 DSI exception source */ 102#define DSISR_DIRECT 0x80000000 /* Direct-store error exception */ 103#define DSISR_NOTFOUND 0x40000000 /* Translation not found */ 104#define DSISR_PROTECT 0x08000000 /* Memory access not permitted */ 105#define DSISR_INVRX 0x04000000 /* Reserve-indexed insn direct-store access */ 106#define DSISR_STORE 0x02000000 /* Store operation */ 107#define DSISR_DABR 0x00400000 /* DABR match */ 108#define DSISR_SEGMENT 0x00200000 /* XXX; not in 6xx PEM */ 109#define DSISR_EAR 0x00100000 /* eciwx/ecowx && EAR[E] == 0 */ 110#define SPR_DAR 0x013 /* .68 Data Address Register */ 111#define SPR_RTCU_W 0x014 /* .6. 601 RTC Upper - Write */ 112#define SPR_RTCL_W 0x015 /* .6. 601 RTC Lower - Write */ 113#define SPR_DEC 0x016 /* .68 DECrementer register */ 114#define SPR_SDR1 0x019 /* .68 Page table base address register */ 115#define SPR_SRR0 0x01a /* 468 Save/Restore Register 0 */ 116#define SPR_SRR1 0x01b /* 468 Save/Restore Register 1 */ 117#define SRR1_ISI_PFAULT 0x40000000 /* ISI page not found */ 118#define SRR1_ISI_NOEXECUTE 0x10000000 /* Memory marked no-execute */ 119#define SRR1_ISI_PP 0x08000000 /* PP bits forbid access */ 120#define SPR_DECAR 0x036 /* ..8 Decrementer auto reload */ 121#define SPR_EIE 0x050 /* ..8 Exception Interrupt ??? */ 122#define SPR_EID 0x051 /* ..8 Exception Interrupt ??? */ 123#define SPR_NRI 0x052 /* ..8 Exception Interrupt ??? */ 124#define SPR_FSCR 0x099 /* Facility Status and Control Register */ 125#define FSCR_IC_MASK 0xFF00000000000000ULL /* FSCR[0:7] is Interrupt Cause */ 126#define FSCR_IC_FP 0x0000000000000000ULL /* FP unavailable */ 127#define FSCR_IC_VSX 0x0100000000000000ULL /* VSX unavailable */ 128#define FSCR_IC_DSCR 0x0200000000000000ULL /* Access to the DSCR at SPRs 3 or 17 */ 129#define FSCR_IC_PM 0x0300000000000000ULL /* Read or write access of a Performance Monitor SPR in group A */ 130#define FSCR_IC_BHRB 0x0400000000000000ULL /* Execution of a BHRB Instruction */ 131#define FSCR_IC_HTM 0x0500000000000000ULL /* Access to a Transactional Memory */ 132/* Reserved 0x0600000000000000ULL */ 133#define FSCR_IC_EBB 0x0700000000000000ULL /* Access to Event-Based Branch */ 134#define FSCR_IC_TAR 0x0800000000000000ULL /* Access to Target Address Register */ 135#define FSCR_IC_STOP 0x0900000000000000ULL /* Access to the 'stop' instruction in privileged non-hypervisor state */ 136#define FSCR_IC_MSG 0x0A00000000000000ULL /* Access to 'msgsndp' or 'msgclrp' instructions */ 137#define FSCR_IC_SCV 0x0C00000000000000ULL /* Execution of a 'scv' instruction */ 138#define SPR_USPRG0 0x100 /* 4.. User SPR General 0 */ 139#define SPR_VRSAVE 0x100 /* .6. AltiVec VRSAVE */ 140#define SPR_SPRG0 0x110 /* 468 SPR General 0 */ 141#define SPR_SPRG1 0x111 /* 468 SPR General 1 */ 142#define SPR_SPRG2 0x112 /* 468 SPR General 2 */ 143#define SPR_SPRG3 0x113 /* 468 SPR General 3 */ 144#define SPR_SPRG4 0x114 /* 4.. SPR General 4 */ 145#define SPR_SPRG5 0x115 /* 4.. SPR General 5 */ 146#define SPR_SPRG6 0x116 /* 4.. SPR General 6 */ 147#define SPR_SPRG7 0x117 /* 4.. SPR General 7 */ 148#define SPR_SCOMC 0x114 /* ... SCOM Address Register (970) */ 149#define SPR_SCOMD 0x115 /* ... SCOM Data Register (970) */ 150#define SPR_ASR 0x118 /* ... Address Space Register (PPC64) */ 151#define SPR_EAR 0x11a /* .68 External Access Register */ 152#define SPR_PVR 0x11f /* 468 Processor Version Register */ 153#define MPC601 0x0001 154#define MPC603 0x0003 155#define MPC604 0x0004 156#define MPC602 0x0005 157#define MPC603e 0x0006 158#define MPC603ev 0x0007 159#define MPC750 0x0008 160#define MPC750CL 0x7000 /* Nintendo Wii's Broadway */ 161#define MPC604ev 0x0009 162#define MPC7400 0x000c 163#define MPC620 0x0014 164#define IBM403 0x0020 165#define IBM401A1 0x0021 166#define IBM401B2 0x0022 167#define IBM401C2 0x0023 168#define IBM401D2 0x0024 169#define IBM401E2 0x0025 170#define IBM401F2 0x0026 171#define IBM401G2 0x0027 172#define IBMRS64II 0x0033 173#define IBMRS64III 0x0034 174#define IBMPOWER4 0x0035 175#define IBMRS64III_2 0x0036 176#define IBMRS64IV 0x0037 177#define IBMPOWER4PLUS 0x0038 178#define IBM970 0x0039 179#define IBMPOWER5 0x003a 180#define IBMPOWER5PLUS 0x003b 181#define IBM970FX 0x003c 182#define IBMPOWER6 0x003e 183#define IBMPOWER7 0x003f 184#define IBMPOWER3 0x0040 185#define IBMPOWER3PLUS 0x0041 186#define IBM970MP 0x0044 187#define IBM970GX 0x0045 188#define IBMPOWERPCA2 0x0049 189#define IBMPOWER7PLUS 0x004a 190#define IBMPOWER8E 0x004b 191#define IBMPOWER8NVL 0x004c 192#define IBMPOWER8 0x004d 193#define IBMPOWER9 0x004e 194#define MPC860 0x0050 195#define IBMCELLBE 0x0070 196#define MPC8240 0x0081 197#define PA6T 0x0090 198#define IBM405GP 0x4011 199#define IBM405L 0x4161 200#define IBM750FX 0x7000 201#define MPC745X_P(v) ((v & 0xFFF8) == 0x8000) 202#define MPC7450 0x8000 203#define MPC7455 0x8001 204#define MPC7457 0x8002 205#define MPC7447A 0x8003 206#define MPC7448 0x8004 207#define MPC7410 0x800c 208#define MPC8245 0x8081 209#define FSL_E500v1 0x8020 210#define FSL_E500v2 0x8021 211#define FSL_E500mc 0x8023 212#define FSL_E5500 0x8024 213#define FSL_E6500 0x8040 214#define FSL_E300C1 0x8083 215#define FSL_E300C2 0x8084 216#define FSL_E300C3 0x8085 217#define FSL_E300C4 0x8086 218 219#define LPCR_PECE_WAKESET (LPCR_PECE_EXT | LPCR_PECE_DECR | LPCR_PECE_ME) 220 221#define SPR_EPCR 0x133 222#define EPCR_EXTGS 0x80000000 223#define EPCR_DTLBGS 0x40000000 224#define EPCR_ITLBGS 0x20000000 225#define EPCR_DSIGS 0x10000000 226#define EPCR_ISIGS 0x08000000 227#define EPCR_DUVGS 0x04000000 228#define EPCR_ICM 0x02000000 229#define EPCR_GICMGS 0x01000000 230#define EPCR_DGTMI 0x00800000 231#define EPCR_DMIUH 0x00400000 232#define EPCR_PMGS 0x00200000 233 234#define SPR_HSRR0 0x13a 235#define SPR_HSRR1 0x13b 236#define SPR_LPCR 0x13e /* Logical Partitioning Control */ 237#define LPCR_LPES 0x008 /* Bit 60 */ 238#define LPCR_HVICE 0x002 /* Hypervisor Virtualization Interrupt (Arch 3.0) */ 239#define LPCR_PECE_DRBL (1ULL << 16) /* Directed Privileged Doorbell */ 240#define LPCR_PECE_HDRBL (1ULL << 15) /* Directed Hypervisor Doorbell */ 241#define LPCR_PECE_EXT (1ULL << 14) /* External exceptions */ 242#define LPCR_PECE_DECR (1ULL << 13) /* Decrementer exceptions */ 243#define LPCR_PECE_ME (1ULL << 12) /* Machine Check and Hypervisor */ 244 /* Maintenance exceptions */ 245#define SPR_LPID 0x13f /* Logical Partitioning Control */ 246#define SPR_HMER 0x150 /* Hypervisor Maintenance Exception Register */ 247#define SPR_HMEER 0x151 /* Hypervisor Maintenance Exception Enable Register */ 248 249#define SPR_PTCR 0x1d0 /* Partition Table Control Register */ 250#define SPR_SPEFSCR 0x200 /* ..8 Signal Processing Engine FSCR. */ 251#define SPEFSCR_SOVH 0x80000000 252#define SPEFSCR_OVH 0x40000000 253#define SPEFSCR_FGH 0x20000000 254#define SPEFSCR_FXH 0x10000000 255#define SPEFSCR_FINVH 0x08000000 256#define SPEFSCR_FDBZH 0x04000000 257#define SPEFSCR_FUNFH 0x02000000 258#define SPEFSCR_FOVFH 0x01000000 259#define SPEFSCR_FINXS 0x00200000 260#define SPEFSCR_FINVS 0x00100000 261#define SPEFSCR_FDBZS 0x00080000 262#define SPEFSCR_FUNFS 0x00040000 263#define SPEFSCR_FOVFS 0x00020000 264#define SPEFSCR_SOV 0x00008000 265#define SPEFSCR_OV 0x00004000 266#define SPEFSCR_FG 0x00002000 267#define SPEFSCR_FX 0x00001000 268#define SPEFSCR_FINV 0x00000800 269#define SPEFSCR_FDBZ 0x00000400 270#define SPEFSCR_FUNF 0x00000200 271#define SPEFSCR_FOVF 0x00000100 272#define SPEFSCR_FINXE 0x00000040 273#define SPEFSCR_FINVE 0x00000020 274#define SPEFSCR_FDBZE 0x00000010 275#define SPEFSCR_FUNFE 0x00000008 276#define SPEFSCR_FOVFE 0x00000004 277#define SPEFSCR_FRMC_M 0x00000003 278#define SPR_IBAT0U 0x210 /* .6. Instruction BAT Reg 0 Upper */ 279#define SPR_IBAT0L 0x211 /* .6. Instruction BAT Reg 0 Lower */ 280#define SPR_IBAT1U 0x212 /* .6. Instruction BAT Reg 1 Upper */ 281#define SPR_IBAT1L 0x213 /* .6. Instruction BAT Reg 1 Lower */ 282#define SPR_IBAT2U 0x214 /* .6. Instruction BAT Reg 2 Upper */ 283#define SPR_IBAT2L 0x215 /* .6. Instruction BAT Reg 2 Lower */ 284#define SPR_IBAT3U 0x216 /* .6. Instruction BAT Reg 3 Upper */ 285#define SPR_IBAT3L 0x217 /* .6. Instruction BAT Reg 3 Lower */ 286#define SPR_DBAT0U 0x218 /* .6. Data BAT Reg 0 Upper */ 287#define SPR_DBAT0L 0x219 /* .6. Data BAT Reg 0 Lower */ 288#define SPR_DBAT1U 0x21a /* .6. Data BAT Reg 1 Upper */ 289#define SPR_DBAT1L 0x21b /* .6. Data BAT Reg 1 Lower */ 290#define SPR_DBAT2U 0x21c /* .6. Data BAT Reg 2 Upper */ 291#define SPR_DBAT2L 0x21d /* .6. Data BAT Reg 2 Lower */ 292#define SPR_DBAT3U 0x21e /* .6. Data BAT Reg 3 Upper */ 293#define SPR_DBAT3L 0x21f /* .6. Data BAT Reg 3 Lower */ 294#define SPR_IC_CST 0x230 /* ..8 Instruction Cache CSR */ 295#define IC_CST_IEN 0x80000000 /* I cache is ENabled (RO) */ 296#define IC_CST_CMD_INVALL 0x0c000000 /* I cache invalidate all */ 297#define IC_CST_CMD_UNLOCKALL 0x0a000000 /* I cache unlock all */ 298#define IC_CST_CMD_UNLOCK 0x08000000 /* I cache unlock block */ 299#define IC_CST_CMD_LOADLOCK 0x06000000 /* I cache load & lock block */ 300#define IC_CST_CMD_DISABLE 0x04000000 /* I cache disable */ 301#define IC_CST_CMD_ENABLE 0x02000000 /* I cache enable */ 302#define IC_CST_CCER1 0x00200000 /* I cache error type 1 (RO) */ 303#define IC_CST_CCER2 0x00100000 /* I cache error type 2 (RO) */ 304#define IC_CST_CCER3 0x00080000 /* I cache error type 3 (RO) */ 305#define SPR_IBAT4U 0x230 /* .6. Instruction BAT Reg 4 Upper */ 306#define SPR_IC_ADR 0x231 /* ..8 Instruction Cache Address */ 307#define SPR_IBAT4L 0x231 /* .6. Instruction BAT Reg 4 Lower */ 308#define SPR_IC_DAT 0x232 /* ..8 Instruction Cache Data */ 309#define SPR_IBAT5U 0x232 /* .6. Instruction BAT Reg 5 Upper */ 310#define SPR_IBAT5L 0x233 /* .6. Instruction BAT Reg 5 Lower */ 311#define SPR_IBAT6U 0x234 /* .6. Instruction BAT Reg 6 Upper */ 312#define SPR_IBAT6L 0x235 /* .6. Instruction BAT Reg 6 Lower */ 313#define SPR_IBAT7U 0x236 /* .6. Instruction BAT Reg 7 Upper */ 314#define SPR_IBAT7L 0x237 /* .6. Instruction BAT Reg 7 Lower */ 315#define SPR_DC_CST 0x230 /* ..8 Data Cache CSR */ 316#define DC_CST_DEN 0x80000000 /* D cache ENabled (RO) */ 317#define DC_CST_DFWT 0x40000000 /* D cache Force Write-Thru (RO) */ 318#define DC_CST_LES 0x20000000 /* D cache Little Endian Swap (RO) */ 319#define DC_CST_CMD_FLUSH 0x0e000000 /* D cache invalidate all */ 320#define DC_CST_CMD_INVALL 0x0c000000 /* D cache invalidate all */ 321#define DC_CST_CMD_UNLOCKALL 0x0a000000 /* D cache unlock all */ 322#define DC_CST_CMD_UNLOCK 0x08000000 /* D cache unlock block */ 323#define DC_CST_CMD_CLRLESWAP 0x07000000 /* D cache clr little-endian swap */ 324#define DC_CST_CMD_LOADLOCK 0x06000000 /* D cache load & lock block */ 325#define DC_CST_CMD_SETLESWAP 0x05000000 /* D cache set little-endian swap */ 326#define DC_CST_CMD_DISABLE 0x04000000 /* D cache disable */ 327#define DC_CST_CMD_CLRFWT 0x03000000 /* D cache clear forced write-thru */ 328#define DC_CST_CMD_ENABLE 0x02000000 /* D cache enable */ 329#define DC_CST_CMD_SETFWT 0x01000000 /* D cache set forced write-thru */ 330#define DC_CST_CCER1 0x00200000 /* D cache error type 1 (RO) */ 331#define DC_CST_CCER2 0x00100000 /* D cache error type 2 (RO) */ 332#define DC_CST_CCER3 0x00080000 /* D cache error type 3 (RO) */ 333#define SPR_DBAT4U 0x238 /* .6. Data BAT Reg 4 Upper */ 334#define SPR_DC_ADR 0x231 /* ..8 Data Cache Address */ 335#define SPR_DBAT4L 0x239 /* .6. Data BAT Reg 4 Lower */ 336#define SPR_DC_DAT 0x232 /* ..8 Data Cache Data */ 337#define SPR_DBAT5U 0x23a /* .6. Data BAT Reg 5 Upper */ 338#define SPR_DBAT5L 0x23b /* .6. Data BAT Reg 5 Lower */ 339#define SPR_DBAT6U 0x23c /* .6. Data BAT Reg 6 Upper */ 340#define SPR_DBAT6L 0x23d /* .6. Data BAT Reg 6 Lower */ 341#define SPR_DBAT7U 0x23e /* .6. Data BAT Reg 7 Upper */ 342#define SPR_DBAT7L 0x23f /* .6. Data BAT Reg 7 Lower */ 343#define SPR_SPRG8 0x25c /* ..8 SPR General 8 */ 344#define SPR_MI_CTR 0x310 /* ..8 IMMU control */ 345#define Mx_CTR_GPM 0x80000000 /* Group Protection Mode */ 346#define Mx_CTR_PPM 0x40000000 /* Page Protection Mode */ 347#define Mx_CTR_CIDEF 0x20000000 /* Cache-Inhibit DEFault */ 348#define MD_CTR_WTDEF 0x20000000 /* Write-Through DEFault */ 349#define Mx_CTR_RSV4 0x08000000 /* Reserve 4 TLB entries */ 350#define MD_CTR_TWAM 0x04000000 /* TableWalk Assist Mode */ 351#define Mx_CTR_PPCS 0x02000000 /* Priv/user state compare mode */ 352#define Mx_CTR_TLB_INDX 0x000001f0 /* TLB index mask */ 353#define Mx_CTR_TLB_INDX_BITPOS 8 /* TLB index shift */ 354#define SPR_MI_AP 0x312 /* ..8 IMMU access protection */ 355#define Mx_GP_SUPER(n) (0 << (2*(15-(n)))) /* access is supervisor */ 356#define Mx_GP_PAGE (1 << (2*(15-(n)))) /* access is page protect */ 357#define Mx_GP_SWAPPED (2 << (2*(15-(n)))) /* access is swapped */ 358#define Mx_GP_USER (3 << (2*(15-(n)))) /* access is user */ 359#define SPR_MI_EPN 0x313 /* ..8 IMMU effective number */ 360#define Mx_EPN_EPN 0xfffff000 /* Effective Page Number mask */ 361#define Mx_EPN_EV 0x00000020 /* Entry Valid */ 362#define Mx_EPN_ASID 0x0000000f /* Address Space ID */ 363#define SPR_MI_TWC 0x315 /* ..8 IMMU tablewalk control */ 364#define MD_TWC_L2TB 0xfffff000 /* Level-2 Tablewalk Base */ 365#define Mx_TWC_APG 0x000001e0 /* Access Protection Group */ 366#define Mx_TWC_G 0x00000010 /* Guarded memory */ 367#define Mx_TWC_PS 0x0000000c /* Page Size (L1) */ 368#define MD_TWC_WT 0x00000002 /* Write-Through */ 369#define Mx_TWC_V 0x00000001 /* Entry Valid */ 370#define SPR_MI_RPN 0x316 /* ..8 IMMU real (phys) page number */ 371#define Mx_RPN_RPN 0xfffff000 /* Real Page Number */ 372#define Mx_RPN_PP 0x00000ff0 /* Page Protection */ 373#define Mx_RPN_SPS 0x00000008 /* Small Page Size */ 374#define Mx_RPN_SH 0x00000004 /* SHared page */ 375#define Mx_RPN_CI 0x00000002 /* Cache Inhibit */ 376#define Mx_RPN_V 0x00000001 /* Valid */ 377#define SPR_MD_CTR 0x318 /* ..8 DMMU control */ 378#define SPR_M_CASID 0x319 /* ..8 CASID */ 379#define M_CASID 0x0000000f /* Current AS Id */ 380#define SPR_MD_AP 0x31a /* ..8 DMMU access protection */ 381#define SPR_MD_EPN 0x31b /* ..8 DMMU effective number */ 382 383#define SPR_970MMCR0 0x31b /* ... Monitor Mode Control Register 0 (PPC 970) */ 384#define SPR_970MMCR0_PMC1SEL(x) ((x) << 8) /* PMC1 selector (970) */ 385#define SPR_970MMCR0_PMC2SEL(x) ((x) << 1) /* PMC2 selector (970) */ 386#define SPR_970MMCR1 0x31e /* ... Monitor Mode Control Register 1 (PPC 970) */ 387#define SPR_970MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ 388#define SPR_970MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ 389#define SPR_970MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ 390#define SPR_970MMCR1_PMC6SEL(x) (((x) & 0x1f) << 12) /* PMC 6 selector */ 391#define SPR_970MMCR1_PMC7SEL(x) (((x) & 0x1f) << 7) /* PMC 7 selector */ 392#define SPR_970MMCR1_PMC8SEL(x) (((x) & 0x1f) << 2) /* PMC 8 selector */ 393#define SPR_970MMCRA 0x312 /* ... Monitor Mode Control Register 2 (PPC 970) */ 394#define SPR_970PMC1 0x313 /* ... PMC 1 */ 395#define SPR_970PMC2 0x314 /* ... PMC 2 */ 396#define SPR_970PMC3 0x315 /* ... PMC 3 */ 397#define SPR_970PMC4 0x316 /* ... PMC 4 */ 398#define SPR_970PMC5 0x317 /* ... PMC 5 */ 399#define SPR_970PMC6 0x318 /* ... PMC 6 */ 400#define SPR_970PMC7 0x319 /* ... PMC 7 */ 401#define SPR_970PMC8 0x31a /* ... PMC 8 */ 402 403#define SPR_M_TWB 0x31c /* ..8 MMU tablewalk base */ 404#define M_TWB_L1TB 0xfffff000 /* level-1 translation base */ 405#define M_TWB_L1INDX 0x00000ffc /* level-1 index */ 406#define SPR_MD_TWC 0x31d /* ..8 DMMU tablewalk control */ 407#define SPR_MD_RPN 0x31e /* ..8 DMMU real (phys) page number */ 408#define SPR_MD_TW 0x31f /* ..8 MMU tablewalk scratch */ 409#define SPR_MI_CAM 0x330 /* ..8 IMMU CAM entry read */ 410#define SPR_MI_RAM0 0x331 /* ..8 IMMU RAM entry read reg 0 */ 411#define SPR_MI_RAM1 0x332 /* ..8 IMMU RAM entry read reg 1 */ 412#define SPR_MD_CAM 0x338 /* ..8 IMMU CAM entry read */ 413#define SPR_MD_RAM0 0x339 /* ..8 IMMU RAM entry read reg 0 */ 414#define SPR_MD_RAM1 0x33a /* ..8 IMMU RAM entry read reg 1 */ 415#define SPR_PSSCR 0x357 /* Processor Stop Status and Control Register (ISA 3.0) */ 416#define SPR_PMCR 0x374 /* Processor Management Control Register */ 417#define SPR_UMMCR2 0x3a0 /* .6. User Monitor Mode Control Register 2 */ 418#define SPR_UMMCR0 0x3a8 /* .6. User Monitor Mode Control Register 0 */ 419#define SPR_USIA 0x3ab /* .6. User Sampled Instruction Address */ 420#define SPR_UMMCR1 0x3ac /* .6. User Monitor Mode Control Register 1 */ 421#define SPR_ZPR 0x3b0 /* 4.. Zone Protection Register */ 422#define SPR_MMCR2 0x3b0 /* .6. Monitor Mode Control Register 2 */ 423#define SPR_MMCR2_THRESHMULT_32 0x80000000 /* Multiply MMCR0 threshold by 32 */ 424#define SPR_MMCR2_THRESHMULT_2 0x00000000 /* Multiply MMCR0 threshold by 2 */ 425#define SPR_PID 0x3b1 /* 4.. Process ID */ 426#define SPR_PMC5 0x3b1 /* .6. Performance Counter Register 5 */ 427#define SPR_PMC6 0x3b2 /* .6. Performance Counter Register 6 */ 428#define SPR_CCR0 0x3b3 /* 4.. Core Configuration Register 0 */ 429#define SPR_IAC3 0x3b4 /* 4.. Instruction Address Compare 3 */ 430#define SPR_IAC4 0x3b5 /* 4.. Instruction Address Compare 4 */ 431#define SPR_DVC1 0x3b6 /* 4.. Data Value Compare 1 */ 432#define SPR_DVC2 0x3b7 /* 4.. Data Value Compare 2 */ 433#define SPR_MMCR0 0x3b8 /* .6. Monitor Mode Control Register 0 */ 434#define SPR_MMCR0_FC 0x80000000 /* Freeze counters */ 435#define SPR_MMCR0_FCS 0x40000000 /* Freeze counters in supervisor mode */ 436#define SPR_MMCR0_FCP 0x20000000 /* Freeze counters in user mode */ 437#define SPR_MMCR0_FCM1 0x10000000 /* Freeze counters when mark=1 */ 438#define SPR_MMCR0_FCM0 0x08000000 /* Freeze counters when mark=0 */ 439#define SPR_MMCR0_PMXE 0x04000000 /* Enable PM interrupt */ 440#define SPR_MMCR0_FCECE 0x02000000 /* Freeze counters after event */ 441#define SPR_MMCR0_TBSEL_15 0x01800000 /* Count bit 15 of TBL */ 442#define SPR_MMCR0_TBSEL_19 0x01000000 /* Count bit 19 of TBL */ 443#define SPR_MMCR0_TBSEL_23 0x00800000 /* Count bit 23 of TBL */ 444#define SPR_MMCR0_TBSEL_31 0x00000000 /* Count bit 31 of TBL */ 445#define SPR_MMCR0_TBEE 0x00400000 /* Time-base event enable */ 446#define SPR_MMCRO_THRESHOLD(x) ((x) << 16) /* Threshold value */ 447#define SPR_MMCR0_PMC1CE 0x00008000 /* PMC1 condition enable */ 448#define SPR_MMCR0_PMCNCE 0x00004000 /* PMCn condition enable */ 449#define SPR_MMCR0_TRIGGER 0x00002000 /* Trigger */ 450#define SPR_MMCR0_PMC1SEL(x) (((x) & 0x3f) << 6) /* PMC1 selector */ 451#define SPR_MMCR0_PMC2SEL(x) (((x) & 0x3f) << 0) /* PMC2 selector */ 452#define SPR_SGR 0x3b9 /* 4.. Storage Guarded Register */ 453#define SPR_PMC1 0x3b9 /* .6. Performance Counter Register 1 */ 454#define SPR_DCWR 0x3ba /* 4.. Data Cache Write-through Register */ 455#define SPR_PMC2 0x3ba /* .6. Performance Counter Register 2 */ 456#define SPR_SLER 0x3bb /* 4.. Storage Little Endian Register */ 457#define SPR_SIA 0x3bb /* .6. Sampled Instruction Address */ 458#define SPR_MMCR1 0x3bc /* .6. Monitor Mode Control Register 2 */ 459#define SPR_MMCR1_PMC3SEL(x) (((x) & 0x1f) << 27) /* PMC 3 selector */ 460#define SPR_MMCR1_PMC4SEL(x) (((x) & 0x1f) << 22) /* PMC 4 selector */ 461#define SPR_MMCR1_PMC5SEL(x) (((x) & 0x1f) << 17) /* PMC 5 selector */ 462#define SPR_MMCR1_PMC6SEL(x) (((x) & 0x3f) << 11) /* PMC 6 selector */ 463 464#define SPR_SU0R 0x3bc /* 4.. Storage User-defined 0 Register */ 465#define SPR_PMC3 0x3bd /* .6. Performance Counter Register 3 */ 466#define SPR_PMC4 0x3be /* .6. Performance Counter Register 4 */ 467#define SPR_DMISS 0x3d0 /* .68 Data TLB Miss Address Register */ 468#define SPR_DCMP 0x3d1 /* .68 Data TLB Compare Register */ 469#define SPR_HASH1 0x3d2 /* .68 Primary Hash Address Register */ 470#define SPR_ICDBDR 0x3d3 /* 4.. Instruction Cache Debug Data Register */ 471#define SPR_HASH2 0x3d3 /* .68 Secondary Hash Address Register */ 472#define SPR_IMISS 0x3d4 /* .68 Instruction TLB Miss Address Register */ 473#define SPR_TLBMISS 0x3d4 /* .6. TLB Miss Address Register */ 474#define SPR_DEAR 0x3d5 /* 4.. Data Error Address Register */ 475#define SPR_ICMP 0x3d5 /* .68 Instruction TLB Compare Register */ 476#define SPR_PTEHI 0x3d5 /* .6. Instruction TLB Compare Register */ 477#define SPR_EVPR 0x3d6 /* 4.. Exception Vector Prefix Register */ 478#define SPR_RPA 0x3d6 /* .68 Required Physical Address Register */ 479#define SPR_PTELO 0x3d6 /* .6. Required Physical Address Register */ 480 481#define SPR_TSR 0x150 /* ..8 Timer Status Register */ 482#define SPR_TCR 0x154 /* ..8 Timer Control Register */ 483 484#define TSR_ENW 0x80000000 /* Enable Next Watchdog */ 485#define TSR_WIS 0x40000000 /* Watchdog Interrupt Status */ 486#define TSR_WRS_MASK 0x30000000 /* Watchdog Reset Status */ 487#define TSR_WRS_NONE 0x00000000 /* No watchdog reset has occurred */ 488#define TSR_WRS_CORE 0x10000000 /* Core reset was forced by the watchdog */ 489#define TSR_WRS_CHIP 0x20000000 /* Chip reset was forced by the watchdog */ 490#define TSR_WRS_SYSTEM 0x30000000 /* System reset was forced by the watchdog */ 491#define TSR_PIS 0x08000000 /* PIT Interrupt Status */ 492#define TSR_DIS 0x08000000 /* Decrementer Interrupt Status */ 493#define TSR_FIS 0x04000000 /* FIT Interrupt Status */ 494 495#define TCR_WP_MASK 0xc0000000 /* Watchdog Period mask */ 496#define TCR_WP_2_17 0x00000000 /* 2**17 clocks */ 497#define TCR_WP_2_21 0x40000000 /* 2**21 clocks */ 498#define TCR_WP_2_25 0x80000000 /* 2**25 clocks */ 499#define TCR_WP_2_29 0xc0000000 /* 2**29 clocks */ 500#define TCR_WRC_MASK 0x30000000 /* Watchdog Reset Control mask */ 501#define TCR_WRC_NONE 0x00000000 /* No watchdog reset */ 502#define TCR_WRC_CORE 0x10000000 /* Core reset */ 503#define TCR_WRC_CHIP 0x20000000 /* Chip reset */ 504#define TCR_WRC_SYSTEM 0x30000000 /* System reset */ 505#define TCR_WIE 0x08000000 /* Watchdog Interrupt Enable */ 506#define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ 507#define TCR_DIE 0x04000000 /* Pecrementer Interrupt Enable */ 508#define TCR_FP_MASK 0x03000000 /* FIT Period */ 509#define TCR_FP_2_9 0x00000000 /* 2**9 clocks */ 510#define TCR_FP_2_13 0x01000000 /* 2**13 clocks */ 511#define TCR_FP_2_17 0x02000000 /* 2**17 clocks */ 512#define TCR_FP_2_21 0x03000000 /* 2**21 clocks */ 513#define TCR_FIE 0x00800000 /* FIT Interrupt Enable */ 514#define TCR_ARE 0x00400000 /* Auto Reload Enable */ 515 516#define SPR_PIT 0x3db /* 4.. Programmable Interval Timer */ 517#define SPR_SRR2 0x3de /* 4.. Save/Restore Register 2 */ 518#define SPR_SRR3 0x3df /* 4.. Save/Restore Register 3 */ 519#define SPR_HID0 0x3f0 /* ..8 Hardware Implementation Register 0 */ 520#define SPR_HID1 0x3f1 /* ..8 Hardware Implementation Register 1 */ 521#define SPR_HID2 0x3f3 /* ..8 Hardware Implementation Register 2 */ 522#define SPR_HID4 0x3f4 /* ..8 Hardware Implementation Register 4 */ 523#define SPR_HID5 0x3f6 /* ..8 Hardware Implementation Register 5 */ 524#define SPR_HID6 0x3f9 /* ..8 Hardware Implementation Register 6 */ 525 526#define SPR_CELL_TSRL 0x380 /* ... Cell BE Thread Status Register */ 527#define SPR_CELL_TSCR 0x399 /* ... Cell BE Thread Switch Register */ 528 529#if defined(AIM) 530#define SPR_DBSR 0x3f0 /* 4.. Debug Status Register */ 531#define DBSR_IC 0x80000000 /* Instruction completion debug event */ 532#define DBSR_BT 0x40000000 /* Branch Taken debug event */ 533#define DBSR_EDE 0x20000000 /* Exception debug event */ 534#define DBSR_TIE 0x10000000 /* Trap Instruction debug event */ 535#define DBSR_UDE 0x08000000 /* Unconditional debug event */ 536#define DBSR_IA1 0x04000000 /* IAC1 debug event */ 537#define DBSR_IA2 0x02000000 /* IAC2 debug event */ 538#define DBSR_DR1 0x01000000 /* DAC1 Read debug event */ 539#define DBSR_DW1 0x00800000 /* DAC1 Write debug event */ 540#define DBSR_DR2 0x00400000 /* DAC2 Read debug event */ 541#define DBSR_DW2 0x00200000 /* DAC2 Write debug event */ 542#define DBSR_IDE 0x00100000 /* Imprecise debug event */ 543#define DBSR_IA3 0x00080000 /* IAC3 debug event */ 544#define DBSR_IA4 0x00040000 /* IAC4 debug event */ 545#define DBSR_MRR 0x00000300 /* Most recent reset */ 546#define SPR_DBCR0 0x3f2 /* 4.. Debug Control Register 0 */ 547#define SPR_DBCR1 0x3bd /* 4.. Debug Control Register 1 */ 548#define SPR_IAC1 0x3f4 /* 4.. Instruction Address Compare 1 */ 549#define SPR_IAC2 0x3f5 /* 4.. Instruction Address Compare 2 */ 550#define SPR_DAC1 0x3f6 /* 4.. Data Address Compare 1 */ 551#define SPR_DAC2 0x3f7 /* 4.. Data Address Compare 2 */ 552#define SPR_PIR 0x3ff /* .6. Processor Identification Register */ 553#elif defined(BOOKE) 554#define SPR_PIR 0x11e /* ..8 Processor Identification Register */ 555#define SPR_DBSR 0x130 /* ..8 Debug Status Register */ 556#define DBSR_IDE 0x80000000 /* Imprecise debug event. */ 557#define DBSR_UDE 0x40000000 /* Unconditional debug event. */ 558#define DBSR_MRR 0x30000000 /* Most recent Reset (mask). */ 559#define DBSR_ICMP 0x08000000 /* Instr. complete debug event. */ 560#define DBSR_BRT 0x04000000 /* Branch taken debug event. */ 561#define DBSR_IRPT 0x02000000 /* Interrupt taken debug event. */ 562#define DBSR_TRAP 0x01000000 /* Trap instr. debug event. */ 563#define DBSR_IAC1 0x00800000 /* Instr. address compare #1. */ 564#define DBSR_IAC2 0x00400000 /* Instr. address compare #2. */ 565#define DBSR_IAC3 0x00200000 /* Instr. address compare #3. */ 566#define DBSR_IAC4 0x00100000 /* Instr. address compare #4. */ 567#define DBSR_DAC1R 0x00080000 /* Data addr. read compare #1. */ 568#define DBSR_DAC1W 0x00040000 /* Data addr. write compare #1. */ 569#define DBSR_DAC2R 0x00020000 /* Data addr. read compare #2. */ 570#define DBSR_DAC2W 0x00010000 /* Data addr. write compare #2. */ 571#define DBSR_RET 0x00008000 /* Return debug event. */ 572#define SPR_DBCR0 0x134 /* ..8 Debug Control Register 0 */ 573#define SPR_DBCR1 0x135 /* ..8 Debug Control Register 1 */ 574#define SPR_IAC1 0x138 /* ..8 Instruction Address Compare 1 */ 575#define SPR_IAC2 0x139 /* ..8 Instruction Address Compare 2 */ 576#define SPR_DAC1 0x13c /* ..8 Data Address Compare 1 */ 577#define SPR_DAC2 0x13d /* ..8 Data Address Compare 2 */ 578#endif 579 580#define DBCR0_EDM 0x80000000 /* External Debug Mode */ 581#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ 582#define DBCR0_RST_MASK 0x30000000 /* ReSeT */ 583#define DBCR0_RST_NONE 0x00000000 /* No action */ 584#define DBCR0_RST_CORE 0x10000000 /* Core reset */ 585#define DBCR0_RST_CHIP 0x20000000 /* Chip reset */ 586#define DBCR0_RST_SYSTEM 0x30000000 /* System reset */ 587#define DBCR0_IC 0x08000000 /* Instruction Completion debug event */ 588#define DBCR0_BT 0x04000000 /* Branch Taken debug event */ 589#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ 590#define DBCR0_TDE 0x01000000 /* Trap Debug Event */ 591#define DBCR0_IA1 0x00800000 /* IAC (Instruction Address Compare) 1 debug event */ 592#define DBCR0_IA2 0x00400000 /* IAC 2 debug event */ 593#define DBCR0_IA12 0x00200000 /* Instruction Address Range Compare 1-2 */ 594#define DBCR0_IA12X 0x00100000 /* IA12 eXclusive */ 595#define DBCR0_IA3 0x00080000 /* IAC 3 debug event */ 596#define DBCR0_IA4 0x00040000 /* IAC 4 debug event */ 597#define DBCR0_IA34 0x00020000 /* Instruction Address Range Compare 3-4 */ 598#define DBCR0_IA34X 0x00010000 /* IA34 eXclusive */ 599#define DBCR0_IA12T 0x00008000 /* Instruction Address Range Compare 1-2 range Toggle */ 600#define DBCR0_IA34T 0x00004000 /* Instruction Address Range Compare 3-4 range Toggle */ 601#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ 602 603#define SPR_IABR 0x3f2 /* ..8 Instruction Address Breakpoint Register 0 */ 604#define SPR_DABR 0x3f5 /* .6. Data Address Breakpoint Register */ 605#define SPR_MSSCR0 0x3f6 /* .6. Memory SubSystem Control Register */ 606#define MSSCR0_SHDEN 0x80000000 /* 0: Shared-state enable */ 607#define MSSCR0_SHDPEN3 0x40000000 /* 1: ~SHD[01] signal enable in MEI mode */ 608#define MSSCR0_L1INTVEN 0x38000000 /* 2-4: L1 data cache ~HIT intervention enable */ 609#define MSSCR0_L2INTVEN 0x07000000 /* 5-7: L2 data cache ~HIT intervention enable*/ 610#define MSSCR0_DL1HWF 0x00800000 /* 8: L1 data cache hardware flush */ 611#define MSSCR0_MBO 0x00400000 /* 9: must be one */ 612#define MSSCR0_EMODE 0x00200000 /* 10: MPX bus mode (read-only) */ 613#define MSSCR0_ABD 0x00100000 /* 11: address bus driven (read-only) */ 614#define MSSCR0_MBZ 0x000fffff /* 12-31: must be zero */ 615#define MSSCR0_L2PFE 0x00000003 /* 30-31: L2 prefetch enable */ 616#define SPR_MSSSR0 0x3f7 /* .6. Memory Subsystem Status Register (MPC745x) */ 617#define MSSSR0_L2TAG 0x00040000 /* 13: L2 tag parity error */ 618#define MSSSR0_L2DAT 0x00020000 /* 14: L2 data parity error */ 619#define MSSSR0_L3TAG 0x00010000 /* 15: L3 tag parity error */ 620#define MSSSR0_L3DAT 0x00008000 /* 16: L3 data parity error */ 621#define MSSSR0_APE 0x00004000 /* 17: Address parity error */ 622#define MSSSR0_DPE 0x00002000 /* 18: Data parity error */ 623#define MSSSR0_TEA 0x00001000 /* 19: Bus transfer error acknowledge */ 624#define SPR_LDSTCR 0x3f8 /* .6. Load/Store Control Register */ 625#define SPR_L2PM 0x3f8 /* .6. L2 Private Memory Control Register */ 626#define SPR_L2CR 0x3f9 /* .6. L2 Control Register */ 627#define L2CR_L2E 0x80000000 /* 0: L2 enable */ 628#define L2CR_L2PE 0x40000000 /* 1: L2 data parity enable */ 629#define L2CR_L2SIZ 0x30000000 /* 2-3: L2 size */ 630#define L2SIZ_2M 0x00000000 631#define L2SIZ_256K 0x10000000 632#define L2SIZ_512K 0x20000000 633#define L2SIZ_1M 0x30000000 634#define L2CR_L2CLK 0x0e000000 /* 4-6: L2 clock ratio */ 635#define L2CLK_DIS 0x00000000 /* disable L2 clock */ 636#define L2CLK_10 0x02000000 /* core clock / 1 */ 637#define L2CLK_15 0x04000000 /* / 1.5 */ 638#define L2CLK_20 0x08000000 /* / 2 */ 639#define L2CLK_25 0x0a000000 /* / 2.5 */ 640#define L2CLK_30 0x0c000000 /* / 3 */ 641#define L2CR_L2RAM 0x01800000 /* 7-8: L2 RAM type */ 642#define L2RAM_FLOWTHRU_BURST 0x00000000 643#define L2RAM_PIPELINE_BURST 0x01000000 644#define L2RAM_PIPELINE_LATE 0x01800000 645#define L2CR_L2DO 0x00400000 /* 9: L2 data-only. 646 Setting this bit disables instruction 647 caching. */ 648#define L2CR_L2I 0x00200000 /* 10: L2 global invalidate. */ 649#define L2CR_L2IO_7450 0x00010000 /* 11: L2 instruction-only (MPC745x). */ 650#define L2CR_L2CTL 0x00100000 /* 11: L2 RAM control (ZZ enable). 651 Enables automatic operation of the 652 L2ZZ (low-power mode) signal. */ 653#define L2CR_L2WT 0x00080000 /* 12: L2 write-through. */ 654#define L2CR_L2TS 0x00040000 /* 13: L2 test support. */ 655#define L2CR_L2OH 0x00030000 /* 14-15: L2 output hold. */ 656#define L2CR_L2DO_7450 0x00010000 /* 15: L2 data-only (MPC745x). */ 657#define L2CR_L2SL 0x00008000 /* 16: L2 DLL slow. */ 658#define L2CR_L2DF 0x00004000 /* 17: L2 differential clock. */ 659#define L2CR_L2BYP 0x00002000 /* 18: L2 DLL bypass. */ 660#define L2CR_L2FA 0x00001000 /* 19: L2 flush assist (for software flush). */ 661#define L2CR_L2HWF 0x00000800 /* 20: L2 hardware flush. */ 662#define L2CR_L2IO 0x00000400 /* 21: L2 instruction-only. */ 663#define L2CR_L2CLKSTP 0x00000200 /* 22: L2 clock stop. */ 664#define L2CR_L2DRO 0x00000100 /* 23: L2DLL rollover checkstop enable. */ 665#define L2CR_L2IP 0x00000001 /* 31: L2 global invalidate in */ 666 /* progress (read only). */ 667#define SPR_L3CR 0x3fa /* .6. L3 Control Register */ 668#define L3CR_L3E 0x80000000 /* 0: L3 enable */ 669#define L3CR_L3PE 0x40000000 /* 1: L3 data parity enable */ 670#define L3CR_L3APE 0x20000000 671#define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ 672#define L3CR_L3CLKEN 0x08000000 /* 4: Enables L3_CLK[0:1] */ 673#define L3CR_L3CLK 0x03800000 674#define L3CR_L3IO 0x00400000 675#define L3CR_L3CLKEXT 0x00200000 676#define L3CR_L3CKSPEXT 0x00100000 677#define L3CR_L3OH1 0x00080000 678#define L3CR_L3SPO 0x00040000 679#define L3CR_L3CKSP 0x00030000 680#define L3CR_L3PSP 0x0000e000 681#define L3CR_L3REP 0x00001000 682#define L3CR_L3HWF 0x00000800 683#define L3CR_L3I 0x00000400 /* 21: L3 global invalidate */ 684#define L3CR_L3RT 0x00000300 685#define L3CR_L3NIRCA 0x00000080 686#define L3CR_L3DO 0x00000040 687#define L3CR_PMEN 0x00000004 688#define L3CR_PMSIZ 0x00000003 689 690#define SPR_DCCR 0x3fa /* 4.. Data Cache Cachability Register */ 691#define SPR_ICCR 0x3fb /* 4.. Instruction Cache Cachability Register */ 692#define SPR_THRM1 0x3fc /* .6. Thermal Management Register */ 693#define SPR_THRM2 0x3fd /* .6. Thermal Management Register */ 694#define SPR_THRM_TIN 0x80000000 /* Thermal interrupt bit (RO) */ 695#define SPR_THRM_TIV 0x40000000 /* Thermal interrupt valid (RO) */ 696#define SPR_THRM_THRESHOLD(x) ((x) << 23) /* Thermal sensor threshold */ 697#define SPR_THRM_TID 0x00000004 /* Thermal interrupt direction */ 698#define SPR_THRM_TIE 0x00000002 /* Thermal interrupt enable */ 699#define SPR_THRM_VALID 0x00000001 /* Valid bit */ 700#define SPR_THRM3 0x3fe /* .6. Thermal Management Register */ 701#define SPR_THRM_TIMER(x) ((x) << 1) /* Sampling interval timer */ 702#define SPR_THRM_ENABLE 0x00000001 /* TAU Enable */ 703#define SPR_FPECR 0x3fe /* .6. Floating-Point Exception Cause Register */ 704 705/* Time Base Register declarations */ 706#define TBR_TBL 0x10c /* 468 Time Base Lower - read */ 707#define TBR_TBU 0x10d /* 468 Time Base Upper - read */ 708#define TBR_TBWL 0x11c /* 468 Time Base Lower - supervisor, write */ 709#define TBR_TBWU 0x11d /* 468 Time Base Upper - supervisor, write */ 710 711/* Performance counter declarations */ 712#define PMC_OVERFLOW 0x80000000 /* Counter has overflowed */ 713 714/* The first five countable [non-]events are common to many PMC's */ 715#define PMCN_NONE 0 /* Count nothing */ 716#define PMCN_CYCLES 1 /* Processor cycles */ 717#define PMCN_ICOMP 2 /* Instructions completed */ 718#define PMCN_TBLTRANS 3 /* TBL bit transitions */ 719#define PCMN_IDISPATCH 4 /* Instructions dispatched */ 720 721/* Similar things for the 970 PMC direct counters */ 722#define PMC970N_NONE 0x8 /* Count nothing */ 723#define PMC970N_CYCLES 0xf /* Processor cycles */ 724#define PMC970N_ICOMP 0x9 /* Instructions completed */ 725 726#if defined(BOOKE) 727 728#define SPR_MCARU 0x239 /* ..8 Machine Check Address register upper bits */ 729#define SPR_MCSR 0x23c /* ..8 Machine Check Syndrome register */ 730#define SPR_MCAR 0x23d /* ..8 Machine Check Address register */ 731 732#define SPR_ESR 0x003e /* ..8 Exception Syndrome Register */ 733#define ESR_PIL 0x08000000 /* Program interrupt - illegal */ 734#define ESR_PPR 0x04000000 /* Program interrupt - privileged */ 735#define ESR_PTR 0x02000000 /* Program interrupt - trap */ 736#define ESR_ST 0x00800000 /* Store operation */ 737#define ESR_DLK 0x00200000 /* Data storage, D cache locking */ 738#define ESR_ILK 0x00100000 /* Data storage, I cache locking */ 739#define ESR_BO 0x00020000 /* Data/instruction storage, byte ordering */ 740#define ESR_SPE 0x00000080 /* SPE exception bit */ 741 742#define SPR_CSRR0 0x03a /* ..8 58 Critical SRR0 */ 743#define SPR_CSRR1 0x03b /* ..8 59 Critical SRR1 */ 744#define SPR_MCSRR0 0x23a /* ..8 570 Machine check SRR0 */ 745#define SPR_MCSRR1 0x23b /* ..8 571 Machine check SRR1 */ 746#define SPR_DSRR0 0x23e /* ..8 574 Debug SRR0<E.ED> */ 747#define SPR_DSRR1 0x23f /* ..8 575 Debug SRR1<E.ED> */ 748 749#define SPR_MMUCR 0x3b2 /* 4.. MMU Control Register */ 750#define MMUCR_SWOA (0x80000000 >> 7) 751#define MMUCR_U1TE (0x80000000 >> 9) 752#define MMUCR_U2SWOAE (0x80000000 >> 10) 753#define MMUCR_DULXE (0x80000000 >> 12) 754#define MMUCR_IULXE (0x80000000 >> 13) 755#define MMUCR_STS (0x80000000 >> 15) 756#define MMUCR_STID_MASK (0xFF000000 >> 24) 757 758#define SPR_MMUCSR0 0x3f4 /* ..8 1012 MMU Control and Status Register 0 */ 759#define MMUCSR0_L2TLB0_FI 0x04 /* TLB0 flash invalidate */ 760#define MMUCSR0_L2TLB1_FI 0x02 /* TLB1 flash invalidate */ 761 762#define SPR_SVR 0x3ff /* ..8 1023 System Version Register */ 763#define SVR_MPC8533 0x8034 764#define SVR_MPC8533E 0x803c 765#define SVR_MPC8541 0x8072 766#define SVR_MPC8541E 0x807a 767#define SVR_MPC8548 0x8031 768#define SVR_MPC8548E 0x8039 769#define SVR_MPC8555 0x8071 770#define SVR_MPC8555E 0x8079 771#define SVR_MPC8572 0x80e0 772#define SVR_MPC8572E 0x80e8 773#define SVR_P1011 0x80e5 774#define SVR_P1011E 0x80ed 775#define SVR_P1013 0x80e7 776#define SVR_P1013E 0x80ef 777#define SVR_P1020 0x80e4 778#define SVR_P1020E 0x80ec 779#define SVR_P1022 0x80e6 780#define SVR_P1022E 0x80ee 781#define SVR_P2010 0x80e3 782#define SVR_P2010E 0x80eb 783#define SVR_P2020 0x80e2 784#define SVR_P2020E 0x80ea 785#define SVR_P2041 0x8210 786#define SVR_P2041E 0x8218 787#define SVR_P3041 0x8211 788#define SVR_P3041E 0x8219 789#define SVR_P4040 0x8200 790#define SVR_P4040E 0x8208 791#define SVR_P4080 0x8201 792#define SVR_P4080E 0x8209 793#define SVR_P5010 0x8221 794#define SVR_P5010E 0x8229 795#define SVR_P5020 0x8220 796#define SVR_P5020E 0x8228 797#define SVR_P5021 0x8205 798#define SVR_P5021E 0x820d 799#define SVR_P5040 0x8204 800#define SVR_P5040E 0x820c 801#define SVR_VER(svr) (((svr) >> 16) & 0xffff) 802 803#define SPR_PID0 0x030 /* ..8 Process ID Register 0 */ 804#define SPR_PID1 0x279 /* ..8 Process ID Register 1 */ 805#define SPR_PID2 0x27a /* ..8 Process ID Register 2 */ 806 807#define SPR_TLB0CFG 0x2B0 /* ..8 TLB 0 Config Register */ 808#define SPR_TLB1CFG 0x2B1 /* ..8 TLB 1 Config Register */ 809#define TLBCFG_ASSOC_MASK 0xff000000 /* Associativity of TLB */ 810#define TLBCFG_ASSOC_SHIFT 24 811#define TLBCFG_NENTRY_MASK 0x00000fff /* Number of entries in TLB */ 812 813#define SPR_IVPR 0x03f /* ..8 Interrupt Vector Prefix Register */ 814#define SPR_IVOR0 0x190 /* ..8 Critical input */ 815#define SPR_IVOR1 0x191 /* ..8 Machine check */ 816#define SPR_IVOR2 0x192 817#define SPR_IVOR3 0x193 818#define SPR_IVOR4 0x194 819#define SPR_IVOR5 0x195 820#define SPR_IVOR6 0x196 821#define SPR_IVOR7 0x197 822#define SPR_IVOR8 0x198 823#define SPR_IVOR9 0x199 824#define SPR_IVOR10 0x19a 825#define SPR_IVOR11 0x19b 826#define SPR_IVOR12 0x19c 827#define SPR_IVOR13 0x19d 828#define SPR_IVOR14 0x19e 829#define SPR_IVOR15 0x19f 830#define SPR_IVOR32 0x210 831#define SPR_IVOR33 0x211 832#define SPR_IVOR34 0x212 833#define SPR_IVOR35 0x213 834 835#define SPR_MAS0 0x270 /* ..8 MMU Assist Register 0 Book-E/e500 */ 836#define SPR_MAS1 0x271 /* ..8 MMU Assist Register 1 Book-E/e500 */ 837#define SPR_MAS2 0x272 /* ..8 MMU Assist Register 2 Book-E/e500 */ 838#define SPR_MAS3 0x273 /* ..8 MMU Assist Register 3 Book-E/e500 */ 839#define SPR_MAS4 0x274 /* ..8 MMU Assist Register 4 Book-E/e500 */ 840#define SPR_MAS5 0x275 /* ..8 MMU Assist Register 5 Book-E */ 841#define SPR_MAS6 0x276 /* ..8 MMU Assist Register 6 Book-E/e500 */ 842#define SPR_MAS7 0x3B0 /* ..8 MMU Assist Register 7 Book-E/e500 */ 843#define SPR_MAS8 0x155 /* ..8 MMU Assist Register 8 Book-E/e500 */ 844 845#define SPR_L1CFG0 0x203 /* ..8 L1 cache configuration register 0 */ 846#define SPR_L1CFG1 0x204 /* ..8 L1 cache configuration register 1 */ 847 848#define SPR_CCR1 0x378 849#define CCR1_L2COBE 0x00000040 850 851#define DCR_L2DCDCRAI 0x0000 /* L2 D-Cache DCR Address Pointer */ 852#define DCR_L2DCDCRDI 0x0001 /* L2 D-Cache DCR Data Indirect */ 853#define DCR_L2CR0 0x00 /* L2 Cache Configuration Register 0 */ 854#define L2CR0_AS 0x30000000 855 856#define SPR_L1CSR0 0x3F2 /* ..8 L1 Cache Control and Status Register 0 */ 857#define L1CSR0_DCPE 0x00010000 /* Data Cache Parity Enable */ 858#define L1CSR0_DCLFR 0x00000100 /* Data Cache Lock Bits Flash Reset */ 859#define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */ 860#define L1CSR0_DCE 0x00000001 /* Data Cache Enable */ 861#define SPR_L1CSR1 0x3F3 /* ..8 L1 Cache Control and Status Register 1 */ 862#define L1CSR1_ICPE 0x00010000 /* Instruction Cache Parity Enable */ 863#define L1CSR1_ICUL 0x00000400 /* Instr Cache Unable to Lock */ 864#define L1CSR1_ICLFR 0x00000100 /* Instruction Cache Lock Bits Flash Reset */ 865#define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */ 866#define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */ 867 868#define SPR_L2CSR0 0x3F9 /* ..8 L2 Cache Control and Status Register 0 */ 869#define L2CSR0_L2E 0x80000000 /* L2 Cache Enable */ 870#define L2CSR0_L2PE 0x40000000 /* L2 Cache Parity Enable */ 871#define L2CSR0_L2FI 0x00200000 /* L2 Cache Flash Invalidate */ 872#define L2CSR0_L2LFC 0x00000400 /* L2 Cache Lock Flags Clear */ 873 874#define SPR_BUCSR 0x3F5 /* ..8 Branch Unit Control and Status Register */ 875#define BUCSR_BPEN 0x00000001 /* Branch Prediction Enable */ 876#define BUCSR_BBFI 0x00000200 /* Branch Buffer Flash Invalidate */ 877 878#endif /* BOOKE */ 879#endif /* !_POWERPC_SPR_H_ */ 880