1/*-
2 * Copyright (c) 2016 Stanislav Galabov.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30#ifndef _MTK_SOC_H_
31#define _MTK_SOC_H_
32
33enum mtk_soc_id {
34	MTK_SOC_UNKNOWN,
35	MTK_SOC_RT2880,
36	MTK_SOC_RT3050,
37	MTK_SOC_RT3052,
38	MTK_SOC_RT3350,
39	MTK_SOC_RT3352,
40	MTK_SOC_RT3662,
41	MTK_SOC_RT3883,
42	MTK_SOC_RT5350,
43	MTK_SOC_MT7620A,
44	MTK_SOC_MT7620N,
45	MTK_SOC_MT7621,
46	MTK_SOC_MT7628,
47	MTK_SOC_MT7688,
48	MTK_SOC_MAX
49};
50
51#define RT2880_CPU_CLKSEL_OFF	20
52#define RT2880_CPU_CLKSEL_MSK	0x3
53#define RT305X_CPU_CLKSEL_OFF	18
54#define RT305X_CPU_CLKSEL_MSK	0x1
55#define RT3352_CPU_CLKSEL_OFF	8
56#define RT3352_CPU_CLKSEL_MSK	0x1
57#define RT3883_CPU_CLKSEL_OFF	8
58#define RT3883_CPU_CLKSEL_MSK	0x3
59#define RT5350_CPU_CLKSEL_OFF1	8
60#define RT5350_CPU_CLKSEL_OFF2	10
61#define RT5350_CPU_CLKSEL_MSK	0x1
62#define MT7628_CPU_CLKSEL_OFF	6
63#define MT7628_CPU_CLKSEL_MSK	0x1
64
65#define MT7620_CPU_CLK_AUX0	(1u<<24)
66#define MT7620_CPLL_SW_CFG	(1u<<31)
67#define MT7620_PLL_MULT_RATIO_OFF	16
68#define MT7620_PLL_MULT_RATIO_MSK	0x7
69#define MT7620_PLL_MULT_RATIO_BASE	24
70#define MT7620_PLL_DIV_RATIO_OFF	10
71#define MT7620_PLL_DIV_RATIO_MSK	0x3
72#define MT7620_PLL_DIV_RATIO_BASE	2
73#define MT7620_PLL_DIV_RATIO_MAX	8
74#define MT7620_XTAL_40			40
75
76#define MT7621_USES_MEMDIV	(1u<<30)
77#define MT7621_MEMDIV_OFF	4
78#define MT7621_MEMDIV_MSK	0x7f
79#define MT7621_MEMDIV_BASE	1
80#define MT7621_CLKSEL_OFF	6
81#define MT7621_CLKSEL_MSK	0x7
82#define MT7621_CLKSEL_25MHZ_VAL	6
83#define MT7621_CLKSEL_20MHZ_VAL	3
84#define MT7621_CLKSEL_20MHZ	20
85#define MT7621_CLKSEL_25MHZ	25
86#define MT7621_CLK_STS_DIV_OFF	8
87#define MT7621_CLK_STS_MSK	0x1f
88#define MT7621_CLK_STS_BASE	500
89
90#define MTK_MT7621_CLKDIV_REG	0x5648
91#define MTK_MT7621_CLKDIV_OFF	4
92#define MTK_MT7621_CLKDIV_MSK	0x7f
93
94#define MTK_MHZ(x)		((x) * 1000 * 1000)
95
96#define MTK_CPU_CLK_UNKNOWN	0
97#define MTK_CPU_CLK_233MHZ	233333333
98#define MTK_CPU_CLK_250MHZ	250000000
99#define MTK_CPU_CLK_266MHZ	266666666
100#define MTK_CPU_CLK_280MHZ	280000000
101#define MTK_CPU_CLK_300MHZ	300000000
102#define MTK_CPU_CLK_320MHZ	320000000
103#define MTK_CPU_CLK_360MHZ	360000000
104#define MTK_CPU_CLK_384MHZ	384000000
105#define MTK_CPU_CLK_400MHZ	400000000
106#define MTK_CPU_CLK_480MHZ	480000000
107#define MTK_CPU_CLK_500MHZ	500000000
108#define MTK_CPU_CLK_575MHZ	575000000
109#define MTK_CPU_CLK_580MHZ	580000000
110#define MTK_CPU_CLK_600MHZ	600000000
111#define MTK_CPU_CLK_880MHZ	880000000
112
113#define MTK_UART_CLK_40MHZ	40000000
114#define MTK_UART_CLK_50MHZ	50000000
115
116#define MTK_UARTDIV_2		2
117#define MTK_UARTDIV_3		3
118
119#define MTK_DEFAULT_BASE	0x10000000
120#define MTK_RT2880_BASE		0x00300000
121#define MTK_MT7621_BASE		0x1e000000
122#define MTK_DEFAULT_SIZE	0x6000
123
124extern void     mtk_soc_try_early_detect(void);
125extern uint32_t mtk_soc_get_uartclk(void);
126extern uint32_t mtk_soc_get_cpuclk(void);
127extern uint32_t mtk_soc_get_timerclk(void);
128extern uint32_t mtk_soc_get_socid(void);
129
130extern int	mtk_soc_reset_device(device_t);
131extern int	mtk_soc_stop_clock(device_t);
132extern int	mtk_soc_start_clock(device_t);
133extern int	mtk_soc_assert_reset(device_t);
134extern int	mtk_soc_deassert_reset(device_t);
135extern void     mtk_soc_reset(void);
136
137#endif /* _MTK_SOC_H_ */
138