1/*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
19 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
20 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
21 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
22 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD$
27 */
28
29/*
30 * Ingenic JZ4780 SMB Controller
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD$");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39#include <sys/rman.h>
40#include <sys/kernel.h>
41#include <sys/module.h>
42#include <sys/time.h>
43#include <machine/bus.h>
44
45#include <dev/ofw/ofw_bus.h>
46#include <dev/ofw/ofw_bus_subr.h>
47
48#include <dev/iicbus/iiconf.h>
49#include <dev/iicbus/iicbus.h>
50
51#include <dev/extres/clk/clk.h>
52
53#include <mips/ingenic/jz4780_smb.h>
54
55#include "iicbus_if.h"
56
57#define	JZSMB_TIMEOUT			((300UL * hz) / 1000)
58
59#define	JZSMB_SPEED_STANDARD		100000
60#define	JZSMB_SETUP_TIME_STANDARD	300
61#define	JZSMB_HOLD_TIME_STANDARD	400
62#define	JZSMB_PERIOD_MIN_STANDARD	4000
63#define	JZSMB_PERIOD_MAX_STANDARD	4700
64
65#define	JZSMB_SPEED_FAST		400000
66#define	JZSMB_SETUP_TIME_FAST		450
67#define	JZSMB_HOLD_TIME_FAST		450
68#define	JZSMB_PERIOD_MIN_FAST		600
69#define	JZSMB_PERIOD_MAX_FAST		1300
70
71#define	JZSMB_HCNT_BASE			8
72#define	JZSMB_HCNT_MIN			6
73#define	JZSMB_LCNT_BASE			1
74#define	JZSMB_LCNT_MIN			8
75
76static inline int
77tstohz(const struct timespec *tsp)
78{
79	struct timeval tv;
80
81	TIMESPEC_TO_TIMEVAL(&tv, tsp);
82	return (tvtohz(&tv));
83}
84
85static struct ofw_compat_data compat_data[] = {
86	{ "ingenic,jz4780-i2c",		1 },
87	{ NULL,				0 }
88};
89
90static struct resource_spec jzsmb_spec[] = {
91	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
92	{ -1, 0 }
93};
94
95struct jzsmb_softc {
96	struct resource	*res;
97	struct mtx	mtx;
98	clk_t		clk;
99	device_t	iicbus;
100	int		busy;
101	uint32_t	i2c_freq;
102	uint64_t	bus_freq;
103	uint32_t	status;
104
105	struct iic_msg	*msg;
106};
107
108#define	SMB_LOCK(sc)			mtx_lock(&(sc)->mtx)
109#define	SMB_UNLOCK(sc)			mtx_unlock(&(sc)->mtx)
110#define	SMB_ASSERT_LOCKED(sc)		mtx_assert(&(sc)->mtx, MA_OWNED)
111#define	SMB_READ(sc, reg)		bus_read_2((sc)->res, (reg))
112#define	SMB_WRITE(sc, reg, val)		bus_write_2((sc)->res, (reg), (val))
113
114static phandle_t
115jzsmb_get_node(device_t bus, device_t dev)
116{
117	return (ofw_bus_get_node(bus));
118}
119
120static int
121jzsmb_enable(struct jzsmb_softc *sc, int enable)
122{
123	SMB_ASSERT_LOCKED(sc);
124
125	if (enable) {
126		SMB_WRITE(sc, SMBENB, SMBENB_SMBENB);
127		while ((SMB_READ(sc, SMBENBST) & SMBENBST_SMBEN) == 0)
128			;
129	} else {
130		SMB_WRITE(sc, SMBENB, 0);
131		while ((SMB_READ(sc, SMBENBST) & SMBENBST_SMBEN) != 0)
132			;
133	}
134
135	return (0);
136}
137
138static int
139jzsmb_reset_locked(device_t dev, u_char addr)
140{
141	struct jzsmb_softc *sc;
142	uint16_t con;
143	uint32_t period;
144	int hcnt, lcnt, setup_time, hold_time;
145
146	sc = device_get_softc(dev);
147
148	SMB_ASSERT_LOCKED(sc);
149
150	/* Setup master mode operation */
151
152	/* Disable SMB */
153	jzsmb_enable(sc, 0);
154
155	/* Disable interrupts */
156	SMB_WRITE(sc, SMBINTM, 0);
157
158	/* Set supported speed mode and expected SCL frequency */
159	period = sc->bus_freq / sc->i2c_freq;
160	con = SMBCON_REST | SMBCON_SLVDIS | SMBCON_MD;
161	switch (sc->i2c_freq) {
162	case JZSMB_SPEED_STANDARD:
163		con |= SMBCON_SPD_STANDARD;
164		setup_time = JZSMB_SETUP_TIME_STANDARD;
165		hold_time = JZSMB_HOLD_TIME_STANDARD;
166		hcnt = (period * JZSMB_PERIOD_MIN_STANDARD) /
167		    (JZSMB_PERIOD_MAX_STANDARD + JZSMB_PERIOD_MIN_STANDARD);
168		lcnt = period - hcnt;
169		hcnt = MAX(hcnt - JZSMB_HCNT_BASE, JZSMB_HCNT_MIN);
170		lcnt = MAX(lcnt - JZSMB_LCNT_BASE, JZSMB_LCNT_MIN);
171		SMB_WRITE(sc, SMBCON, con);
172		SMB_WRITE(sc, SMBSHCNT, hcnt);
173		SMB_WRITE(sc, SMBSLCNT, lcnt);
174		break;
175	case JZSMB_SPEED_FAST:
176		con |= SMBCON_SPD_FAST;
177		setup_time = JZSMB_SETUP_TIME_FAST;
178		hold_time = JZSMB_HOLD_TIME_FAST;
179		hcnt = (period * JZSMB_PERIOD_MIN_FAST) /
180		    (JZSMB_PERIOD_MAX_FAST + JZSMB_PERIOD_MIN_FAST);
181		lcnt = period - hcnt;
182		hcnt = MAX(hcnt - JZSMB_HCNT_BASE, JZSMB_HCNT_MIN);
183		lcnt = MAX(lcnt - JZSMB_LCNT_BASE, JZSMB_LCNT_MIN);
184		SMB_WRITE(sc, SMBCON, con);
185		SMB_WRITE(sc, SMBFHCNT, hcnt);
186		SMB_WRITE(sc, SMBFLCNT, lcnt);
187		break;
188	default:
189		return (EINVAL);
190	}
191
192	setup_time = ((setup_time * sc->bus_freq / 1000) / 1000000) + 1;
193	setup_time = MIN(1, MAX(255, setup_time));
194	SMB_WRITE(sc, SMBSDASU, setup_time);
195
196	hold_time = ((hold_time * sc->bus_freq / 1000) / 1000000) - 1;
197	hold_time = MAX(255, hold_time);
198	if (hold_time >= 0)
199		SMB_WRITE(sc, SMBSDAHD, hold_time | SMBSDAHD_HDENB);
200	else
201		SMB_WRITE(sc, SMBSDAHD, 0);
202
203	SMB_WRITE(sc, SMBTAR, addr >> 1);
204
205	if (addr != 0) {
206		/* Enable SMB */
207		jzsmb_enable(sc, 1);
208	}
209
210	return (0);
211}
212
213static int
214jzsmb_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
215{
216	struct jzsmb_softc *sc;
217	int error;
218
219	sc = device_get_softc(dev);
220
221	SMB_LOCK(sc);
222	error = jzsmb_reset_locked(dev, addr);
223	SMB_UNLOCK(sc);
224
225	return (error);
226}
227
228static int
229jzsmb_transfer_read(device_t dev, struct iic_msg *msg)
230{
231	struct jzsmb_softc *sc;
232	struct timespec start, diff;
233	uint16_t con, resid;
234	int timeo;
235
236	sc = device_get_softc(dev);
237	timeo = JZSMB_TIMEOUT * msg->len;
238
239	SMB_ASSERT_LOCKED(sc);
240
241	con = SMB_READ(sc, SMBCON);
242	con |= SMBCON_STPHLD;
243	SMB_WRITE(sc, SMBCON, con);
244
245	getnanouptime(&start);
246	for (resid = msg->len; resid > 0; resid--) {
247		for (int i = 0; i < min(resid, 8); i++)
248			SMB_WRITE(sc, SMBDC, SMBDC_CMD);
249		for (;;) {
250			getnanouptime(&diff);
251			timespecsub(&diff, &start, &diff);
252			if ((SMB_READ(sc, SMBST) & SMBST_RFNE) != 0) {
253				msg->buf[msg->len - resid] =
254				    SMB_READ(sc, SMBDC) & SMBDC_DAT;
255				break;
256			} else
257				DELAY(1000);
258
259			if (tstohz(&diff) >= timeo) {
260				device_printf(dev,
261				    "read timeout (status=0x%02x)\n",
262				    SMB_READ(sc, SMBST));
263				return (EIO);
264			}
265		}
266	}
267
268	con = SMB_READ(sc, SMBCON);
269	con &= ~SMBCON_STPHLD;
270	SMB_WRITE(sc, SMBCON, con);
271
272	return (0);
273}
274
275static int
276jzsmb_transfer_write(device_t dev, struct iic_msg *msg, int stop_hold)
277{
278	struct jzsmb_softc *sc;
279	struct timespec start, diff;
280	uint16_t con, resid;
281	int timeo;
282
283	sc = device_get_softc(dev);
284	timeo = JZSMB_TIMEOUT * msg->len;
285
286	SMB_ASSERT_LOCKED(sc);
287
288	con = SMB_READ(sc, SMBCON);
289	con |= SMBCON_STPHLD;
290	SMB_WRITE(sc, SMBCON, con);
291
292	getnanouptime(&start);
293	for (resid = msg->len; resid > 0; resid--) {
294		for (;;) {
295			getnanouptime(&diff);
296			timespecsub(&diff, &start, &diff);
297			if ((SMB_READ(sc, SMBST) & SMBST_TFNF) != 0) {
298				SMB_WRITE(sc, SMBDC,
299				    msg->buf[msg->len - resid]);
300				break;
301			} else
302				DELAY((1000 * hz) / JZSMB_TIMEOUT);
303
304			if (tstohz(&diff) >= timeo) {
305				device_printf(dev,
306				    "write timeout (status=0x%02x)\n",
307				    SMB_READ(sc, SMBST));
308				return (EIO);
309			}
310		}
311	}
312
313	if (!stop_hold) {
314		con = SMB_READ(sc, SMBCON);
315		con &= ~SMBCON_STPHLD;
316		SMB_WRITE(sc, SMBCON, con);
317	}
318
319	return (0);
320}
321
322static int
323jzsmb_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
324{
325	struct jzsmb_softc *sc;
326	uint32_t n;
327	uint16_t con;
328	int error;
329
330	sc = device_get_softc(dev);
331
332	SMB_LOCK(sc);
333	while (sc->busy)
334		mtx_sleep(sc, &sc->mtx, 0, "i2cbuswait", 0);
335	sc->busy = 1;
336	sc->status = 0;
337
338	for (n = 0; n < nmsgs; n++) {
339		/* Set target address */
340		if (n == 0 || msgs[n].slave != msgs[n - 1].slave)
341			jzsmb_reset_locked(dev, msgs[n].slave);
342
343		/* Set read or write */
344		if ((msgs[n].flags & IIC_M_RD) != 0)
345			error = jzsmb_transfer_read(dev, &msgs[n]);
346		else
347			error = jzsmb_transfer_write(dev, &msgs[n],
348			    n < nmsgs - 1);
349
350		if (error != 0)
351			goto done;
352	}
353
354done:
355	/* Send stop if necessary */
356	con = SMB_READ(sc, SMBCON);
357	con &= ~SMBCON_STPHLD;
358	SMB_WRITE(sc, SMBCON, con);
359
360	/* Disable SMB */
361	jzsmb_enable(sc, 0);
362
363	sc->msg = NULL;
364	sc->busy = 0;
365	wakeup(sc);
366	SMB_UNLOCK(sc);
367
368	return (error);
369}
370
371static int
372jzsmb_probe(device_t dev)
373{
374	if (!ofw_bus_status_okay(dev))
375		return (ENXIO);
376
377	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
378		return (ENXIO);
379
380	device_set_desc(dev, "Ingenic JZ4780 SMB Controller");
381
382	return (BUS_PROBE_DEFAULT);
383}
384
385static int
386jzsmb_attach(device_t dev)
387{
388	struct jzsmb_softc *sc;
389	phandle_t node;
390	int error;
391
392	sc = device_get_softc(dev);
393	node = ofw_bus_get_node(dev);
394	mtx_init(&sc->mtx, device_get_nameunit(dev), "jzsmb", MTX_DEF);
395
396	error = clk_get_by_ofw_index(dev, 0, 0, &sc->clk);
397	if (error != 0) {
398		device_printf(dev, "cannot get clock\n");
399		goto fail;
400	}
401	error = clk_enable(sc->clk);
402	if (error != 0) {
403		device_printf(dev, "cannot enable clock\n");
404		goto fail;
405	}
406	error = clk_get_freq(sc->clk, &sc->bus_freq);
407	if (error != 0 || sc->bus_freq == 0) {
408		device_printf(dev, "cannot get bus frequency\n");
409		return (error);
410	}
411
412	if (bus_alloc_resources(dev, jzsmb_spec, &sc->res) != 0) {
413		device_printf(dev, "cannot allocate resources for device\n");
414		error = ENXIO;
415		goto fail;
416	}
417
418	if (OF_getencprop(node, "clock-frequency", &sc->i2c_freq,
419	    sizeof(sc->i2c_freq)) != 0 || sc->i2c_freq == 0)
420		sc->i2c_freq = 100000;	/* Default to standard mode */
421
422	sc->iicbus = device_add_child(dev, "iicbus", -1);
423	if (sc->iicbus == NULL) {
424		device_printf(dev, "cannot add iicbus child device\n");
425		error = ENXIO;
426		goto fail;
427	}
428
429	bus_generic_attach(dev);
430
431	return (0);
432
433fail:
434	bus_release_resources(dev, jzsmb_spec, &sc->res);
435	if (sc->clk != NULL)
436		clk_release(sc->clk);
437	mtx_destroy(&sc->mtx);
438	return (error);
439}
440
441static device_method_t jzsmb_methods[] = {
442	/* Device interface */
443	DEVMETHOD(device_probe,		jzsmb_probe),
444	DEVMETHOD(device_attach,	jzsmb_attach),
445
446	/* Bus interface */
447	DEVMETHOD(bus_setup_intr,	bus_generic_setup_intr),
448	DEVMETHOD(bus_teardown_intr,	bus_generic_teardown_intr),
449	DEVMETHOD(bus_alloc_resource,	bus_generic_alloc_resource),
450	DEVMETHOD(bus_release_resource,	bus_generic_release_resource),
451	DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
452	DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
453	DEVMETHOD(bus_adjust_resource,	bus_generic_adjust_resource),
454	DEVMETHOD(bus_set_resource,	bus_generic_rl_set_resource),
455	DEVMETHOD(bus_get_resource,	bus_generic_rl_get_resource),
456
457	/* OFW methods */
458	DEVMETHOD(ofw_bus_get_node,	jzsmb_get_node),
459
460	/* iicbus interface */
461	DEVMETHOD(iicbus_callback,	iicbus_null_callback),
462	DEVMETHOD(iicbus_reset,		jzsmb_reset),
463	DEVMETHOD(iicbus_transfer,	jzsmb_transfer),
464
465	DEVMETHOD_END
466};
467
468static driver_t jzsmb_driver = {
469	"iichb",
470	jzsmb_methods,
471	sizeof(struct jzsmb_softc),
472};
473
474static devclass_t jzsmb_devclass;
475
476EARLY_DRIVER_MODULE(iicbus, jzsmb, iicbus_driver, iicbus_devclass, 0, 0,
477    BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
478EARLY_DRIVER_MODULE(jzsmb, simplebus, jzsmb_driver, jzsmb_devclass, 0, 0,
479    BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
480MODULE_VERSION(jzsmb, 1);
481