1/* $FreeBSD$ */ 2/*- 3 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 4 * 5 * Copyright (c) 2007 Hans Petter Selasky <hselasky@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30#ifndef _USS820_DCI_H_ 31#define _USS820_DCI_H_ 32 33#define USS820_MAX_DEVICES (USB_MIN_DEVICES + 1) 34 35#define USS820_EP_MAX 8 /* maximum number of endpoints */ 36 37#define USS820_TXDAT 0x00 /* Transmit FIFO data */ 38 39#define USS820_TXCNTL 0x01 /* Transmit FIFO byte count low */ 40#define USS820_TXCNTL_MASK 0xFF 41 42#define USS820_TXCNTH 0x02 /* Transmit FIFO byte count high */ 43#define USS820_TXCNTH_MASK 0x03 44#define USS820_TXCNTH_UNUSED 0xFC 45 46#define USS820_TXCON 0x03 /* USB transmit FIFO control */ 47#define USS820_TXCON_REVRP 0x01 48#define USS820_TXCON_ADVRM 0x02 49#define USS820_TXCON_ATM 0x04 /* Automatic Transmit Management */ 50#define USS820_TXCON_TXISO 0x08 /* Transmit Isochronous Data */ 51#define USS820_TXCON_UNUSED 0x10 52#define USS820_TXCON_FFSZ_16_64 0x00 53#define USS820_TXCON_FFSZ_64_256 0x20 54#define USS820_TXCON_FFSZ_8_512 0x40 55#define USS820_TXCON_FFSZ_32_1024 0x60 56#define USS820_TXCON_FFSZ_MASK 0x60 57#define USS820_TXCON_TXCLR 0x80 /* Transmit FIFO clear */ 58 59#define USS820_TXFLG 0x04 /* Transmit FIFO flag (Read Only) */ 60#define USS820_TXFLG_TXOVF 0x01 /* TX overrun */ 61#define USS820_TXFLG_TXURF 0x02 /* TX underrun */ 62#define USS820_TXFLG_TXFULL 0x04 /* TX full */ 63#define USS820_TXFLG_TXEMP 0x08 /* TX empty */ 64#define USS820_TXFLG_UNUSED 0x30 65#define USS820_TXFLG_TXFIF0 0x40 66#define USS820_TXFLG_TXFIF1 0x80 67 68#define USS820_RXDAT 0x05 /* Receive FIFO data */ 69 70#define USS820_RXCNTL 0x06 /* Receive FIFO byte count low */ 71#define USS820_RXCNTL_MASK 0xFF 72 73#define USS820_RXCNTH 0x07 /* Receive FIFO byte count high */ 74#define USS820_RXCNTH_MASK 0x03 75#define USS820_RXCNTH_UNUSED 0xFC 76 77#define USS820_RXCON 0x08 /* Receive FIFO control */ 78#define USS820_RXCON_REVWP 0x01 79#define USS820_RXCON_ADVWM 0x02 80#define USS820_RXCON_ARM 0x04 /* Auto Receive Management */ 81#define USS820_RXCON_RXISO 0x08 /* Receive Isochronous Data */ 82#define USS820_RXCON_RXFFRC 0x10 /* FIFO Read Complete */ 83#define USS820_RXCON_FFSZ_16_64 0x00 84#define USS820_RXCON_FFSZ_64_256 0x20 85#define USS820_RXCON_FFSZ_8_512 0x40 86#define USS820_RXCON_FFSZ_32_1024 0x60 87#define USS820_RXCON_RXCLR 0x80 /* Receive FIFO clear */ 88 89#define USS820_RXFLG 0x09 /* Receive FIFO flag (Read Only) */ 90#define USS820_RXFLG_RXOVF 0x01 /* RX overflow */ 91#define USS820_RXFLG_RXURF 0x02 /* RX underflow */ 92#define USS820_RXFLG_RXFULL 0x04 /* RX full */ 93#define USS820_RXFLG_RXEMP 0x08 /* RX empty */ 94#define USS820_RXFLG_RXFLUSH 0x10 /* RX flush */ 95#define USS820_RXFLG_UNUSED 0x20 96#define USS820_RXFLG_RXFIF0 0x40 97#define USS820_RXFLG_RXFIF1 0x80 98 99#define USS820_EPINDEX 0x0a /* Endpoint index selection */ 100#define USS820_EPINDEX_MASK 0x07 101#define USS820_EPINDEX_UNUSED 0xF8 102 103#define USS820_EPCON 0x0b /* Endpoint control */ 104#define USS820_EPCON_TXEPEN 0x01 /* Transmit Endpoint Enable */ 105#define USS820_EPCON_TXOE 0x02 /* Transmit Output Enable */ 106#define USS820_EPCON_RXEPEN 0x04 /* Receive Endpoint Enable */ 107#define USS820_EPCON_RXIE 0x08 /* Receive Input Enable */ 108#define USS820_EPCON_RXSPM 0x10 /* Receive Single-Packet Mode */ 109#define USS820_EPCON_CTLEP 0x20 /* Control Endpoint */ 110#define USS820_EPCON_TXSTL 0x40 /* Stall Transmit Endpoint */ 111#define USS820_EPCON_RXSTL 0x80 /* Stall Receive Endpoint */ 112 113#define USS820_TXSTAT 0x0c /* Transmit status */ 114#define USS820_TXSTAT_TXACK 0x01 /* Transmit Acknowledge */ 115#define USS820_TXSTAT_TXERR 0x02 /* Transmit Error */ 116#define USS820_TXSTAT_TXVOID 0x04 /* Transmit Void */ 117#define USS820_TXSTAT_TXSOVW 0x08 /* Transmit Data Sequence Overwrite 118 * Bit */ 119#define USS820_TXSTAT_TXFLUSH 0x10 /* Transmit FIFO Packet Flushed */ 120#define USS820_TXSTAT_TXNAKE 0x20 /* Transmit NAK Mode Enable */ 121#define USS820_TXSTAT_TXDSAM 0x40 /* Transmit Data-Set-Available Mode */ 122#define USS820_TXSTAT_TXSEQ 0x80 /* Transmitter Current Sequence Bit */ 123 124#define USS820_RXSTAT 0x0d /* Receive status */ 125#define USS820_RXSTAT_RXACK 0x01 /* Receive Acknowledge */ 126#define USS820_RXSTAT_RXERR 0x02 /* Receive Error */ 127#define USS820_RXSTAT_RXVOID 0x04 /* Receive Void */ 128#define USS820_RXSTAT_RXSOVW 0x08 /* Receive Data Sequence Overwrite Bit */ 129#define USS820_RXSTAT_EDOVW 0x10 /* End Overwrite Flag */ 130#define USS820_RXSTAT_STOVW 0x20 /* Start Overwrite Flag */ 131#define USS820_RXSTAT_RXSETUP 0x40 /* Received SETUP token */ 132#define USS820_RXSTAT_RXSEQ 0x80 /* Receiver Endpoint Sequence Bit */ 133 134#define USS820_SOFL 0x0e /* Start Of Frame counter low */ 135#define USS820_SOFL_MASK 0xFF 136 137#define USS820_SOFH 0x0f /* Start Of Frame counter high */ 138#define USS820_SOFH_MASK 0x07 139#define USS820_SOFH_SOFDIS 0x08 /* SOF Pin Output Disable */ 140#define USS820_SOFH_FTLOCK 0x10 /* Frame Timer Lock */ 141#define USS820_SOFH_SOFIE 0x20 /* SOF Interrupt Enable */ 142#define USS820_SOFH_ASOF 0x40 /* Any Start of Frame */ 143#define USS820_SOFH_SOFACK 0x80 /* SOF Token Received Without Error */ 144 145#define USS820_FADDR 0x10 /* Function Address */ 146#define USS820_FADDR_MASK 0x7F 147#define USS820_FADDR_UNUSED 0x80 148 149#define USS820_SCR 0x11 /* System Control */ 150#define USS820_SCR_UNUSED 0x01 151#define USS820_SCR_T_IRQ 0x02 /* Global Interrupt Enable */ 152#define USS820_SCR_IRQLVL 0x04 /* Interrupt Mode */ 153#define USS820_SCR_SRESET 0x08 /* Software reset */ 154#define USS820_SCR_IE_RESET 0x10 /* Enable Reset Interrupt */ 155#define USS820_SCR_IE_SUSP 0x20 /* Enable Suspend Interrupt */ 156#define USS820_SCR_RWUPE 0x40 /* Enable Remote Wake-Up Feature */ 157#define USS820_SCR_IRQPOL 0x80 /* IRQ polarity */ 158 159#define USS820_SSR 0x12 /* System Status */ 160#define USS820_SSR_RESET 0x01 /* Reset Condition Detected on USB 161 * cable */ 162#define USS820_SSR_SUSPEND 0x02 /* Suspend Detected */ 163#define USS820_SSR_RESUME 0x04 /* Resume Detected */ 164#define USS820_SSR_SUSPDIS 0x08 /* Suspend Disable */ 165#define USS820_SSR_SUSPPO 0x10 /* Suspend Power Off */ 166#define USS820_SSR_UNUSED 0xE0 167 168#define USS820_UNK0 0x13 /* Unknown */ 169#define USS820_UNK0_UNUSED 0xFF 170 171#define USS820_SBI 0x14 /* Serial bus interrupt low */ 172#define USS820_SBI_FTXD0 0x01 /* Function Transmit Done, EP 0 */ 173#define USS820_SBI_FRXD0 0x02 /* Function Receive Done, EP 0 */ 174#define USS820_SBI_FTXD1 0x04 175#define USS820_SBI_FRXD1 0x08 176#define USS820_SBI_FTXD2 0x10 177#define USS820_SBI_FRXD2 0x20 178#define USS820_SBI_FTXD3 0x40 179#define USS820_SBI_FRXD3 0x80 180 181#define USS820_SBI1 0x15 /* Serial bus interrupt high */ 182#define USS820_SBI1_FTXD4 0x01 183#define USS820_SBI1_FRXD4 0x02 184#define USS820_SBI1_FTXD5 0x04 185#define USS820_SBI1_FRXD5 0x08 186#define USS820_SBI1_FTXD6 0x10 187#define USS820_SBI1_FRXD6 0x20 188#define USS820_SBI1_FTXD7 0x40 189#define USS820_SBI1_FRXD7 0x80 190 191#define USS820_SBIE 0x16 /* Serial bus interrupt enable low */ 192#define USS820_SBIE_FTXIE0 0x01 193#define USS820_SBIE_FRXIE0 0x02 194#define USS820_SBIE_FTXIE1 0x04 195#define USS820_SBIE_FRXIE1 0x08 196#define USS820_SBIE_FTXIE2 0x10 197#define USS820_SBIE_FRXIE2 0x20 198#define USS820_SBIE_FTXIE3 0x40 199#define USS820_SBIE_FRXIE3 0x80 200 201#define USS820_SBIE1 0x17 /* Serial bus interrupt enable high */ 202#define USS820_SBIE1_FTXIE4 0x01 203#define USS820_SBIE1_FRXIE4 0x02 204#define USS820_SBIE1_FTXIE5 0x04 205#define USS820_SBIE1_FRXIE5 0x08 206#define USS820_SBIE1_FTXIE6 0x10 207#define USS820_SBIE1_FRXIE6 0x20 208#define USS820_SBIE1_FTXIE7 0x40 209#define USS820_SBIE1_FRXIE7 0x80 210 211#define USS820_REV 0x18 /* Hardware revision */ 212#define USS820_REV_MIN 0x0F 213#define USS820_REV_MAJ 0xF0 214 215#define USS820_LOCK 0x19 /* Suspend power-off locking */ 216#define USS820_LOCK_UNLOCKED 0x01 217#define USS820_LOCK_UNUSED 0xFE 218 219#define USS820_PEND 0x1a /* Pend hardware status update */ 220#define USS820_PEND_PEND 0x01 221#define USS820_PEND_UNUSED 0xFE 222 223#define USS820_SCRATCH 0x1b /* Scratch firmware information */ 224#define USS820_SCRATCH_MASK 0x7F 225#define USS820_SCRATCH_IE_RESUME 0x80 /* Enable Resume Interrupt */ 226 227#define USS820_MCSR 0x1c /* Miscellaneous control and status */ 228#define USS820_MCSR_DPEN 0x01 /* DPLS Pull-Up Enable */ 229#define USS820_MCSR_SUSPLOE 0x02 /* Suspend Lock Out Enable */ 230#define USS820_MCSR_BDFEAT 0x04 /* Board Feature Enable */ 231#define USS820_MCSR_FEAT 0x08 /* Feature Enable */ 232#define USS820_MCSR_PKGID 0x10 /* Package Identification */ 233#define USS820_MCSR_SUSPS 0x20 /* Suspend Status */ 234#define USS820_MCSR_INIT 0x40 /* Device Initialized */ 235#define USS820_MCSR_RWUPR 0x80 /* Remote Wakeup-Up Remember */ 236 237#define USS820_DSAV 0x1d /* Data set available low (Read Only) */ 238#define USS820_DSAV_TXAV0 0x01 239#define USS820_DSAV_RXAV0 0x02 240#define USS820_DSAV_TXAV1 0x04 241#define USS820_DSAV_RXAV1 0x08 242#define USS820_DSAV_TXAV2 0x10 243#define USS820_DSAV_RXAV2 0x20 244#define USS820_DSAV_TXAV3 0x40 245#define USS820_DSAV_RXAV3 0x80 246 247#define USS820_DSAV1 0x1e /* Data set available high */ 248#define USS820_DSAV1_TXAV4 0x01 249#define USS820_DSAV1_RXAV4 0x02 250#define USS820_DSAV1_TXAV5 0x04 251#define USS820_DSAV1_RXAV5 0x08 252#define USS820_DSAV1_TXAV6 0x10 253#define USS820_DSAV1_RXAV6 0x20 254#define USS820_DSAV1_TXAV7 0x40 255#define USS820_DSAV1_RXAV7 0x80 256 257#define USS820_UNK1 0x1f /* Unknown */ 258#define USS820_UNK1_UNKNOWN 0xFF 259 260#ifndef USS820_REG_STRIDE 261#define USS820_REG_STRIDE 1 262#endif 263 264#define USS820_READ_1(sc, reg) \ 265 bus_space_read_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg) * USS820_REG_STRIDE) 266 267#define USS820_WRITE_1(sc, reg, data) \ 268 bus_space_write_1((sc)->sc_io_tag, (sc)->sc_io_hdl, (reg) * USS820_REG_STRIDE, (data)) 269 270struct uss820dci_td; 271struct uss820dci_softc; 272 273typedef uint8_t (uss820dci_cmd_t)(struct uss820dci_softc *, struct uss820dci_td *td); 274 275struct uss820dci_td { 276 struct uss820dci_td *obj_next; 277 uss820dci_cmd_t *func; 278 struct usb_page_cache *pc; 279 uint32_t offset; 280 uint32_t remainder; 281 uint16_t max_packet_size; 282 uint8_t ep_index; 283 uint8_t error:1; 284 uint8_t alt_next:1; 285 uint8_t short_pkt:1; 286 uint8_t support_multi_buffer:1; 287 uint8_t did_stall:1; 288 uint8_t did_enable:1; 289}; 290 291struct uss820_std_temp { 292 uss820dci_cmd_t *func; 293 struct usb_page_cache *pc; 294 struct uss820dci_td *td; 295 struct uss820dci_td *td_next; 296 uint32_t len; 297 uint32_t offset; 298 uint16_t max_frame_size; 299 uint8_t short_pkt; 300 /* 301 * short_pkt = 0: transfer should be short terminated 302 * short_pkt = 1: transfer should not be short terminated 303 */ 304 uint8_t setup_alt_next; 305 uint8_t did_stall; 306}; 307 308struct uss820dci_config_desc { 309 struct usb_config_descriptor confd; 310 struct usb_interface_descriptor ifcd; 311 struct usb_endpoint_descriptor endpd; 312} __packed; 313 314union uss820_hub_temp { 315 uWord wValue; 316 struct usb_port_status ps; 317}; 318 319struct uss820_flags { 320 uint8_t change_connect:1; 321 uint8_t change_suspend:1; 322 uint8_t status_suspend:1; /* set if suspended */ 323 uint8_t status_vbus:1; /* set if present */ 324 uint8_t status_bus_reset:1; /* set if reset complete */ 325 uint8_t clocks_off:1; 326 uint8_t port_powered:1; 327 uint8_t port_enabled:1; 328 uint8_t d_pulled_up:1; 329 uint8_t mcsr_feat:1; 330}; 331 332struct uss820dci_softc { 333 struct usb_bus sc_bus; 334 union uss820_hub_temp sc_hub_temp; 335 336 struct usb_device *sc_devices[USS820_MAX_DEVICES]; 337 struct resource *sc_io_res; 338 struct resource *sc_irq_res; 339 void *sc_intr_hdl; 340 bus_size_t sc_io_size; 341 bus_space_tag_t sc_io_tag; 342 bus_space_handle_t sc_io_hdl; 343 344 uint32_t sc_xfer_complete; 345 346 uint8_t sc_rt_addr; /* root HUB address */ 347 uint8_t sc_dv_addr; /* device address */ 348 uint8_t sc_conf; /* root HUB config */ 349 350 uint8_t sc_hub_idata[1]; 351 352 struct uss820_flags sc_flags; 353}; 354 355/* prototypes */ 356 357usb_error_t uss820dci_init(struct uss820dci_softc *sc); 358void uss820dci_uninit(struct uss820dci_softc *sc); 359driver_filter_t uss820dci_filter_interrupt; 360driver_intr_t uss820dci_interrupt; 361 362#endif /* _USS820_DCI_H_ */ 363