1/* $OpenBSD: ubsec.c,v 1.115 2002/09/24 18:33:26 jason Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 2000 Jason L. Wright (jason@thought.net) 7 * Copyright (c) 2000 Theo de Raadt (deraadt@openbsd.org) 8 * Copyright (c) 2001 Patrik Lindergren (patrik@ipunplugged.com) 9 * 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Jason L. Wright 23 * 4. The name of the author may not be used to endorse or promote products 24 * derived from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 29 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 34 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 35 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 * 38 * Effort sponsored in part by the Defense Advanced Research Projects 39 * Agency (DARPA) and Air Force Research Laboratory, Air Force 40 * Materiel Command, USAF, under agreement number F30602-01-2-0537. 41 */ 42 43#include <sys/cdefs.h> 44__FBSDID("$FreeBSD$"); 45 46/* 47 * uBsec 5[56]01, 58xx hardware crypto accelerator 48 */ 49 50#include "opt_ubsec.h" 51 52#include <sys/param.h> 53#include <sys/systm.h> 54#include <sys/proc.h> 55#include <sys/errno.h> 56#include <sys/malloc.h> 57#include <sys/kernel.h> 58#include <sys/module.h> 59#include <sys/mbuf.h> 60#include <sys/lock.h> 61#include <sys/mutex.h> 62#include <sys/sysctl.h> 63#include <sys/endian.h> 64 65#include <vm/vm.h> 66#include <vm/pmap.h> 67 68#include <machine/bus.h> 69#include <machine/resource.h> 70#include <sys/bus.h> 71#include <sys/rman.h> 72 73#include <crypto/sha1.h> 74#include <opencrypto/cryptodev.h> 75#include <opencrypto/cryptosoft.h> 76#include <sys/md5.h> 77#include <sys/random.h> 78#include <sys/kobj.h> 79 80#include "cryptodev_if.h" 81 82#include <dev/pci/pcivar.h> 83#include <dev/pci/pcireg.h> 84 85/* grr, #defines for gratuitous incompatibility in queue.h */ 86#define SIMPLEQ_HEAD STAILQ_HEAD 87#define SIMPLEQ_ENTRY STAILQ_ENTRY 88#define SIMPLEQ_INIT STAILQ_INIT 89#define SIMPLEQ_INSERT_TAIL STAILQ_INSERT_TAIL 90#define SIMPLEQ_EMPTY STAILQ_EMPTY 91#define SIMPLEQ_FIRST STAILQ_FIRST 92#define SIMPLEQ_REMOVE_HEAD STAILQ_REMOVE_HEAD 93#define SIMPLEQ_FOREACH STAILQ_FOREACH 94/* ditto for endian.h */ 95#define letoh16(x) le16toh(x) 96#define letoh32(x) le32toh(x) 97 98#ifdef UBSEC_RNDTEST 99#include <dev/rndtest/rndtest.h> 100#endif 101#include <dev/ubsec/ubsecreg.h> 102#include <dev/ubsec/ubsecvar.h> 103 104/* 105 * Prototypes and count for the pci_device structure 106 */ 107static int ubsec_probe(device_t); 108static int ubsec_attach(device_t); 109static int ubsec_detach(device_t); 110static int ubsec_suspend(device_t); 111static int ubsec_resume(device_t); 112static int ubsec_shutdown(device_t); 113 114static int ubsec_newsession(device_t, crypto_session_t, struct cryptoini *); 115static int ubsec_process(device_t, struct cryptop *, int); 116static int ubsec_kprocess(device_t, struct cryptkop *, int); 117 118static device_method_t ubsec_methods[] = { 119 /* Device interface */ 120 DEVMETHOD(device_probe, ubsec_probe), 121 DEVMETHOD(device_attach, ubsec_attach), 122 DEVMETHOD(device_detach, ubsec_detach), 123 DEVMETHOD(device_suspend, ubsec_suspend), 124 DEVMETHOD(device_resume, ubsec_resume), 125 DEVMETHOD(device_shutdown, ubsec_shutdown), 126 127 /* crypto device methods */ 128 DEVMETHOD(cryptodev_newsession, ubsec_newsession), 129 DEVMETHOD(cryptodev_process, ubsec_process), 130 DEVMETHOD(cryptodev_kprocess, ubsec_kprocess), 131 132 DEVMETHOD_END 133}; 134static driver_t ubsec_driver = { 135 "ubsec", 136 ubsec_methods, 137 sizeof (struct ubsec_softc) 138}; 139static devclass_t ubsec_devclass; 140 141DRIVER_MODULE(ubsec, pci, ubsec_driver, ubsec_devclass, 0, 0); 142MODULE_DEPEND(ubsec, crypto, 1, 1, 1); 143#ifdef UBSEC_RNDTEST 144MODULE_DEPEND(ubsec, rndtest, 1, 1, 1); 145#endif 146 147static void ubsec_intr(void *); 148static void ubsec_callback(struct ubsec_softc *, struct ubsec_q *); 149static void ubsec_feed(struct ubsec_softc *); 150static void ubsec_mcopy(struct mbuf *, struct mbuf *, int, int); 151static void ubsec_callback2(struct ubsec_softc *, struct ubsec_q2 *); 152static int ubsec_feed2(struct ubsec_softc *); 153static void ubsec_rng(void *); 154static int ubsec_dma_malloc(struct ubsec_softc *, bus_size_t, 155 struct ubsec_dma_alloc *, int); 156#define ubsec_dma_sync(_dma, _flags) \ 157 bus_dmamap_sync((_dma)->dma_tag, (_dma)->dma_map, (_flags)) 158static void ubsec_dma_free(struct ubsec_softc *, struct ubsec_dma_alloc *); 159static int ubsec_dmamap_aligned(struct ubsec_operand *op); 160 161static void ubsec_reset_board(struct ubsec_softc *sc); 162static void ubsec_init_board(struct ubsec_softc *sc); 163static void ubsec_init_pciregs(device_t dev); 164static void ubsec_totalreset(struct ubsec_softc *sc); 165 166static int ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q); 167 168static int ubsec_kprocess_modexp_hw(struct ubsec_softc *, struct cryptkop *, int); 169static int ubsec_kprocess_modexp_sw(struct ubsec_softc *, struct cryptkop *, int); 170static int ubsec_kprocess_rsapriv(struct ubsec_softc *, struct cryptkop *, int); 171static void ubsec_kfree(struct ubsec_softc *, struct ubsec_q2 *); 172static int ubsec_ksigbits(struct crparam *); 173static void ubsec_kshift_r(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 174static void ubsec_kshift_l(u_int, u_int8_t *, u_int, u_int8_t *, u_int); 175 176static SYSCTL_NODE(_hw, OID_AUTO, ubsec, CTLFLAG_RD, 0, 177 "Broadcom driver parameters"); 178 179#ifdef UBSEC_DEBUG 180static void ubsec_dump_pb(volatile struct ubsec_pktbuf *); 181static void ubsec_dump_mcr(struct ubsec_mcr *); 182static void ubsec_dump_ctx2(struct ubsec_ctx_keyop *); 183 184static int ubsec_debug = 0; 185SYSCTL_INT(_hw_ubsec, OID_AUTO, debug, CTLFLAG_RW, &ubsec_debug, 186 0, "control debugging msgs"); 187#endif 188 189#define READ_REG(sc,r) \ 190 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (r)) 191 192#define WRITE_REG(sc,reg,val) \ 193 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, reg, val) 194 195#define SWAP32(x) (x) = htole32(ntohl((x))) 196#define HTOLE32(x) (x) = htole32(x) 197 198struct ubsec_stats ubsecstats; 199SYSCTL_STRUCT(_hw_ubsec, OID_AUTO, stats, CTLFLAG_RD, &ubsecstats, 200 ubsec_stats, "driver statistics"); 201 202static int 203ubsec_probe(device_t dev) 204{ 205 if (pci_get_vendor(dev) == PCI_VENDOR_SUN && 206 (pci_get_device(dev) == PCI_PRODUCT_SUN_5821 || 207 pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K)) 208 return (BUS_PROBE_DEFAULT); 209 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 210 (pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5501 || 211 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601)) 212 return (BUS_PROBE_DEFAULT); 213 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 214 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5801 || 215 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 216 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805 || 217 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820 || 218 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 219 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 220 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 || 221 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825 222 )) 223 return (BUS_PROBE_DEFAULT); 224 return (ENXIO); 225} 226 227static const char* 228ubsec_partname(struct ubsec_softc *sc) 229{ 230 /* XXX sprintf numbers when not decoded */ 231 switch (pci_get_vendor(sc->sc_dev)) { 232 case PCI_VENDOR_BROADCOM: 233 switch (pci_get_device(sc->sc_dev)) { 234 case PCI_PRODUCT_BROADCOM_5801: return "Broadcom 5801"; 235 case PCI_PRODUCT_BROADCOM_5802: return "Broadcom 5802"; 236 case PCI_PRODUCT_BROADCOM_5805: return "Broadcom 5805"; 237 case PCI_PRODUCT_BROADCOM_5820: return "Broadcom 5820"; 238 case PCI_PRODUCT_BROADCOM_5821: return "Broadcom 5821"; 239 case PCI_PRODUCT_BROADCOM_5822: return "Broadcom 5822"; 240 case PCI_PRODUCT_BROADCOM_5823: return "Broadcom 5823"; 241 case PCI_PRODUCT_BROADCOM_5825: return "Broadcom 5825"; 242 } 243 return "Broadcom unknown-part"; 244 case PCI_VENDOR_BLUESTEEL: 245 switch (pci_get_device(sc->sc_dev)) { 246 case PCI_PRODUCT_BLUESTEEL_5601: return "Bluesteel 5601"; 247 } 248 return "Bluesteel unknown-part"; 249 case PCI_VENDOR_SUN: 250 switch (pci_get_device(sc->sc_dev)) { 251 case PCI_PRODUCT_SUN_5821: return "Sun Crypto 5821"; 252 case PCI_PRODUCT_SUN_SCA1K: return "Sun Crypto 1K"; 253 } 254 return "Sun unknown-part"; 255 } 256 return "Unknown-vendor unknown-part"; 257} 258 259static void 260default_harvest(struct rndtest_state *rsp, void *buf, u_int count) 261{ 262 /* MarkM: FIX!! Check that this does not swamp the harvester! */ 263 random_harvest_queue(buf, count, RANDOM_PURE_UBSEC); 264} 265 266static int 267ubsec_attach(device_t dev) 268{ 269 struct ubsec_softc *sc = device_get_softc(dev); 270 struct ubsec_dma *dmap; 271 u_int32_t i; 272 int rid; 273 274 bzero(sc, sizeof (*sc)); 275 sc->sc_dev = dev; 276 277 SIMPLEQ_INIT(&sc->sc_queue); 278 SIMPLEQ_INIT(&sc->sc_qchip); 279 SIMPLEQ_INIT(&sc->sc_queue2); 280 SIMPLEQ_INIT(&sc->sc_qchip2); 281 SIMPLEQ_INIT(&sc->sc_q2free); 282 283 /* XXX handle power management */ 284 285 sc->sc_statmask = BS_STAT_MCR1_DONE | BS_STAT_DMAERR; 286 287 if (pci_get_vendor(dev) == PCI_VENDOR_BLUESTEEL && 288 pci_get_device(dev) == PCI_PRODUCT_BLUESTEEL_5601) 289 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 290 291 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 292 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5802 || 293 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5805)) 294 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG; 295 296 if (pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 297 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5820) 298 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 299 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 300 301 if ((pci_get_vendor(dev) == PCI_VENDOR_BROADCOM && 302 (pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5821 || 303 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5822 || 304 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5823 || 305 pci_get_device(dev) == PCI_PRODUCT_BROADCOM_5825)) || 306 (pci_get_vendor(dev) == PCI_VENDOR_SUN && 307 (pci_get_device(dev) == PCI_PRODUCT_SUN_SCA1K || 308 pci_get_device(dev) == PCI_PRODUCT_SUN_5821))) { 309 /* NB: the 5821/5822 defines some additional status bits */ 310 sc->sc_statmask |= BS_STAT_MCR1_ALLEMPTY | 311 BS_STAT_MCR2_ALLEMPTY; 312 sc->sc_flags |= UBS_FLAGS_KEY | UBS_FLAGS_RNG | 313 UBS_FLAGS_LONGCTX | UBS_FLAGS_HWNORM | UBS_FLAGS_BIGKEY; 314 } 315 316 pci_enable_busmaster(dev); 317 318 /* 319 * Setup memory-mapping of PCI registers. 320 */ 321 rid = BS_BAR; 322 sc->sc_sr = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 323 RF_ACTIVE); 324 if (sc->sc_sr == NULL) { 325 device_printf(dev, "cannot map register space\n"); 326 goto bad; 327 } 328 sc->sc_st = rman_get_bustag(sc->sc_sr); 329 sc->sc_sh = rman_get_bushandle(sc->sc_sr); 330 331 /* 332 * Arrange interrupt line. 333 */ 334 rid = 0; 335 sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 336 RF_SHAREABLE|RF_ACTIVE); 337 if (sc->sc_irq == NULL) { 338 device_printf(dev, "could not map interrupt\n"); 339 goto bad1; 340 } 341 /* 342 * NB: Network code assumes we are blocked with splimp() 343 * so make sure the IRQ is mapped appropriately. 344 */ 345 if (bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_NET | INTR_MPSAFE, 346 NULL, ubsec_intr, sc, &sc->sc_ih)) { 347 device_printf(dev, "could not establish interrupt\n"); 348 goto bad2; 349 } 350 351 sc->sc_cid = crypto_get_driverid(dev, sizeof(struct ubsec_session), 352 CRYPTOCAP_F_HARDWARE); 353 if (sc->sc_cid < 0) { 354 device_printf(dev, "could not get crypto driver id\n"); 355 goto bad3; 356 } 357 358 /* 359 * Setup DMA descriptor area. 360 */ 361 if (bus_dma_tag_create(bus_get_dma_tag(dev), /* parent */ 362 1, 0, /* alignment, bounds */ 363 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 364 BUS_SPACE_MAXADDR, /* highaddr */ 365 NULL, NULL, /* filter, filterarg */ 366 0x3ffff, /* maxsize */ 367 UBS_MAX_SCATTER, /* nsegments */ 368 0xffff, /* maxsegsize */ 369 BUS_DMA_ALLOCNOW, /* flags */ 370 NULL, NULL, /* lockfunc, lockarg */ 371 &sc->sc_dmat)) { 372 device_printf(dev, "cannot allocate DMA tag\n"); 373 goto bad4; 374 } 375 SIMPLEQ_INIT(&sc->sc_freequeue); 376 dmap = sc->sc_dmaa; 377 for (i = 0; i < UBS_MAX_NQUEUE; i++, dmap++) { 378 struct ubsec_q *q; 379 380 q = (struct ubsec_q *)malloc(sizeof(struct ubsec_q), 381 M_DEVBUF, M_NOWAIT); 382 if (q == NULL) { 383 device_printf(dev, "cannot allocate queue buffers\n"); 384 break; 385 } 386 387 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_dmachunk), 388 &dmap->d_alloc, 0)) { 389 device_printf(dev, "cannot allocate dma buffers\n"); 390 free(q, M_DEVBUF); 391 break; 392 } 393 dmap->d_dma = (struct ubsec_dmachunk *)dmap->d_alloc.dma_vaddr; 394 395 q->q_dma = dmap; 396 sc->sc_queuea[i] = q; 397 398 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 399 } 400 mtx_init(&sc->sc_mcr1lock, device_get_nameunit(dev), 401 "mcr1 operations", MTX_DEF); 402 mtx_init(&sc->sc_freeqlock, device_get_nameunit(dev), 403 "mcr1 free q", MTX_DEF); 404 405 device_printf(sc->sc_dev, "%s\n", ubsec_partname(sc)); 406 407 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0); 408 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0); 409 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0); 410 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0); 411 412 /* 413 * Reset Broadcom chip 414 */ 415 ubsec_reset_board(sc); 416 417 /* 418 * Init Broadcom specific PCI settings 419 */ 420 ubsec_init_pciregs(dev); 421 422 /* 423 * Init Broadcom chip 424 */ 425 ubsec_init_board(sc); 426 427#ifndef UBSEC_NO_RNG 428 if (sc->sc_flags & UBS_FLAGS_RNG) { 429 sc->sc_statmask |= BS_STAT_MCR2_DONE; 430#ifdef UBSEC_RNDTEST 431 sc->sc_rndtest = rndtest_attach(dev); 432 if (sc->sc_rndtest) 433 sc->sc_harvest = rndtest_harvest; 434 else 435 sc->sc_harvest = default_harvest; 436#else 437 sc->sc_harvest = default_harvest; 438#endif 439 440 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 441 &sc->sc_rng.rng_q.q_mcr, 0)) 442 goto skip_rng; 443 444 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rngbypass), 445 &sc->sc_rng.rng_q.q_ctx, 0)) { 446 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 447 goto skip_rng; 448 } 449 450 if (ubsec_dma_malloc(sc, sizeof(u_int32_t) * 451 UBSEC_RNG_BUFSIZ, &sc->sc_rng.rng_buf, 0)) { 452 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 453 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 454 goto skip_rng; 455 } 456 457 if (hz >= 100) 458 sc->sc_rnghz = hz / 100; 459 else 460 sc->sc_rnghz = 1; 461 callout_init(&sc->sc_rngto, 1); 462 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 463skip_rng: 464 ; 465 } 466#endif /* UBSEC_NO_RNG */ 467 mtx_init(&sc->sc_mcr2lock, device_get_nameunit(dev), 468 "mcr2 operations", MTX_DEF); 469 470 if (sc->sc_flags & UBS_FLAGS_KEY) { 471 sc->sc_statmask |= BS_STAT_MCR2_DONE; 472 473 crypto_kregister(sc->sc_cid, CRK_MOD_EXP, 0); 474#if 0 475 crypto_kregister(sc->sc_cid, CRK_MOD_EXP_CRT, 0); 476#endif 477 } 478 gone_in_dev(dev, 13, "Does not support modern crypto algorithms"); 479 return (0); 480bad4: 481 crypto_unregister_all(sc->sc_cid); 482bad3: 483 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 484bad2: 485 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 486bad1: 487 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 488bad: 489 return (ENXIO); 490} 491 492/* 493 * Detach a device that successfully probed. 494 */ 495static int 496ubsec_detach(device_t dev) 497{ 498 struct ubsec_softc *sc = device_get_softc(dev); 499 500 /* XXX wait/abort active ops */ 501 502 /* disable interrupts */ 503 WRITE_REG(sc, BS_CTRL, READ_REG(sc, BS_CTRL) &~ 504 (BS_CTRL_MCR2INT | BS_CTRL_MCR1INT | BS_CTRL_DMAERR)); 505 506 callout_stop(&sc->sc_rngto); 507 508 crypto_unregister_all(sc->sc_cid); 509 510#ifdef UBSEC_RNDTEST 511 if (sc->sc_rndtest) 512 rndtest_detach(sc->sc_rndtest); 513#endif 514 515 while (!SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 516 struct ubsec_q *q; 517 518 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 519 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); 520 ubsec_dma_free(sc, &q->q_dma->d_alloc); 521 free(q, M_DEVBUF); 522 } 523 mtx_destroy(&sc->sc_mcr1lock); 524 mtx_destroy(&sc->sc_freeqlock); 525#ifndef UBSEC_NO_RNG 526 if (sc->sc_flags & UBS_FLAGS_RNG) { 527 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_mcr); 528 ubsec_dma_free(sc, &sc->sc_rng.rng_q.q_ctx); 529 ubsec_dma_free(sc, &sc->sc_rng.rng_buf); 530 } 531#endif /* UBSEC_NO_RNG */ 532 mtx_destroy(&sc->sc_mcr2lock); 533 534 bus_generic_detach(dev); 535 bus_teardown_intr(dev, sc->sc_irq, sc->sc_ih); 536 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq); 537 538 bus_dma_tag_destroy(sc->sc_dmat); 539 bus_release_resource(dev, SYS_RES_MEMORY, BS_BAR, sc->sc_sr); 540 541 return (0); 542} 543 544/* 545 * Stop all chip i/o so that the kernel's probe routines don't 546 * get confused by errant DMAs when rebooting. 547 */ 548static int 549ubsec_shutdown(device_t dev) 550{ 551#ifdef notyet 552 ubsec_stop(device_get_softc(dev)); 553#endif 554 return (0); 555} 556 557/* 558 * Device suspend routine. 559 */ 560static int 561ubsec_suspend(device_t dev) 562{ 563 struct ubsec_softc *sc = device_get_softc(dev); 564 565#ifdef notyet 566 /* XXX stop the device and save PCI settings */ 567#endif 568 sc->sc_suspended = 1; 569 570 return (0); 571} 572 573static int 574ubsec_resume(device_t dev) 575{ 576 struct ubsec_softc *sc = device_get_softc(dev); 577 578#ifdef notyet 579 /* XXX retore PCI settings and start the device */ 580#endif 581 sc->sc_suspended = 0; 582 return (0); 583} 584 585/* 586 * UBSEC Interrupt routine 587 */ 588static void 589ubsec_intr(void *arg) 590{ 591 struct ubsec_softc *sc = arg; 592 volatile u_int32_t stat; 593 struct ubsec_q *q; 594 struct ubsec_dma *dmap; 595 int npkts = 0, i; 596 597 stat = READ_REG(sc, BS_STAT); 598 stat &= sc->sc_statmask; 599 if (stat == 0) 600 return; 601 602 WRITE_REG(sc, BS_STAT, stat); /* IACK */ 603 604 /* 605 * Check to see if we have any packets waiting for us 606 */ 607 if ((stat & BS_STAT_MCR1_DONE)) { 608 mtx_lock(&sc->sc_mcr1lock); 609 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 610 q = SIMPLEQ_FIRST(&sc->sc_qchip); 611 dmap = q->q_dma; 612 613 if ((dmap->d_dma->d_mcr.mcr_flags & htole16(UBS_MCR_DONE)) == 0) 614 break; 615 616 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); 617 618 npkts = q->q_nstacked_mcrs; 619 sc->sc_nqchip -= 1+npkts; 620 /* 621 * search for further sc_qchip ubsec_q's that share 622 * the same MCR, and complete them too, they must be 623 * at the top. 624 */ 625 for (i = 0; i < npkts; i++) { 626 if(q->q_stacked_mcr[i]) { 627 ubsec_callback(sc, q->q_stacked_mcr[i]); 628 } else { 629 break; 630 } 631 } 632 ubsec_callback(sc, q); 633 } 634 /* 635 * Don't send any more packet to chip if there has been 636 * a DMAERR. 637 */ 638 if (!(stat & BS_STAT_DMAERR)) 639 ubsec_feed(sc); 640 mtx_unlock(&sc->sc_mcr1lock); 641 } 642 643 /* 644 * Check to see if we have any key setups/rng's waiting for us 645 */ 646 if ((sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) && 647 (stat & BS_STAT_MCR2_DONE)) { 648 struct ubsec_q2 *q2; 649 struct ubsec_mcr *mcr; 650 651 mtx_lock(&sc->sc_mcr2lock); 652 while (!SIMPLEQ_EMPTY(&sc->sc_qchip2)) { 653 q2 = SIMPLEQ_FIRST(&sc->sc_qchip2); 654 655 ubsec_dma_sync(&q2->q_mcr, 656 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 657 658 mcr = (struct ubsec_mcr *)q2->q_mcr.dma_vaddr; 659 if ((mcr->mcr_flags & htole16(UBS_MCR_DONE)) == 0) { 660 ubsec_dma_sync(&q2->q_mcr, 661 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 662 break; 663 } 664 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip2, q_next); 665 ubsec_callback2(sc, q2); 666 /* 667 * Don't send any more packet to chip if there has been 668 * a DMAERR. 669 */ 670 if (!(stat & BS_STAT_DMAERR)) 671 ubsec_feed2(sc); 672 } 673 mtx_unlock(&sc->sc_mcr2lock); 674 } 675 676 /* 677 * Check to see if we got any DMA Error 678 */ 679 if (stat & BS_STAT_DMAERR) { 680#ifdef UBSEC_DEBUG 681 if (ubsec_debug) { 682 volatile u_int32_t a = READ_REG(sc, BS_ERR); 683 684 printf("dmaerr %s@%08x\n", 685 (a & BS_ERR_READ) ? "read" : "write", 686 a & BS_ERR_ADDR); 687 } 688#endif /* UBSEC_DEBUG */ 689 ubsecstats.hst_dmaerr++; 690 mtx_lock(&sc->sc_mcr1lock); 691 ubsec_totalreset(sc); 692 ubsec_feed(sc); 693 mtx_unlock(&sc->sc_mcr1lock); 694 } 695 696 if (sc->sc_needwakeup) { /* XXX check high watermark */ 697 int wakeup; 698 699 mtx_lock(&sc->sc_freeqlock); 700 wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ); 701#ifdef UBSEC_DEBUG 702 if (ubsec_debug) 703 device_printf(sc->sc_dev, "wakeup crypto (%x)\n", 704 sc->sc_needwakeup); 705#endif /* UBSEC_DEBUG */ 706 sc->sc_needwakeup &= ~wakeup; 707 mtx_unlock(&sc->sc_freeqlock); 708 crypto_unblock(sc->sc_cid, wakeup); 709 } 710} 711 712/* 713 * ubsec_feed() - aggregate and post requests to chip 714 */ 715static void 716ubsec_feed(struct ubsec_softc *sc) 717{ 718 struct ubsec_q *q, *q2; 719 int npkts, i; 720 void *v; 721 u_int32_t stat; 722 723 /* 724 * Decide how many ops to combine in a single MCR. We cannot 725 * aggregate more than UBS_MAX_AGGR because this is the number 726 * of slots defined in the data structure. Note that 727 * aggregation only happens if ops are marked batch'able. 728 * Aggregating ops reduces the number of interrupts to the host 729 * but also (potentially) increases the latency for processing 730 * completed ops as we only get an interrupt when all aggregated 731 * ops have completed. 732 */ 733 if (sc->sc_nqueue == 0) 734 return; 735 if (sc->sc_nqueue > 1) { 736 npkts = 0; 737 SIMPLEQ_FOREACH(q, &sc->sc_queue, q_next) { 738 npkts++; 739 if ((q->q_crp->crp_flags & CRYPTO_F_BATCH) == 0) 740 break; 741 } 742 } else 743 npkts = 1; 744 /* 745 * Check device status before going any further. 746 */ 747 if ((stat = READ_REG(sc, BS_STAT)) & (BS_STAT_MCR1_FULL | BS_STAT_DMAERR)) { 748 if (stat & BS_STAT_DMAERR) { 749 ubsec_totalreset(sc); 750 ubsecstats.hst_dmaerr++; 751 } else 752 ubsecstats.hst_mcr1full++; 753 return; 754 } 755 if (sc->sc_nqueue > ubsecstats.hst_maxqueue) 756 ubsecstats.hst_maxqueue = sc->sc_nqueue; 757 if (npkts > UBS_MAX_AGGR) 758 npkts = UBS_MAX_AGGR; 759 if (npkts < 2) /* special case 1 op */ 760 goto feed1; 761 762 ubsecstats.hst_totbatch += npkts-1; 763#ifdef UBSEC_DEBUG 764 if (ubsec_debug) 765 printf("merging %d records\n", npkts); 766#endif /* UBSEC_DEBUG */ 767 768 q = SIMPLEQ_FIRST(&sc->sc_queue); 769 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 770 --sc->sc_nqueue; 771 772 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 773 if (q->q_dst_map != NULL) 774 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 775 776 q->q_nstacked_mcrs = npkts - 1; /* Number of packets stacked */ 777 778 for (i = 0; i < q->q_nstacked_mcrs; i++) { 779 q2 = SIMPLEQ_FIRST(&sc->sc_queue); 780 bus_dmamap_sync(sc->sc_dmat, q2->q_src_map, 781 BUS_DMASYNC_PREWRITE); 782 if (q2->q_dst_map != NULL) 783 bus_dmamap_sync(sc->sc_dmat, q2->q_dst_map, 784 BUS_DMASYNC_PREREAD); 785 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 786 --sc->sc_nqueue; 787 788 v = (void*)(((char *)&q2->q_dma->d_dma->d_mcr) + sizeof(struct ubsec_mcr) - 789 sizeof(struct ubsec_mcr_add)); 790 bcopy(v, &q->q_dma->d_dma->d_mcradd[i], sizeof(struct ubsec_mcr_add)); 791 q->q_stacked_mcr[i] = q2; 792 } 793 q->q_dma->d_dma->d_mcr.mcr_pkts = htole16(npkts); 794 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 795 sc->sc_nqchip += npkts; 796 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 797 ubsecstats.hst_maxqchip = sc->sc_nqchip; 798 ubsec_dma_sync(&q->q_dma->d_alloc, 799 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 800 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 801 offsetof(struct ubsec_dmachunk, d_mcr)); 802 return; 803feed1: 804 q = SIMPLEQ_FIRST(&sc->sc_queue); 805 806 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_PREWRITE); 807 if (q->q_dst_map != NULL) 808 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, BUS_DMASYNC_PREREAD); 809 ubsec_dma_sync(&q->q_dma->d_alloc, 810 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 811 812 WRITE_REG(sc, BS_MCR1, q->q_dma->d_alloc.dma_paddr + 813 offsetof(struct ubsec_dmachunk, d_mcr)); 814#ifdef UBSEC_DEBUG 815 if (ubsec_debug) 816 printf("feed1: q->chip %p %08x stat %08x\n", 817 q, (u_int32_t)vtophys(&q->q_dma->d_dma->d_mcr), 818 stat); 819#endif /* UBSEC_DEBUG */ 820 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue, q_next); 821 --sc->sc_nqueue; 822 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip, q, q_next); 823 sc->sc_nqchip++; 824 if (sc->sc_nqchip > ubsecstats.hst_maxqchip) 825 ubsecstats.hst_maxqchip = sc->sc_nqchip; 826 return; 827} 828 829static void 830ubsec_setup_enckey(struct ubsec_session *ses, int algo, caddr_t key) 831{ 832 833 /* Go ahead and compute key in ubsec's byte order */ 834 if (algo == CRYPTO_DES_CBC) { 835 bcopy(key, &ses->ses_deskey[0], 8); 836 bcopy(key, &ses->ses_deskey[2], 8); 837 bcopy(key, &ses->ses_deskey[4], 8); 838 } else 839 bcopy(key, ses->ses_deskey, 24); 840 841 SWAP32(ses->ses_deskey[0]); 842 SWAP32(ses->ses_deskey[1]); 843 SWAP32(ses->ses_deskey[2]); 844 SWAP32(ses->ses_deskey[3]); 845 SWAP32(ses->ses_deskey[4]); 846 SWAP32(ses->ses_deskey[5]); 847} 848 849static void 850ubsec_setup_mackey(struct ubsec_session *ses, int algo, caddr_t key, int klen) 851{ 852 MD5_CTX md5ctx; 853 SHA1_CTX sha1ctx; 854 int i; 855 856 for (i = 0; i < klen; i++) 857 key[i] ^= HMAC_IPAD_VAL; 858 859 if (algo == CRYPTO_MD5_HMAC) { 860 MD5Init(&md5ctx); 861 MD5Update(&md5ctx, key, klen); 862 MD5Update(&md5ctx, hmac_ipad_buffer, MD5_BLOCK_LEN - klen); 863 bcopy(md5ctx.state, ses->ses_hminner, sizeof(md5ctx.state)); 864 } else { 865 SHA1Init(&sha1ctx); 866 SHA1Update(&sha1ctx, key, klen); 867 SHA1Update(&sha1ctx, hmac_ipad_buffer, 868 SHA1_BLOCK_LEN - klen); 869 bcopy(sha1ctx.h.b32, ses->ses_hminner, sizeof(sha1ctx.h.b32)); 870 } 871 872 for (i = 0; i < klen; i++) 873 key[i] ^= (HMAC_IPAD_VAL ^ HMAC_OPAD_VAL); 874 875 if (algo == CRYPTO_MD5_HMAC) { 876 MD5Init(&md5ctx); 877 MD5Update(&md5ctx, key, klen); 878 MD5Update(&md5ctx, hmac_opad_buffer, MD5_BLOCK_LEN - klen); 879 bcopy(md5ctx.state, ses->ses_hmouter, sizeof(md5ctx.state)); 880 } else { 881 SHA1Init(&sha1ctx); 882 SHA1Update(&sha1ctx, key, klen); 883 SHA1Update(&sha1ctx, hmac_opad_buffer, 884 SHA1_BLOCK_LEN - klen); 885 bcopy(sha1ctx.h.b32, ses->ses_hmouter, sizeof(sha1ctx.h.b32)); 886 } 887 888 for (i = 0; i < klen; i++) 889 key[i] ^= HMAC_OPAD_VAL; 890} 891 892/* 893 * Allocate a new 'session' and return an encoded session id. 'sidp' 894 * contains our registration id, and should contain an encoded session 895 * id on successful allocation. 896 */ 897static int 898ubsec_newsession(device_t dev, crypto_session_t cses, struct cryptoini *cri) 899{ 900 struct ubsec_softc *sc = device_get_softc(dev); 901 struct cryptoini *c, *encini = NULL, *macini = NULL; 902 struct ubsec_session *ses = NULL; 903 904 if (cri == NULL || sc == NULL) 905 return (EINVAL); 906 907 for (c = cri; c != NULL; c = c->cri_next) { 908 if (c->cri_alg == CRYPTO_MD5_HMAC || 909 c->cri_alg == CRYPTO_SHA1_HMAC) { 910 if (macini) 911 return (EINVAL); 912 macini = c; 913 } else if (c->cri_alg == CRYPTO_DES_CBC || 914 c->cri_alg == CRYPTO_3DES_CBC) { 915 if (encini) 916 return (EINVAL); 917 encini = c; 918 } else 919 return (EINVAL); 920 } 921 if (encini == NULL && macini == NULL) 922 return (EINVAL); 923 924 ses = crypto_get_driver_session(cses); 925 if (encini) { 926 /* get an IV, network byte order */ 927 /* XXX may read fewer than requested */ 928 read_random(ses->ses_iv, sizeof(ses->ses_iv)); 929 930 if (encini->cri_key != NULL) { 931 ubsec_setup_enckey(ses, encini->cri_alg, 932 encini->cri_key); 933 } 934 } 935 936 if (macini) { 937 ses->ses_mlen = macini->cri_mlen; 938 if (ses->ses_mlen == 0) { 939 if (macini->cri_alg == CRYPTO_MD5_HMAC) 940 ses->ses_mlen = MD5_HASH_LEN; 941 else 942 ses->ses_mlen = SHA1_HASH_LEN; 943 } 944 945 if (macini->cri_key != NULL) { 946 ubsec_setup_mackey(ses, macini->cri_alg, 947 macini->cri_key, macini->cri_klen / 8); 948 } 949 } 950 951 return (0); 952} 953 954static void 955ubsec_op_cb(void *arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error) 956{ 957 struct ubsec_operand *op = arg; 958 959 KASSERT(nsegs <= UBS_MAX_SCATTER, 960 ("Too many DMA segments returned when mapping operand")); 961#ifdef UBSEC_DEBUG 962 if (ubsec_debug) 963 printf("ubsec_op_cb: mapsize %u nsegs %d error %d\n", 964 (u_int) mapsize, nsegs, error); 965#endif 966 if (error != 0) 967 return; 968 op->mapsize = mapsize; 969 op->nsegs = nsegs; 970 bcopy(seg, op->segs, nsegs * sizeof (seg[0])); 971} 972 973static int 974ubsec_process(device_t dev, struct cryptop *crp, int hint) 975{ 976 struct ubsec_softc *sc = device_get_softc(dev); 977 struct ubsec_q *q = NULL; 978 int err = 0, i, j, nicealign; 979 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd; 980 int encoffset = 0, macoffset = 0, cpskip, cpoffset; 981 int sskip, dskip, stheend, dtheend; 982 int16_t coffset; 983 struct ubsec_session *ses; 984 struct ubsec_pktctx ctx; 985 struct ubsec_dma *dmap = NULL; 986 987 if (crp == NULL || crp->crp_callback == NULL || sc == NULL) { 988 ubsecstats.hst_invalid++; 989 return (EINVAL); 990 } 991 992 mtx_lock(&sc->sc_freeqlock); 993 if (SIMPLEQ_EMPTY(&sc->sc_freequeue)) { 994 ubsecstats.hst_queuefull++; 995 sc->sc_needwakeup |= CRYPTO_SYMQ; 996 mtx_unlock(&sc->sc_freeqlock); 997 return (ERESTART); 998 } 999 q = SIMPLEQ_FIRST(&sc->sc_freequeue); 1000 SIMPLEQ_REMOVE_HEAD(&sc->sc_freequeue, q_next); 1001 mtx_unlock(&sc->sc_freeqlock); 1002 1003 dmap = q->q_dma; /* Save dma pointer */ 1004 bzero(q, sizeof(struct ubsec_q)); 1005 bzero(&ctx, sizeof(ctx)); 1006 1007 q->q_dma = dmap; 1008 ses = crypto_get_driver_session(crp->crp_session); 1009 1010 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1011 q->q_src_m = (struct mbuf *)crp->crp_buf; 1012 q->q_dst_m = (struct mbuf *)crp->crp_buf; 1013 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1014 q->q_src_io = (struct uio *)crp->crp_buf; 1015 q->q_dst_io = (struct uio *)crp->crp_buf; 1016 } else { 1017 ubsecstats.hst_badflags++; 1018 err = EINVAL; 1019 goto errout; /* XXX we don't handle contiguous blocks! */ 1020 } 1021 1022 bzero(&dmap->d_dma->d_mcr, sizeof(struct ubsec_mcr)); 1023 1024 dmap->d_dma->d_mcr.mcr_pkts = htole16(1); 1025 dmap->d_dma->d_mcr.mcr_flags = 0; 1026 q->q_crp = crp; 1027 1028 crd1 = crp->crp_desc; 1029 if (crd1 == NULL) { 1030 ubsecstats.hst_nodesc++; 1031 err = EINVAL; 1032 goto errout; 1033 } 1034 crd2 = crd1->crd_next; 1035 1036 if (crd2 == NULL) { 1037 if (crd1->crd_alg == CRYPTO_MD5_HMAC || 1038 crd1->crd_alg == CRYPTO_SHA1_HMAC) { 1039 maccrd = crd1; 1040 enccrd = NULL; 1041 } else if (crd1->crd_alg == CRYPTO_DES_CBC || 1042 crd1->crd_alg == CRYPTO_3DES_CBC) { 1043 maccrd = NULL; 1044 enccrd = crd1; 1045 } else { 1046 ubsecstats.hst_badalg++; 1047 err = EINVAL; 1048 goto errout; 1049 } 1050 } else { 1051 if ((crd1->crd_alg == CRYPTO_MD5_HMAC || 1052 crd1->crd_alg == CRYPTO_SHA1_HMAC) && 1053 (crd2->crd_alg == CRYPTO_DES_CBC || 1054 crd2->crd_alg == CRYPTO_3DES_CBC) && 1055 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) { 1056 maccrd = crd1; 1057 enccrd = crd2; 1058 } else if ((crd1->crd_alg == CRYPTO_DES_CBC || 1059 crd1->crd_alg == CRYPTO_3DES_CBC) && 1060 (crd2->crd_alg == CRYPTO_MD5_HMAC || 1061 crd2->crd_alg == CRYPTO_SHA1_HMAC) && 1062 (crd1->crd_flags & CRD_F_ENCRYPT)) { 1063 enccrd = crd1; 1064 maccrd = crd2; 1065 } else { 1066 /* 1067 * We cannot order the ubsec as requested 1068 */ 1069 ubsecstats.hst_badalg++; 1070 err = EINVAL; 1071 goto errout; 1072 } 1073 } 1074 1075 if (enccrd) { 1076 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1077 ubsec_setup_enckey(ses, enccrd->crd_alg, 1078 enccrd->crd_key); 1079 } 1080 1081 encoffset = enccrd->crd_skip; 1082 ctx.pc_flags |= htole16(UBS_PKTCTX_ENC_3DES); 1083 1084 if (enccrd->crd_flags & CRD_F_ENCRYPT) { 1085 q->q_flags |= UBSEC_QFLAGS_COPYOUTIV; 1086 1087 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1088 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1089 else { 1090 ctx.pc_iv[0] = ses->ses_iv[0]; 1091 ctx.pc_iv[1] = ses->ses_iv[1]; 1092 } 1093 1094 if ((enccrd->crd_flags & CRD_F_IV_PRESENT) == 0) { 1095 crypto_copyback(crp->crp_flags, crp->crp_buf, 1096 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv); 1097 } 1098 } else { 1099 ctx.pc_flags |= htole16(UBS_PKTCTX_INBOUND); 1100 1101 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT) 1102 bcopy(enccrd->crd_iv, ctx.pc_iv, 8); 1103 else { 1104 crypto_copydata(crp->crp_flags, crp->crp_buf, 1105 enccrd->crd_inject, 8, (caddr_t)ctx.pc_iv); 1106 } 1107 } 1108 1109 ctx.pc_deskey[0] = ses->ses_deskey[0]; 1110 ctx.pc_deskey[1] = ses->ses_deskey[1]; 1111 ctx.pc_deskey[2] = ses->ses_deskey[2]; 1112 ctx.pc_deskey[3] = ses->ses_deskey[3]; 1113 ctx.pc_deskey[4] = ses->ses_deskey[4]; 1114 ctx.pc_deskey[5] = ses->ses_deskey[5]; 1115 SWAP32(ctx.pc_iv[0]); 1116 SWAP32(ctx.pc_iv[1]); 1117 } 1118 1119 if (maccrd) { 1120 if (maccrd->crd_flags & CRD_F_KEY_EXPLICIT) { 1121 ubsec_setup_mackey(ses, maccrd->crd_alg, 1122 maccrd->crd_key, maccrd->crd_klen / 8); 1123 } 1124 1125 macoffset = maccrd->crd_skip; 1126 1127 if (maccrd->crd_alg == CRYPTO_MD5_HMAC) 1128 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_MD5); 1129 else 1130 ctx.pc_flags |= htole16(UBS_PKTCTX_AUTH_SHA1); 1131 1132 for (i = 0; i < 5; i++) { 1133 ctx.pc_hminner[i] = ses->ses_hminner[i]; 1134 ctx.pc_hmouter[i] = ses->ses_hmouter[i]; 1135 1136 HTOLE32(ctx.pc_hminner[i]); 1137 HTOLE32(ctx.pc_hmouter[i]); 1138 } 1139 } 1140 1141 if (enccrd && maccrd) { 1142 /* 1143 * ubsec cannot handle packets where the end of encryption 1144 * and authentication are not the same, or where the 1145 * encrypted part begins before the authenticated part. 1146 */ 1147 if ((encoffset + enccrd->crd_len) != 1148 (macoffset + maccrd->crd_len)) { 1149 ubsecstats.hst_lenmismatch++; 1150 err = EINVAL; 1151 goto errout; 1152 } 1153 if (enccrd->crd_skip < maccrd->crd_skip) { 1154 ubsecstats.hst_skipmismatch++; 1155 err = EINVAL; 1156 goto errout; 1157 } 1158 sskip = maccrd->crd_skip; 1159 cpskip = dskip = enccrd->crd_skip; 1160 stheend = maccrd->crd_len; 1161 dtheend = enccrd->crd_len; 1162 coffset = enccrd->crd_skip - maccrd->crd_skip; 1163 cpoffset = cpskip + dtheend; 1164#ifdef UBSEC_DEBUG 1165 if (ubsec_debug) { 1166 printf("mac: skip %d, len %d, inject %d\n", 1167 maccrd->crd_skip, maccrd->crd_len, maccrd->crd_inject); 1168 printf("enc: skip %d, len %d, inject %d\n", 1169 enccrd->crd_skip, enccrd->crd_len, enccrd->crd_inject); 1170 printf("src: skip %d, len %d\n", sskip, stheend); 1171 printf("dst: skip %d, len %d\n", dskip, dtheend); 1172 printf("ubs: coffset %d, pktlen %d, cpskip %d, cpoffset %d\n", 1173 coffset, stheend, cpskip, cpoffset); 1174 } 1175#endif 1176 } else { 1177 cpskip = dskip = sskip = macoffset + encoffset; 1178 dtheend = stheend = (enccrd)?enccrd->crd_len:maccrd->crd_len; 1179 cpoffset = cpskip + dtheend; 1180 coffset = 0; 1181 } 1182 ctx.pc_offset = htole16(coffset >> 2); 1183 1184 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &q->q_src_map)) { 1185 ubsecstats.hst_nomap++; 1186 err = ENOMEM; 1187 goto errout; 1188 } 1189 if (crp->crp_flags & CRYPTO_F_IMBUF) { 1190 if (bus_dmamap_load_mbuf(sc->sc_dmat, q->q_src_map, 1191 q->q_src_m, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1192 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1193 q->q_src_map = NULL; 1194 ubsecstats.hst_noload++; 1195 err = ENOMEM; 1196 goto errout; 1197 } 1198 } else if (crp->crp_flags & CRYPTO_F_IOV) { 1199 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_src_map, 1200 q->q_src_io, ubsec_op_cb, &q->q_src, BUS_DMA_NOWAIT) != 0) { 1201 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1202 q->q_src_map = NULL; 1203 ubsecstats.hst_noload++; 1204 err = ENOMEM; 1205 goto errout; 1206 } 1207 } 1208 nicealign = ubsec_dmamap_aligned(&q->q_src); 1209 1210 dmap->d_dma->d_mcr.mcr_pktlen = htole16(stheend); 1211 1212#ifdef UBSEC_DEBUG 1213 if (ubsec_debug) 1214 printf("src skip: %d nicealign: %u\n", sskip, nicealign); 1215#endif 1216 for (i = j = 0; i < q->q_src_nsegs; i++) { 1217 struct ubsec_pktbuf *pb; 1218 bus_size_t packl = q->q_src_segs[i].ds_len; 1219 bus_addr_t packp = q->q_src_segs[i].ds_addr; 1220 1221 if (sskip >= packl) { 1222 sskip -= packl; 1223 continue; 1224 } 1225 1226 packl -= sskip; 1227 packp += sskip; 1228 sskip = 0; 1229 1230 if (packl > 0xfffc) { 1231 err = EIO; 1232 goto errout; 1233 } 1234 1235 if (j == 0) 1236 pb = &dmap->d_dma->d_mcr.mcr_ipktbuf; 1237 else 1238 pb = &dmap->d_dma->d_sbuf[j - 1]; 1239 1240 pb->pb_addr = htole32(packp); 1241 1242 if (stheend) { 1243 if (packl > stheend) { 1244 pb->pb_len = htole32(stheend); 1245 stheend = 0; 1246 } else { 1247 pb->pb_len = htole32(packl); 1248 stheend -= packl; 1249 } 1250 } else 1251 pb->pb_len = htole32(packl); 1252 1253 if ((i + 1) == q->q_src_nsegs) 1254 pb->pb_next = 0; 1255 else 1256 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1257 offsetof(struct ubsec_dmachunk, d_sbuf[j])); 1258 j++; 1259 } 1260 1261 if (enccrd == NULL && maccrd != NULL) { 1262 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr = 0; 1263 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len = 0; 1264 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next = htole32(dmap->d_alloc.dma_paddr + 1265 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1266#ifdef UBSEC_DEBUG 1267 if (ubsec_debug) 1268 printf("opkt: %x %x %x\n", 1269 dmap->d_dma->d_mcr.mcr_opktbuf.pb_addr, 1270 dmap->d_dma->d_mcr.mcr_opktbuf.pb_len, 1271 dmap->d_dma->d_mcr.mcr_opktbuf.pb_next); 1272#endif 1273 } else { 1274 if (crp->crp_flags & CRYPTO_F_IOV) { 1275 if (!nicealign) { 1276 ubsecstats.hst_iovmisaligned++; 1277 err = EINVAL; 1278 goto errout; 1279 } 1280 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, 1281 &q->q_dst_map)) { 1282 ubsecstats.hst_nomap++; 1283 err = ENOMEM; 1284 goto errout; 1285 } 1286 if (bus_dmamap_load_uio(sc->sc_dmat, q->q_dst_map, 1287 q->q_dst_io, ubsec_op_cb, &q->q_dst, BUS_DMA_NOWAIT) != 0) { 1288 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1289 q->q_dst_map = NULL; 1290 ubsecstats.hst_noload++; 1291 err = ENOMEM; 1292 goto errout; 1293 } 1294 } else if (crp->crp_flags & CRYPTO_F_IMBUF) { 1295 if (nicealign) { 1296 q->q_dst = q->q_src; 1297 } else { 1298 int totlen, len; 1299 struct mbuf *m, *top, **mp; 1300 1301 ubsecstats.hst_unaligned++; 1302 totlen = q->q_src_mapsize; 1303 if (totlen >= MINCLSIZE) { 1304 m = m_getcl(M_NOWAIT, MT_DATA, 1305 q->q_src_m->m_flags & M_PKTHDR); 1306 len = MCLBYTES; 1307 } else if (q->q_src_m->m_flags & M_PKTHDR) { 1308 m = m_gethdr(M_NOWAIT, MT_DATA); 1309 len = MHLEN; 1310 } else { 1311 m = m_get(M_NOWAIT, MT_DATA); 1312 len = MLEN; 1313 } 1314 if (m && q->q_src_m->m_flags & M_PKTHDR && 1315 !m_dup_pkthdr(m, q->q_src_m, M_NOWAIT)) { 1316 m_free(m); 1317 m = NULL; 1318 } 1319 if (m == NULL) { 1320 ubsecstats.hst_nombuf++; 1321 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1322 goto errout; 1323 } 1324 m->m_len = len = min(totlen, len); 1325 totlen -= len; 1326 top = m; 1327 mp = ⊤ 1328 1329 while (totlen > 0) { 1330 if (totlen >= MINCLSIZE) { 1331 m = m_getcl(M_NOWAIT, 1332 MT_DATA, 0); 1333 len = MCLBYTES; 1334 } else { 1335 m = m_get(M_NOWAIT, MT_DATA); 1336 len = MLEN; 1337 } 1338 if (m == NULL) { 1339 m_freem(top); 1340 ubsecstats.hst_nombuf++; 1341 err = sc->sc_nqueue ? ERESTART : ENOMEM; 1342 goto errout; 1343 } 1344 m->m_len = len = min(totlen, len); 1345 totlen -= len; 1346 *mp = m; 1347 mp = &m->m_next; 1348 } 1349 q->q_dst_m = top; 1350 ubsec_mcopy(q->q_src_m, q->q_dst_m, 1351 cpskip, cpoffset); 1352 if (bus_dmamap_create(sc->sc_dmat, 1353 BUS_DMA_NOWAIT, &q->q_dst_map) != 0) { 1354 ubsecstats.hst_nomap++; 1355 err = ENOMEM; 1356 goto errout; 1357 } 1358 if (bus_dmamap_load_mbuf(sc->sc_dmat, 1359 q->q_dst_map, q->q_dst_m, 1360 ubsec_op_cb, &q->q_dst, 1361 BUS_DMA_NOWAIT) != 0) { 1362 bus_dmamap_destroy(sc->sc_dmat, 1363 q->q_dst_map); 1364 q->q_dst_map = NULL; 1365 ubsecstats.hst_noload++; 1366 err = ENOMEM; 1367 goto errout; 1368 } 1369 } 1370 } else { 1371 ubsecstats.hst_badflags++; 1372 err = EINVAL; 1373 goto errout; 1374 } 1375 1376#ifdef UBSEC_DEBUG 1377 if (ubsec_debug) 1378 printf("dst skip: %d\n", dskip); 1379#endif 1380 for (i = j = 0; i < q->q_dst_nsegs; i++) { 1381 struct ubsec_pktbuf *pb; 1382 bus_size_t packl = q->q_dst_segs[i].ds_len; 1383 bus_addr_t packp = q->q_dst_segs[i].ds_addr; 1384 1385 if (dskip >= packl) { 1386 dskip -= packl; 1387 continue; 1388 } 1389 1390 packl -= dskip; 1391 packp += dskip; 1392 dskip = 0; 1393 1394 if (packl > 0xfffc) { 1395 err = EIO; 1396 goto errout; 1397 } 1398 1399 if (j == 0) 1400 pb = &dmap->d_dma->d_mcr.mcr_opktbuf; 1401 else 1402 pb = &dmap->d_dma->d_dbuf[j - 1]; 1403 1404 pb->pb_addr = htole32(packp); 1405 1406 if (dtheend) { 1407 if (packl > dtheend) { 1408 pb->pb_len = htole32(dtheend); 1409 dtheend = 0; 1410 } else { 1411 pb->pb_len = htole32(packl); 1412 dtheend -= packl; 1413 } 1414 } else 1415 pb->pb_len = htole32(packl); 1416 1417 if ((i + 1) == q->q_dst_nsegs) { 1418 if (maccrd) 1419 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1420 offsetof(struct ubsec_dmachunk, d_macbuf[0])); 1421 else 1422 pb->pb_next = 0; 1423 } else 1424 pb->pb_next = htole32(dmap->d_alloc.dma_paddr + 1425 offsetof(struct ubsec_dmachunk, d_dbuf[j])); 1426 j++; 1427 } 1428 } 1429 1430 dmap->d_dma->d_mcr.mcr_cmdctxp = htole32(dmap->d_alloc.dma_paddr + 1431 offsetof(struct ubsec_dmachunk, d_ctx)); 1432 1433 if (sc->sc_flags & UBS_FLAGS_LONGCTX) { 1434 struct ubsec_pktctx_long *ctxl; 1435 1436 ctxl = (struct ubsec_pktctx_long *)(dmap->d_alloc.dma_vaddr + 1437 offsetof(struct ubsec_dmachunk, d_ctx)); 1438 1439 /* transform small context into long context */ 1440 ctxl->pc_len = htole16(sizeof(struct ubsec_pktctx_long)); 1441 ctxl->pc_type = htole16(UBS_PKTCTX_TYPE_IPSEC); 1442 ctxl->pc_flags = ctx.pc_flags; 1443 ctxl->pc_offset = ctx.pc_offset; 1444 for (i = 0; i < 6; i++) 1445 ctxl->pc_deskey[i] = ctx.pc_deskey[i]; 1446 for (i = 0; i < 5; i++) 1447 ctxl->pc_hminner[i] = ctx.pc_hminner[i]; 1448 for (i = 0; i < 5; i++) 1449 ctxl->pc_hmouter[i] = ctx.pc_hmouter[i]; 1450 ctxl->pc_iv[0] = ctx.pc_iv[0]; 1451 ctxl->pc_iv[1] = ctx.pc_iv[1]; 1452 } else 1453 bcopy(&ctx, dmap->d_alloc.dma_vaddr + 1454 offsetof(struct ubsec_dmachunk, d_ctx), 1455 sizeof(struct ubsec_pktctx)); 1456 1457 mtx_lock(&sc->sc_mcr1lock); 1458 SIMPLEQ_INSERT_TAIL(&sc->sc_queue, q, q_next); 1459 sc->sc_nqueue++; 1460 ubsecstats.hst_ipackets++; 1461 ubsecstats.hst_ibytes += dmap->d_alloc.dma_size; 1462 if ((hint & CRYPTO_HINT_MORE) == 0 || sc->sc_nqueue >= UBS_MAX_AGGR) 1463 ubsec_feed(sc); 1464 mtx_unlock(&sc->sc_mcr1lock); 1465 return (0); 1466 1467errout: 1468 if (q != NULL) { 1469 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1470 m_freem(q->q_dst_m); 1471 1472 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1473 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1474 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1475 } 1476 if (q->q_src_map != NULL) { 1477 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1478 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1479 } 1480 } 1481 if (q != NULL || err == ERESTART) { 1482 mtx_lock(&sc->sc_freeqlock); 1483 if (q != NULL) 1484 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1485 if (err == ERESTART) 1486 sc->sc_needwakeup |= CRYPTO_SYMQ; 1487 mtx_unlock(&sc->sc_freeqlock); 1488 } 1489 if (err != ERESTART) { 1490 crp->crp_etype = err; 1491 crypto_done(crp); 1492 } 1493 return (err); 1494} 1495 1496static void 1497ubsec_callback(struct ubsec_softc *sc, struct ubsec_q *q) 1498{ 1499 struct cryptop *crp = (struct cryptop *)q->q_crp; 1500 struct ubsec_session *ses; 1501 struct cryptodesc *crd; 1502 struct ubsec_dma *dmap = q->q_dma; 1503 1504 ses = crypto_get_driver_session(crp->crp_session); 1505 1506 ubsecstats.hst_opackets++; 1507 ubsecstats.hst_obytes += dmap->d_alloc.dma_size; 1508 1509 ubsec_dma_sync(&dmap->d_alloc, 1510 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1511 if (q->q_dst_map != NULL && q->q_dst_map != q->q_src_map) { 1512 bus_dmamap_sync(sc->sc_dmat, q->q_dst_map, 1513 BUS_DMASYNC_POSTREAD); 1514 bus_dmamap_unload(sc->sc_dmat, q->q_dst_map); 1515 bus_dmamap_destroy(sc->sc_dmat, q->q_dst_map); 1516 } 1517 bus_dmamap_sync(sc->sc_dmat, q->q_src_map, BUS_DMASYNC_POSTWRITE); 1518 bus_dmamap_unload(sc->sc_dmat, q->q_src_map); 1519 bus_dmamap_destroy(sc->sc_dmat, q->q_src_map); 1520 1521 if ((crp->crp_flags & CRYPTO_F_IMBUF) && (q->q_src_m != q->q_dst_m)) { 1522 m_freem(q->q_src_m); 1523 crp->crp_buf = (caddr_t)q->q_dst_m; 1524 } 1525 1526 /* copy out IV for future use */ 1527 if (q->q_flags & UBSEC_QFLAGS_COPYOUTIV) { 1528 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1529 if (crd->crd_alg != CRYPTO_DES_CBC && 1530 crd->crd_alg != CRYPTO_3DES_CBC) 1531 continue; 1532 crypto_copydata(crp->crp_flags, crp->crp_buf, 1533 crd->crd_skip + crd->crd_len - 8, 8, 1534 (caddr_t)ses->ses_iv); 1535 break; 1536 } 1537 } 1538 1539 for (crd = crp->crp_desc; crd; crd = crd->crd_next) { 1540 if (crd->crd_alg != CRYPTO_MD5_HMAC && 1541 crd->crd_alg != CRYPTO_SHA1_HMAC) 1542 continue; 1543 crypto_copyback(crp->crp_flags, crp->crp_buf, crd->crd_inject, 1544 ses->ses_mlen, (caddr_t)dmap->d_dma->d_macbuf); 1545 break; 1546 } 1547 mtx_lock(&sc->sc_freeqlock); 1548 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1549 mtx_unlock(&sc->sc_freeqlock); 1550 crypto_done(crp); 1551} 1552 1553static void 1554ubsec_mcopy(struct mbuf *srcm, struct mbuf *dstm, int hoffset, int toffset) 1555{ 1556 int i, j, dlen, slen; 1557 caddr_t dptr, sptr; 1558 1559 j = 0; 1560 sptr = srcm->m_data; 1561 slen = srcm->m_len; 1562 dptr = dstm->m_data; 1563 dlen = dstm->m_len; 1564 1565 while (1) { 1566 for (i = 0; i < min(slen, dlen); i++) { 1567 if (j < hoffset || j >= toffset) 1568 *dptr++ = *sptr++; 1569 slen--; 1570 dlen--; 1571 j++; 1572 } 1573 if (slen == 0) { 1574 srcm = srcm->m_next; 1575 if (srcm == NULL) 1576 return; 1577 sptr = srcm->m_data; 1578 slen = srcm->m_len; 1579 } 1580 if (dlen == 0) { 1581 dstm = dstm->m_next; 1582 if (dstm == NULL) 1583 return; 1584 dptr = dstm->m_data; 1585 dlen = dstm->m_len; 1586 } 1587 } 1588} 1589 1590/* 1591 * feed the key generator, must be called at splimp() or higher. 1592 */ 1593static int 1594ubsec_feed2(struct ubsec_softc *sc) 1595{ 1596 struct ubsec_q2 *q; 1597 1598 while (!SIMPLEQ_EMPTY(&sc->sc_queue2)) { 1599 if (READ_REG(sc, BS_STAT) & BS_STAT_MCR2_FULL) 1600 break; 1601 q = SIMPLEQ_FIRST(&sc->sc_queue2); 1602 1603 ubsec_dma_sync(&q->q_mcr, 1604 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1605 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_PREWRITE); 1606 1607 WRITE_REG(sc, BS_MCR2, q->q_mcr.dma_paddr); 1608 SIMPLEQ_REMOVE_HEAD(&sc->sc_queue2, q_next); 1609 --sc->sc_nqueue2; 1610 SIMPLEQ_INSERT_TAIL(&sc->sc_qchip2, q, q_next); 1611 } 1612 return (0); 1613} 1614 1615/* 1616 * Callback for handling random numbers 1617 */ 1618static void 1619ubsec_callback2(struct ubsec_softc *sc, struct ubsec_q2 *q) 1620{ 1621 struct cryptkop *krp; 1622 struct ubsec_ctx_keyop *ctx; 1623 1624 ctx = (struct ubsec_ctx_keyop *)q->q_ctx.dma_vaddr; 1625 ubsec_dma_sync(&q->q_ctx, BUS_DMASYNC_POSTWRITE); 1626 1627 switch (q->q_type) { 1628#ifndef UBSEC_NO_RNG 1629 case UBS_CTXOP_RNGBYPASS: { 1630 struct ubsec_q2_rng *rng = (struct ubsec_q2_rng *)q; 1631 1632 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_POSTREAD); 1633 (*sc->sc_harvest)(sc->sc_rndtest, 1634 rng->rng_buf.dma_vaddr, 1635 UBSEC_RNG_BUFSIZ*sizeof (u_int32_t)); 1636 rng->rng_used = 0; 1637 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1638 break; 1639 } 1640#endif 1641 case UBS_CTXOP_MODEXP: { 1642 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 1643 u_int rlen, clen; 1644 1645 krp = me->me_krp; 1646 rlen = (me->me_modbits + 7) / 8; 1647 clen = (krp->krp_param[krp->krp_iparams].crp_nbits + 7) / 8; 1648 1649 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_POSTWRITE); 1650 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_POSTWRITE); 1651 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_POSTREAD); 1652 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_POSTWRITE); 1653 1654 if (clen < rlen) 1655 krp->krp_status = E2BIG; 1656 else { 1657 if (sc->sc_flags & UBS_FLAGS_HWNORM) { 1658 bzero(krp->krp_param[krp->krp_iparams].crp_p, 1659 (krp->krp_param[krp->krp_iparams].crp_nbits 1660 + 7) / 8); 1661 bcopy(me->me_C.dma_vaddr, 1662 krp->krp_param[krp->krp_iparams].crp_p, 1663 (me->me_modbits + 7) / 8); 1664 } else 1665 ubsec_kshift_l(me->me_shiftbits, 1666 me->me_C.dma_vaddr, me->me_normbits, 1667 krp->krp_param[krp->krp_iparams].crp_p, 1668 krp->krp_param[krp->krp_iparams].crp_nbits); 1669 } 1670 1671 crypto_kdone(krp); 1672 1673 /* bzero all potentially sensitive data */ 1674 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 1675 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 1676 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 1677 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 1678 1679 /* Can't free here, so put us on the free list. */ 1680 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &me->me_q, q_next); 1681 break; 1682 } 1683 case UBS_CTXOP_RSAPRIV: { 1684 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 1685 u_int len; 1686 1687 krp = rp->rpr_krp; 1688 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_POSTWRITE); 1689 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_POSTREAD); 1690 1691 len = (krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_nbits + 7) / 8; 1692 bcopy(rp->rpr_msgout.dma_vaddr, 1693 krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT].crp_p, len); 1694 1695 crypto_kdone(krp); 1696 1697 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 1698 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 1699 bzero(rp->rpr_q.q_ctx.dma_vaddr, rp->rpr_q.q_ctx.dma_size); 1700 1701 /* Can't free here, so put us on the free list. */ 1702 SIMPLEQ_INSERT_TAIL(&sc->sc_q2free, &rp->rpr_q, q_next); 1703 break; 1704 } 1705 default: 1706 device_printf(sc->sc_dev, "unknown ctx op: %x\n", 1707 letoh16(ctx->ctx_op)); 1708 break; 1709 } 1710} 1711 1712#ifndef UBSEC_NO_RNG 1713static void 1714ubsec_rng(void *vsc) 1715{ 1716 struct ubsec_softc *sc = vsc; 1717 struct ubsec_q2_rng *rng = &sc->sc_rng; 1718 struct ubsec_mcr *mcr; 1719 struct ubsec_ctx_rngbypass *ctx; 1720 1721 mtx_lock(&sc->sc_mcr2lock); 1722 if (rng->rng_used) { 1723 mtx_unlock(&sc->sc_mcr2lock); 1724 return; 1725 } 1726 sc->sc_nqueue2++; 1727 if (sc->sc_nqueue2 >= UBS_MAX_NQUEUE) 1728 goto out; 1729 1730 mcr = (struct ubsec_mcr *)rng->rng_q.q_mcr.dma_vaddr; 1731 ctx = (struct ubsec_ctx_rngbypass *)rng->rng_q.q_ctx.dma_vaddr; 1732 1733 mcr->mcr_pkts = htole16(1); 1734 mcr->mcr_flags = 0; 1735 mcr->mcr_cmdctxp = htole32(rng->rng_q.q_ctx.dma_paddr); 1736 mcr->mcr_ipktbuf.pb_addr = mcr->mcr_ipktbuf.pb_next = 0; 1737 mcr->mcr_ipktbuf.pb_len = 0; 1738 mcr->mcr_reserved = mcr->mcr_pktlen = 0; 1739 mcr->mcr_opktbuf.pb_addr = htole32(rng->rng_buf.dma_paddr); 1740 mcr->mcr_opktbuf.pb_len = htole32(((sizeof(u_int32_t) * UBSEC_RNG_BUFSIZ)) & 1741 UBS_PKTBUF_LEN); 1742 mcr->mcr_opktbuf.pb_next = 0; 1743 1744 ctx->rbp_len = htole16(sizeof(struct ubsec_ctx_rngbypass)); 1745 ctx->rbp_op = htole16(UBS_CTXOP_RNGBYPASS); 1746 rng->rng_q.q_type = UBS_CTXOP_RNGBYPASS; 1747 1748 ubsec_dma_sync(&rng->rng_buf, BUS_DMASYNC_PREREAD); 1749 1750 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rng->rng_q, q_next); 1751 rng->rng_used = 1; 1752 ubsec_feed2(sc); 1753 ubsecstats.hst_rng++; 1754 mtx_unlock(&sc->sc_mcr2lock); 1755 1756 return; 1757 1758out: 1759 /* 1760 * Something weird happened, generate our own call back. 1761 */ 1762 sc->sc_nqueue2--; 1763 mtx_unlock(&sc->sc_mcr2lock); 1764 callout_reset(&sc->sc_rngto, sc->sc_rnghz, ubsec_rng, sc); 1765} 1766#endif /* UBSEC_NO_RNG */ 1767 1768static void 1769ubsec_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1770{ 1771 bus_addr_t *paddr = (bus_addr_t*) arg; 1772 *paddr = segs->ds_addr; 1773} 1774 1775static int 1776ubsec_dma_malloc( 1777 struct ubsec_softc *sc, 1778 bus_size_t size, 1779 struct ubsec_dma_alloc *dma, 1780 int mapflags 1781) 1782{ 1783 int r; 1784 1785 /* XXX could specify sc_dmat as parent but that just adds overhead */ 1786 r = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1787 1, 0, /* alignment, bounds */ 1788 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1789 BUS_SPACE_MAXADDR, /* highaddr */ 1790 NULL, NULL, /* filter, filterarg */ 1791 size, /* maxsize */ 1792 1, /* nsegments */ 1793 size, /* maxsegsize */ 1794 BUS_DMA_ALLOCNOW, /* flags */ 1795 NULL, NULL, /* lockfunc, lockarg */ 1796 &dma->dma_tag); 1797 if (r != 0) { 1798 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1799 "bus_dma_tag_create failed; error %u\n", r); 1800 goto fail_1; 1801 } 1802 1803 r = bus_dmamem_alloc(dma->dma_tag, (void**) &dma->dma_vaddr, 1804 BUS_DMA_NOWAIT, &dma->dma_map); 1805 if (r != 0) { 1806 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1807 "bus_dmammem_alloc failed; size %ju, error %u\n", 1808 (intmax_t)size, r); 1809 goto fail_2; 1810 } 1811 1812 r = bus_dmamap_load(dma->dma_tag, dma->dma_map, dma->dma_vaddr, 1813 size, 1814 ubsec_dmamap_cb, 1815 &dma->dma_paddr, 1816 mapflags | BUS_DMA_NOWAIT); 1817 if (r != 0) { 1818 device_printf(sc->sc_dev, "ubsec_dma_malloc: " 1819 "bus_dmamap_load failed; error %u\n", r); 1820 goto fail_3; 1821 } 1822 1823 dma->dma_size = size; 1824 return (0); 1825 1826fail_3: 1827 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1828fail_2: 1829 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1830fail_1: 1831 bus_dma_tag_destroy(dma->dma_tag); 1832 dma->dma_tag = NULL; 1833 return (r); 1834} 1835 1836static void 1837ubsec_dma_free(struct ubsec_softc *sc, struct ubsec_dma_alloc *dma) 1838{ 1839 bus_dmamap_unload(dma->dma_tag, dma->dma_map); 1840 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map); 1841 bus_dma_tag_destroy(dma->dma_tag); 1842} 1843 1844/* 1845 * Resets the board. Values in the regesters are left as is 1846 * from the reset (i.e. initial values are assigned elsewhere). 1847 */ 1848static void 1849ubsec_reset_board(struct ubsec_softc *sc) 1850{ 1851 volatile u_int32_t ctrl; 1852 1853 ctrl = READ_REG(sc, BS_CTRL); 1854 ctrl |= BS_CTRL_RESET; 1855 WRITE_REG(sc, BS_CTRL, ctrl); 1856 1857 /* 1858 * Wait aprox. 30 PCI clocks = 900 ns = 0.9 us 1859 */ 1860 DELAY(10); 1861} 1862 1863/* 1864 * Init Broadcom registers 1865 */ 1866static void 1867ubsec_init_board(struct ubsec_softc *sc) 1868{ 1869 u_int32_t ctrl; 1870 1871 ctrl = READ_REG(sc, BS_CTRL); 1872 ctrl &= ~(BS_CTRL_BE32 | BS_CTRL_BE64); 1873 ctrl |= BS_CTRL_LITTLE_ENDIAN | BS_CTRL_MCR1INT; 1874 1875 if (sc->sc_flags & (UBS_FLAGS_KEY|UBS_FLAGS_RNG)) 1876 ctrl |= BS_CTRL_MCR2INT; 1877 else 1878 ctrl &= ~BS_CTRL_MCR2INT; 1879 1880 if (sc->sc_flags & UBS_FLAGS_HWNORM) 1881 ctrl &= ~BS_CTRL_SWNORM; 1882 1883 WRITE_REG(sc, BS_CTRL, ctrl); 1884} 1885 1886/* 1887 * Init Broadcom PCI registers 1888 */ 1889static void 1890ubsec_init_pciregs(device_t dev) 1891{ 1892#if 0 1893 u_int32_t misc; 1894 1895 misc = pci_conf_read(pc, pa->pa_tag, BS_RTY_TOUT); 1896 misc = (misc & ~(UBS_PCI_RTY_MASK << UBS_PCI_RTY_SHIFT)) 1897 | ((UBS_DEF_RTY & 0xff) << UBS_PCI_RTY_SHIFT); 1898 misc = (misc & ~(UBS_PCI_TOUT_MASK << UBS_PCI_TOUT_SHIFT)) 1899 | ((UBS_DEF_TOUT & 0xff) << UBS_PCI_TOUT_SHIFT); 1900 pci_conf_write(pc, pa->pa_tag, BS_RTY_TOUT, misc); 1901#endif 1902 1903 /* 1904 * This will set the cache line size to 1, this will 1905 * force the BCM58xx chip just to do burst read/writes. 1906 * Cache line read/writes are to slow 1907 */ 1908 pci_write_config(dev, PCIR_CACHELNSZ, UBS_DEF_CACHELINE, 1); 1909} 1910 1911/* 1912 * Clean up after a chip crash. 1913 * It is assumed that the caller in splimp() 1914 */ 1915static void 1916ubsec_cleanchip(struct ubsec_softc *sc) 1917{ 1918 struct ubsec_q *q; 1919 1920 while (!SIMPLEQ_EMPTY(&sc->sc_qchip)) { 1921 q = SIMPLEQ_FIRST(&sc->sc_qchip); 1922 SIMPLEQ_REMOVE_HEAD(&sc->sc_qchip, q_next); 1923 ubsec_free_q(sc, q); 1924 } 1925 sc->sc_nqchip = 0; 1926} 1927 1928/* 1929 * free a ubsec_q 1930 * It is assumed that the caller is within splimp(). 1931 */ 1932static int 1933ubsec_free_q(struct ubsec_softc *sc, struct ubsec_q *q) 1934{ 1935 struct ubsec_q *q2; 1936 struct cryptop *crp; 1937 int npkts; 1938 int i; 1939 1940 npkts = q->q_nstacked_mcrs; 1941 1942 for (i = 0; i < npkts; i++) { 1943 if(q->q_stacked_mcr[i]) { 1944 q2 = q->q_stacked_mcr[i]; 1945 1946 if ((q2->q_dst_m != NULL) && (q2->q_src_m != q2->q_dst_m)) 1947 m_freem(q2->q_dst_m); 1948 1949 crp = (struct cryptop *)q2->q_crp; 1950 1951 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q2, q_next); 1952 1953 crp->crp_etype = EFAULT; 1954 crypto_done(crp); 1955 } else { 1956 break; 1957 } 1958 } 1959 1960 /* 1961 * Free header MCR 1962 */ 1963 if ((q->q_dst_m != NULL) && (q->q_src_m != q->q_dst_m)) 1964 m_freem(q->q_dst_m); 1965 1966 crp = (struct cryptop *)q->q_crp; 1967 1968 SIMPLEQ_INSERT_TAIL(&sc->sc_freequeue, q, q_next); 1969 1970 crp->crp_etype = EFAULT; 1971 crypto_done(crp); 1972 return(0); 1973} 1974 1975/* 1976 * Routine to reset the chip and clean up. 1977 * It is assumed that the caller is in splimp() 1978 */ 1979static void 1980ubsec_totalreset(struct ubsec_softc *sc) 1981{ 1982 ubsec_reset_board(sc); 1983 ubsec_init_board(sc); 1984 ubsec_cleanchip(sc); 1985} 1986 1987static int 1988ubsec_dmamap_aligned(struct ubsec_operand *op) 1989{ 1990 int i; 1991 1992 for (i = 0; i < op->nsegs; i++) { 1993 if (op->segs[i].ds_addr & 3) 1994 return (0); 1995 if ((i != (op->nsegs - 1)) && 1996 (op->segs[i].ds_len & 3)) 1997 return (0); 1998 } 1999 return (1); 2000} 2001 2002static void 2003ubsec_kfree(struct ubsec_softc *sc, struct ubsec_q2 *q) 2004{ 2005 switch (q->q_type) { 2006 case UBS_CTXOP_MODEXP: { 2007 struct ubsec_q2_modexp *me = (struct ubsec_q2_modexp *)q; 2008 2009 ubsec_dma_free(sc, &me->me_q.q_mcr); 2010 ubsec_dma_free(sc, &me->me_q.q_ctx); 2011 ubsec_dma_free(sc, &me->me_M); 2012 ubsec_dma_free(sc, &me->me_E); 2013 ubsec_dma_free(sc, &me->me_C); 2014 ubsec_dma_free(sc, &me->me_epb); 2015 free(me, M_DEVBUF); 2016 break; 2017 } 2018 case UBS_CTXOP_RSAPRIV: { 2019 struct ubsec_q2_rsapriv *rp = (struct ubsec_q2_rsapriv *)q; 2020 2021 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2022 ubsec_dma_free(sc, &rp->rpr_q.q_ctx); 2023 ubsec_dma_free(sc, &rp->rpr_msgin); 2024 ubsec_dma_free(sc, &rp->rpr_msgout); 2025 free(rp, M_DEVBUF); 2026 break; 2027 } 2028 default: 2029 device_printf(sc->sc_dev, "invalid kfree 0x%x\n", q->q_type); 2030 break; 2031 } 2032} 2033 2034static int 2035ubsec_kprocess(device_t dev, struct cryptkop *krp, int hint) 2036{ 2037 struct ubsec_softc *sc = device_get_softc(dev); 2038 int r; 2039 2040 if (krp == NULL || krp->krp_callback == NULL) 2041 return (EINVAL); 2042 2043 while (!SIMPLEQ_EMPTY(&sc->sc_q2free)) { 2044 struct ubsec_q2 *q; 2045 2046 q = SIMPLEQ_FIRST(&sc->sc_q2free); 2047 SIMPLEQ_REMOVE_HEAD(&sc->sc_q2free, q_next); 2048 ubsec_kfree(sc, q); 2049 } 2050 2051 switch (krp->krp_op) { 2052 case CRK_MOD_EXP: 2053 if (sc->sc_flags & UBS_FLAGS_HWNORM) 2054 r = ubsec_kprocess_modexp_hw(sc, krp, hint); 2055 else 2056 r = ubsec_kprocess_modexp_sw(sc, krp, hint); 2057 break; 2058 case CRK_MOD_EXP_CRT: 2059 return (ubsec_kprocess_rsapriv(sc, krp, hint)); 2060 default: 2061 device_printf(sc->sc_dev, "kprocess: invalid op 0x%x\n", 2062 krp->krp_op); 2063 krp->krp_status = EOPNOTSUPP; 2064 crypto_kdone(krp); 2065 return (0); 2066 } 2067 return (0); /* silence compiler */ 2068} 2069 2070/* 2071 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (sw normalization) 2072 */ 2073static int 2074ubsec_kprocess_modexp_sw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2075{ 2076 struct ubsec_q2_modexp *me; 2077 struct ubsec_mcr *mcr; 2078 struct ubsec_ctx_modexp *ctx; 2079 struct ubsec_pktbuf *epb; 2080 int err = 0; 2081 u_int nbits, normbits, mbits, shiftbits, ebits; 2082 2083 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2084 if (me == NULL) { 2085 err = ENOMEM; 2086 goto errout; 2087 } 2088 bzero(me, sizeof *me); 2089 me->me_krp = krp; 2090 me->me_q.q_type = UBS_CTXOP_MODEXP; 2091 2092 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2093 if (nbits <= 512) 2094 normbits = 512; 2095 else if (nbits <= 768) 2096 normbits = 768; 2097 else if (nbits <= 1024) 2098 normbits = 1024; 2099 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2100 normbits = 1536; 2101 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2102 normbits = 2048; 2103 else { 2104 err = E2BIG; 2105 goto errout; 2106 } 2107 2108 shiftbits = normbits - nbits; 2109 2110 me->me_modbits = nbits; 2111 me->me_shiftbits = shiftbits; 2112 me->me_normbits = normbits; 2113 2114 /* Sanity check: result bits must be >= true modulus bits. */ 2115 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2116 err = ERANGE; 2117 goto errout; 2118 } 2119 2120 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2121 &me->me_q.q_mcr, 0)) { 2122 err = ENOMEM; 2123 goto errout; 2124 } 2125 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2126 2127 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2128 &me->me_q.q_ctx, 0)) { 2129 err = ENOMEM; 2130 goto errout; 2131 } 2132 2133 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2134 if (mbits > nbits) { 2135 err = E2BIG; 2136 goto errout; 2137 } 2138 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2139 err = ENOMEM; 2140 goto errout; 2141 } 2142 ubsec_kshift_r(shiftbits, 2143 krp->krp_param[UBS_MODEXP_PAR_M].crp_p, mbits, 2144 me->me_M.dma_vaddr, normbits); 2145 2146 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2147 err = ENOMEM; 2148 goto errout; 2149 } 2150 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2151 2152 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2153 if (ebits > nbits) { 2154 err = E2BIG; 2155 goto errout; 2156 } 2157 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2158 err = ENOMEM; 2159 goto errout; 2160 } 2161 ubsec_kshift_r(shiftbits, 2162 krp->krp_param[UBS_MODEXP_PAR_E].crp_p, ebits, 2163 me->me_E.dma_vaddr, normbits); 2164 2165 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2166 &me->me_epb, 0)) { 2167 err = ENOMEM; 2168 goto errout; 2169 } 2170 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2171 epb->pb_addr = htole32(me->me_E.dma_paddr); 2172 epb->pb_next = 0; 2173 epb->pb_len = htole32(normbits / 8); 2174 2175#ifdef UBSEC_DEBUG 2176 if (ubsec_debug) { 2177 printf("Epb "); 2178 ubsec_dump_pb(epb); 2179 } 2180#endif 2181 2182 mcr->mcr_pkts = htole16(1); 2183 mcr->mcr_flags = 0; 2184 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2185 mcr->mcr_reserved = 0; 2186 mcr->mcr_pktlen = 0; 2187 2188 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2189 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2190 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2191 2192 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2193 mcr->mcr_opktbuf.pb_next = 0; 2194 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2195 2196#ifdef DIAGNOSTIC 2197 /* Misaligned output buffer will hang the chip. */ 2198 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2199 panic("%s: modexp invalid addr 0x%x\n", 2200 device_get_nameunit(sc->sc_dev), 2201 letoh32(mcr->mcr_opktbuf.pb_addr)); 2202 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2203 panic("%s: modexp invalid len 0x%x\n", 2204 device_get_nameunit(sc->sc_dev), 2205 letoh32(mcr->mcr_opktbuf.pb_len)); 2206#endif 2207 2208 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2209 bzero(ctx, sizeof(*ctx)); 2210 ubsec_kshift_r(shiftbits, 2211 krp->krp_param[UBS_MODEXP_PAR_N].crp_p, nbits, 2212 ctx->me_N, normbits); 2213 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2214 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2215 ctx->me_E_len = htole16(nbits); 2216 ctx->me_N_len = htole16(nbits); 2217 2218#ifdef UBSEC_DEBUG 2219 if (ubsec_debug) { 2220 ubsec_dump_mcr(mcr); 2221 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2222 } 2223#endif 2224 2225 /* 2226 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2227 * everything else. 2228 */ 2229 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2230 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2231 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2232 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2233 2234 /* Enqueue and we're done... */ 2235 mtx_lock(&sc->sc_mcr2lock); 2236 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2237 ubsec_feed2(sc); 2238 ubsecstats.hst_modexp++; 2239 mtx_unlock(&sc->sc_mcr2lock); 2240 2241 return (0); 2242 2243errout: 2244 if (me != NULL) { 2245 if (me->me_q.q_mcr.dma_tag != NULL) 2246 ubsec_dma_free(sc, &me->me_q.q_mcr); 2247 if (me->me_q.q_ctx.dma_tag != NULL) { 2248 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2249 ubsec_dma_free(sc, &me->me_q.q_ctx); 2250 } 2251 if (me->me_M.dma_tag != NULL) { 2252 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2253 ubsec_dma_free(sc, &me->me_M); 2254 } 2255 if (me->me_E.dma_tag != NULL) { 2256 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2257 ubsec_dma_free(sc, &me->me_E); 2258 } 2259 if (me->me_C.dma_tag != NULL) { 2260 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2261 ubsec_dma_free(sc, &me->me_C); 2262 } 2263 if (me->me_epb.dma_tag != NULL) 2264 ubsec_dma_free(sc, &me->me_epb); 2265 free(me, M_DEVBUF); 2266 } 2267 krp->krp_status = err; 2268 crypto_kdone(krp); 2269 return (0); 2270} 2271 2272/* 2273 * Start computation of cr[C] = (cr[M] ^ cr[E]) mod cr[N] (hw normalization) 2274 */ 2275static int 2276ubsec_kprocess_modexp_hw(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2277{ 2278 struct ubsec_q2_modexp *me; 2279 struct ubsec_mcr *mcr; 2280 struct ubsec_ctx_modexp *ctx; 2281 struct ubsec_pktbuf *epb; 2282 int err = 0; 2283 u_int nbits, normbits, mbits, shiftbits, ebits; 2284 2285 me = (struct ubsec_q2_modexp *)malloc(sizeof *me, M_DEVBUF, M_NOWAIT); 2286 if (me == NULL) { 2287 err = ENOMEM; 2288 goto errout; 2289 } 2290 bzero(me, sizeof *me); 2291 me->me_krp = krp; 2292 me->me_q.q_type = UBS_CTXOP_MODEXP; 2293 2294 nbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_N]); 2295 if (nbits <= 512) 2296 normbits = 512; 2297 else if (nbits <= 768) 2298 normbits = 768; 2299 else if (nbits <= 1024) 2300 normbits = 1024; 2301 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 1536) 2302 normbits = 1536; 2303 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && nbits <= 2048) 2304 normbits = 2048; 2305 else { 2306 err = E2BIG; 2307 goto errout; 2308 } 2309 2310 shiftbits = normbits - nbits; 2311 2312 /* XXX ??? */ 2313 me->me_modbits = nbits; 2314 me->me_shiftbits = shiftbits; 2315 me->me_normbits = normbits; 2316 2317 /* Sanity check: result bits must be >= true modulus bits. */ 2318 if (krp->krp_param[krp->krp_iparams].crp_nbits < nbits) { 2319 err = ERANGE; 2320 goto errout; 2321 } 2322 2323 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2324 &me->me_q.q_mcr, 0)) { 2325 err = ENOMEM; 2326 goto errout; 2327 } 2328 mcr = (struct ubsec_mcr *)me->me_q.q_mcr.dma_vaddr; 2329 2330 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_modexp), 2331 &me->me_q.q_ctx, 0)) { 2332 err = ENOMEM; 2333 goto errout; 2334 } 2335 2336 mbits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_M]); 2337 if (mbits > nbits) { 2338 err = E2BIG; 2339 goto errout; 2340 } 2341 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_M, 0)) { 2342 err = ENOMEM; 2343 goto errout; 2344 } 2345 bzero(me->me_M.dma_vaddr, normbits / 8); 2346 bcopy(krp->krp_param[UBS_MODEXP_PAR_M].crp_p, 2347 me->me_M.dma_vaddr, (mbits + 7) / 8); 2348 2349 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_C, 0)) { 2350 err = ENOMEM; 2351 goto errout; 2352 } 2353 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2354 2355 ebits = ubsec_ksigbits(&krp->krp_param[UBS_MODEXP_PAR_E]); 2356 if (ebits > nbits) { 2357 err = E2BIG; 2358 goto errout; 2359 } 2360 if (ubsec_dma_malloc(sc, normbits / 8, &me->me_E, 0)) { 2361 err = ENOMEM; 2362 goto errout; 2363 } 2364 bzero(me->me_E.dma_vaddr, normbits / 8); 2365 bcopy(krp->krp_param[UBS_MODEXP_PAR_E].crp_p, 2366 me->me_E.dma_vaddr, (ebits + 7) / 8); 2367 2368 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_pktbuf), 2369 &me->me_epb, 0)) { 2370 err = ENOMEM; 2371 goto errout; 2372 } 2373 epb = (struct ubsec_pktbuf *)me->me_epb.dma_vaddr; 2374 epb->pb_addr = htole32(me->me_E.dma_paddr); 2375 epb->pb_next = 0; 2376 epb->pb_len = htole32((ebits + 7) / 8); 2377 2378#ifdef UBSEC_DEBUG 2379 if (ubsec_debug) { 2380 printf("Epb "); 2381 ubsec_dump_pb(epb); 2382 } 2383#endif 2384 2385 mcr->mcr_pkts = htole16(1); 2386 mcr->mcr_flags = 0; 2387 mcr->mcr_cmdctxp = htole32(me->me_q.q_ctx.dma_paddr); 2388 mcr->mcr_reserved = 0; 2389 mcr->mcr_pktlen = 0; 2390 2391 mcr->mcr_ipktbuf.pb_addr = htole32(me->me_M.dma_paddr); 2392 mcr->mcr_ipktbuf.pb_len = htole32(normbits / 8); 2393 mcr->mcr_ipktbuf.pb_next = htole32(me->me_epb.dma_paddr); 2394 2395 mcr->mcr_opktbuf.pb_addr = htole32(me->me_C.dma_paddr); 2396 mcr->mcr_opktbuf.pb_next = 0; 2397 mcr->mcr_opktbuf.pb_len = htole32(normbits / 8); 2398 2399#ifdef DIAGNOSTIC 2400 /* Misaligned output buffer will hang the chip. */ 2401 if ((letoh32(mcr->mcr_opktbuf.pb_addr) & 3) != 0) 2402 panic("%s: modexp invalid addr 0x%x\n", 2403 device_get_nameunit(sc->sc_dev), 2404 letoh32(mcr->mcr_opktbuf.pb_addr)); 2405 if ((letoh32(mcr->mcr_opktbuf.pb_len) & 3) != 0) 2406 panic("%s: modexp invalid len 0x%x\n", 2407 device_get_nameunit(sc->sc_dev), 2408 letoh32(mcr->mcr_opktbuf.pb_len)); 2409#endif 2410 2411 ctx = (struct ubsec_ctx_modexp *)me->me_q.q_ctx.dma_vaddr; 2412 bzero(ctx, sizeof(*ctx)); 2413 bcopy(krp->krp_param[UBS_MODEXP_PAR_N].crp_p, ctx->me_N, 2414 (nbits + 7) / 8); 2415 ctx->me_len = htole16((normbits / 8) + (4 * sizeof(u_int16_t))); 2416 ctx->me_op = htole16(UBS_CTXOP_MODEXP); 2417 ctx->me_E_len = htole16(ebits); 2418 ctx->me_N_len = htole16(nbits); 2419 2420#ifdef UBSEC_DEBUG 2421 if (ubsec_debug) { 2422 ubsec_dump_mcr(mcr); 2423 ubsec_dump_ctx2((struct ubsec_ctx_keyop *)ctx); 2424 } 2425#endif 2426 2427 /* 2428 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2429 * everything else. 2430 */ 2431 ubsec_dma_sync(&me->me_M, BUS_DMASYNC_PREWRITE); 2432 ubsec_dma_sync(&me->me_E, BUS_DMASYNC_PREWRITE); 2433 ubsec_dma_sync(&me->me_C, BUS_DMASYNC_PREREAD); 2434 ubsec_dma_sync(&me->me_epb, BUS_DMASYNC_PREWRITE); 2435 2436 /* Enqueue and we're done... */ 2437 mtx_lock(&sc->sc_mcr2lock); 2438 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &me->me_q, q_next); 2439 ubsec_feed2(sc); 2440 mtx_unlock(&sc->sc_mcr2lock); 2441 2442 return (0); 2443 2444errout: 2445 if (me != NULL) { 2446 if (me->me_q.q_mcr.dma_tag != NULL) 2447 ubsec_dma_free(sc, &me->me_q.q_mcr); 2448 if (me->me_q.q_ctx.dma_tag != NULL) { 2449 bzero(me->me_q.q_ctx.dma_vaddr, me->me_q.q_ctx.dma_size); 2450 ubsec_dma_free(sc, &me->me_q.q_ctx); 2451 } 2452 if (me->me_M.dma_tag != NULL) { 2453 bzero(me->me_M.dma_vaddr, me->me_M.dma_size); 2454 ubsec_dma_free(sc, &me->me_M); 2455 } 2456 if (me->me_E.dma_tag != NULL) { 2457 bzero(me->me_E.dma_vaddr, me->me_E.dma_size); 2458 ubsec_dma_free(sc, &me->me_E); 2459 } 2460 if (me->me_C.dma_tag != NULL) { 2461 bzero(me->me_C.dma_vaddr, me->me_C.dma_size); 2462 ubsec_dma_free(sc, &me->me_C); 2463 } 2464 if (me->me_epb.dma_tag != NULL) 2465 ubsec_dma_free(sc, &me->me_epb); 2466 free(me, M_DEVBUF); 2467 } 2468 krp->krp_status = err; 2469 crypto_kdone(krp); 2470 return (0); 2471} 2472 2473static int 2474ubsec_kprocess_rsapriv(struct ubsec_softc *sc, struct cryptkop *krp, int hint) 2475{ 2476 struct ubsec_q2_rsapriv *rp = NULL; 2477 struct ubsec_mcr *mcr; 2478 struct ubsec_ctx_rsapriv *ctx; 2479 int err = 0; 2480 u_int padlen, msglen; 2481 2482 msglen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_P]); 2483 padlen = ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_Q]); 2484 if (msglen > padlen) 2485 padlen = msglen; 2486 2487 if (padlen <= 256) 2488 padlen = 256; 2489 else if (padlen <= 384) 2490 padlen = 384; 2491 else if (padlen <= 512) 2492 padlen = 512; 2493 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 768) 2494 padlen = 768; 2495 else if (sc->sc_flags & UBS_FLAGS_BIGKEY && padlen <= 1024) 2496 padlen = 1024; 2497 else { 2498 err = E2BIG; 2499 goto errout; 2500 } 2501 2502 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DP]) > padlen) { 2503 err = E2BIG; 2504 goto errout; 2505 } 2506 2507 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_DQ]) > padlen) { 2508 err = E2BIG; 2509 goto errout; 2510 } 2511 2512 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_PINV]) > padlen) { 2513 err = E2BIG; 2514 goto errout; 2515 } 2516 2517 rp = (struct ubsec_q2_rsapriv *)malloc(sizeof *rp, M_DEVBUF, M_NOWAIT); 2518 if (rp == NULL) 2519 return (ENOMEM); 2520 bzero(rp, sizeof *rp); 2521 rp->rpr_krp = krp; 2522 rp->rpr_q.q_type = UBS_CTXOP_RSAPRIV; 2523 2524 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_mcr), 2525 &rp->rpr_q.q_mcr, 0)) { 2526 err = ENOMEM; 2527 goto errout; 2528 } 2529 mcr = (struct ubsec_mcr *)rp->rpr_q.q_mcr.dma_vaddr; 2530 2531 if (ubsec_dma_malloc(sc, sizeof(struct ubsec_ctx_rsapriv), 2532 &rp->rpr_q.q_ctx, 0)) { 2533 err = ENOMEM; 2534 goto errout; 2535 } 2536 ctx = (struct ubsec_ctx_rsapriv *)rp->rpr_q.q_ctx.dma_vaddr; 2537 bzero(ctx, sizeof *ctx); 2538 2539 /* Copy in p */ 2540 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_P].crp_p, 2541 &ctx->rpr_buf[0 * (padlen / 8)], 2542 (krp->krp_param[UBS_RSAPRIV_PAR_P].crp_nbits + 7) / 8); 2543 2544 /* Copy in q */ 2545 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_p, 2546 &ctx->rpr_buf[1 * (padlen / 8)], 2547 (krp->krp_param[UBS_RSAPRIV_PAR_Q].crp_nbits + 7) / 8); 2548 2549 /* Copy in dp */ 2550 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_p, 2551 &ctx->rpr_buf[2 * (padlen / 8)], 2552 (krp->krp_param[UBS_RSAPRIV_PAR_DP].crp_nbits + 7) / 8); 2553 2554 /* Copy in dq */ 2555 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_p, 2556 &ctx->rpr_buf[3 * (padlen / 8)], 2557 (krp->krp_param[UBS_RSAPRIV_PAR_DQ].crp_nbits + 7) / 8); 2558 2559 /* Copy in pinv */ 2560 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_p, 2561 &ctx->rpr_buf[4 * (padlen / 8)], 2562 (krp->krp_param[UBS_RSAPRIV_PAR_PINV].crp_nbits + 7) / 8); 2563 2564 msglen = padlen * 2; 2565 2566 /* Copy in input message (aligned buffer/length). */ 2567 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGIN]) > msglen) { 2568 /* Is this likely? */ 2569 err = E2BIG; 2570 goto errout; 2571 } 2572 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgin, 0)) { 2573 err = ENOMEM; 2574 goto errout; 2575 } 2576 bzero(rp->rpr_msgin.dma_vaddr, (msglen + 7) / 8); 2577 bcopy(krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_p, 2578 rp->rpr_msgin.dma_vaddr, 2579 (krp->krp_param[UBS_RSAPRIV_PAR_MSGIN].crp_nbits + 7) / 8); 2580 2581 /* Prepare space for output message (aligned buffer/length). */ 2582 if (ubsec_ksigbits(&krp->krp_param[UBS_RSAPRIV_PAR_MSGOUT]) < msglen) { 2583 /* Is this likely? */ 2584 err = E2BIG; 2585 goto errout; 2586 } 2587 if (ubsec_dma_malloc(sc, (msglen + 7) / 8, &rp->rpr_msgout, 0)) { 2588 err = ENOMEM; 2589 goto errout; 2590 } 2591 bzero(rp->rpr_msgout.dma_vaddr, (msglen + 7) / 8); 2592 2593 mcr->mcr_pkts = htole16(1); 2594 mcr->mcr_flags = 0; 2595 mcr->mcr_cmdctxp = htole32(rp->rpr_q.q_ctx.dma_paddr); 2596 mcr->mcr_ipktbuf.pb_addr = htole32(rp->rpr_msgin.dma_paddr); 2597 mcr->mcr_ipktbuf.pb_next = 0; 2598 mcr->mcr_ipktbuf.pb_len = htole32(rp->rpr_msgin.dma_size); 2599 mcr->mcr_reserved = 0; 2600 mcr->mcr_pktlen = htole16(msglen); 2601 mcr->mcr_opktbuf.pb_addr = htole32(rp->rpr_msgout.dma_paddr); 2602 mcr->mcr_opktbuf.pb_next = 0; 2603 mcr->mcr_opktbuf.pb_len = htole32(rp->rpr_msgout.dma_size); 2604 2605#ifdef DIAGNOSTIC 2606 if (rp->rpr_msgin.dma_paddr & 3 || rp->rpr_msgin.dma_size & 3) { 2607 panic("%s: rsapriv: invalid msgin %x(0x%jx)", 2608 device_get_nameunit(sc->sc_dev), 2609 rp->rpr_msgin.dma_paddr, (uintmax_t)rp->rpr_msgin.dma_size); 2610 } 2611 if (rp->rpr_msgout.dma_paddr & 3 || rp->rpr_msgout.dma_size & 3) { 2612 panic("%s: rsapriv: invalid msgout %x(0x%jx)", 2613 device_get_nameunit(sc->sc_dev), 2614 rp->rpr_msgout.dma_paddr, (uintmax_t)rp->rpr_msgout.dma_size); 2615 } 2616#endif 2617 2618 ctx->rpr_len = (sizeof(u_int16_t) * 4) + (5 * (padlen / 8)); 2619 ctx->rpr_op = htole16(UBS_CTXOP_RSAPRIV); 2620 ctx->rpr_q_len = htole16(padlen); 2621 ctx->rpr_p_len = htole16(padlen); 2622 2623 /* 2624 * ubsec_feed2 will sync mcr and ctx, we just need to sync 2625 * everything else. 2626 */ 2627 ubsec_dma_sync(&rp->rpr_msgin, BUS_DMASYNC_PREWRITE); 2628 ubsec_dma_sync(&rp->rpr_msgout, BUS_DMASYNC_PREREAD); 2629 2630 /* Enqueue and we're done... */ 2631 mtx_lock(&sc->sc_mcr2lock); 2632 SIMPLEQ_INSERT_TAIL(&sc->sc_queue2, &rp->rpr_q, q_next); 2633 ubsec_feed2(sc); 2634 ubsecstats.hst_modexpcrt++; 2635 mtx_unlock(&sc->sc_mcr2lock); 2636 return (0); 2637 2638errout: 2639 if (rp != NULL) { 2640 if (rp->rpr_q.q_mcr.dma_tag != NULL) 2641 ubsec_dma_free(sc, &rp->rpr_q.q_mcr); 2642 if (rp->rpr_msgin.dma_tag != NULL) { 2643 bzero(rp->rpr_msgin.dma_vaddr, rp->rpr_msgin.dma_size); 2644 ubsec_dma_free(sc, &rp->rpr_msgin); 2645 } 2646 if (rp->rpr_msgout.dma_tag != NULL) { 2647 bzero(rp->rpr_msgout.dma_vaddr, rp->rpr_msgout.dma_size); 2648 ubsec_dma_free(sc, &rp->rpr_msgout); 2649 } 2650 free(rp, M_DEVBUF); 2651 } 2652 krp->krp_status = err; 2653 crypto_kdone(krp); 2654 return (0); 2655} 2656 2657#ifdef UBSEC_DEBUG 2658static void 2659ubsec_dump_pb(volatile struct ubsec_pktbuf *pb) 2660{ 2661 printf("addr 0x%x (0x%x) next 0x%x\n", 2662 pb->pb_addr, pb->pb_len, pb->pb_next); 2663} 2664 2665static void 2666ubsec_dump_ctx2(struct ubsec_ctx_keyop *c) 2667{ 2668 printf("CTX (0x%x):\n", c->ctx_len); 2669 switch (letoh16(c->ctx_op)) { 2670 case UBS_CTXOP_RNGBYPASS: 2671 case UBS_CTXOP_RNGSHA1: 2672 break; 2673 case UBS_CTXOP_MODEXP: 2674 { 2675 struct ubsec_ctx_modexp *cx = (void *)c; 2676 int i, len; 2677 2678 printf(" Elen %u, Nlen %u\n", 2679 letoh16(cx->me_E_len), letoh16(cx->me_N_len)); 2680 len = (cx->me_N_len + 7)/8; 2681 for (i = 0; i < len; i++) 2682 printf("%s%02x", (i == 0) ? " N: " : ":", cx->me_N[i]); 2683 printf("\n"); 2684 break; 2685 } 2686 default: 2687 printf("unknown context: %x\n", c->ctx_op); 2688 } 2689 printf("END CTX\n"); 2690} 2691 2692static void 2693ubsec_dump_mcr(struct ubsec_mcr *mcr) 2694{ 2695 volatile struct ubsec_mcr_add *ma; 2696 int i; 2697 2698 printf("MCR:\n"); 2699 printf(" pkts: %u, flags 0x%x\n", 2700 letoh16(mcr->mcr_pkts), letoh16(mcr->mcr_flags)); 2701 ma = (volatile struct ubsec_mcr_add *)&mcr->mcr_cmdctxp; 2702 for (i = 0; i < letoh16(mcr->mcr_pkts); i++) { 2703 printf(" %d: ctx 0x%x len 0x%x rsvd 0x%x\n", i, 2704 letoh32(ma->mcr_cmdctxp), letoh16(ma->mcr_pktlen), 2705 letoh16(ma->mcr_reserved)); 2706 printf(" %d: ipkt ", i); 2707 ubsec_dump_pb(&ma->mcr_ipktbuf); 2708 printf(" %d: opkt ", i); 2709 ubsec_dump_pb(&ma->mcr_opktbuf); 2710 ma++; 2711 } 2712 printf("END MCR\n"); 2713} 2714#endif /* UBSEC_DEBUG */ 2715 2716/* 2717 * Return the number of significant bits of a big number. 2718 */ 2719static int 2720ubsec_ksigbits(struct crparam *cr) 2721{ 2722 u_int plen = (cr->crp_nbits + 7) / 8; 2723 int i, sig = plen * 8; 2724 u_int8_t c, *p = cr->crp_p; 2725 2726 for (i = plen - 1; i >= 0; i--) { 2727 c = p[i]; 2728 if (c != 0) { 2729 while ((c & 0x80) == 0) { 2730 sig--; 2731 c <<= 1; 2732 } 2733 break; 2734 } 2735 sig -= 8; 2736 } 2737 return (sig); 2738} 2739 2740static void 2741ubsec_kshift_r( 2742 u_int shiftbits, 2743 u_int8_t *src, u_int srcbits, 2744 u_int8_t *dst, u_int dstbits) 2745{ 2746 u_int slen, dlen; 2747 int i, si, di, n; 2748 2749 slen = (srcbits + 7) / 8; 2750 dlen = (dstbits + 7) / 8; 2751 2752 for (i = 0; i < slen; i++) 2753 dst[i] = src[i]; 2754 for (i = 0; i < dlen - slen; i++) 2755 dst[slen + i] = 0; 2756 2757 n = shiftbits / 8; 2758 if (n != 0) { 2759 si = dlen - n - 1; 2760 di = dlen - 1; 2761 while (si >= 0) 2762 dst[di--] = dst[si--]; 2763 while (di >= 0) 2764 dst[di--] = 0; 2765 } 2766 2767 n = shiftbits % 8; 2768 if (n != 0) { 2769 for (i = dlen - 1; i > 0; i--) 2770 dst[i] = (dst[i] << n) | 2771 (dst[i - 1] >> (8 - n)); 2772 dst[0] = dst[0] << n; 2773 } 2774} 2775 2776static void 2777ubsec_kshift_l( 2778 u_int shiftbits, 2779 u_int8_t *src, u_int srcbits, 2780 u_int8_t *dst, u_int dstbits) 2781{ 2782 int slen, dlen, i, n; 2783 2784 slen = (srcbits + 7) / 8; 2785 dlen = (dstbits + 7) / 8; 2786 2787 n = shiftbits / 8; 2788 for (i = 0; i < slen; i++) 2789 dst[i] = src[i + n]; 2790 for (i = 0; i < dlen - slen; i++) 2791 dst[slen + i] = 0; 2792 2793 n = shiftbits % 8; 2794 if (n != 0) { 2795 for (i = 0; i < (dlen - 1); i++) 2796 dst[i] = (dst[i] >> n) | (dst[i + 1] << (8 - n)); 2797 dst[dlen - 1] = dst[dlen - 1] >> n; 2798 } 2799} 2800