1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Benno Rice. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30#ifndef _IF_SMCREG_H_ 31#define _IF_SMCREG_H_ 32 33/* All Banks, Offset 0xe: Bank Select Register */ 34#define BSR 0xe 35#define BSR_BANK_MASK 0x0007 /* Which bank is currently selected */ 36#define BSR_IDENTIFY 0x3300 /* Static value for identification */ 37#define BSR_IDENTIFY_MASK 0xff00 38 39/* Bank 0, Offset 0x0: Transmit Control Register */ 40#define TCR 0x0 41#define TCR_TXENA 0x0001 /* Enable/disable transmitter */ 42#define TCR_LOOP 0x0002 /* Put the PHY into loopback mode */ 43#define TCR_FORCOL 0x0004 /* Force a collision */ 44#define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */ 45#define TCR_NOCRC 0x0100 /* Disable/enable CRC */ 46#define TCR_MON_CSN 0x0400 /* Monitor carrier signal */ 47#define TCR_FDUPLX 0x0800 /* Enable/disable full duplex */ 48#define TCR_STP_SQET 0x1000 /* Stop TX on signal quality error */ 49#define TCR_EPH_LOOP 0x2000 /* Internal loopback */ 50#define TCR_SWFDUP 0x8000 /* Switched full duplex */ 51 52/* Bank 0, Offset 0x2: EPH Status Register */ 53#define EPHSR 0x2 54#define EPHSR_TX_SUC 0x0001 /* Last TX was successful */ 55#define EPHSR_SNGLCOL 0x0002 /* Single collision on last TX */ 56#define EPHSR_MULCOL 0x0004 /* Multiple collisions on last TX */ 57#define EPHSR_LTX_MULT 0x0008 /* Last TX was multicast */ 58#define EPHSR_16COL 0x0010 /* 16 collisions on last TX */ 59#define EPHSR_SQET 0x0020 /* Signal quality error test */ 60#define EPHSR_LTX_BRD 0x0040 /* Last TX was broadcast */ 61#define EPHSR_TX_DEFR 0x0080 /* Transmit deferred */ 62#define EPHSR_LATCOL 0x0200 /* Late collision on last TX */ 63#define EPHSR_LOST_CARR 0x0400 /* Lost carrier sense */ 64#define EPHSR_EXC_DEF 0x0800 /* Excessive deferral */ 65#define EPHSR_CTR_ROL 0x1000 /* Counter rollover */ 66#define EPHSR_LINK_OK 0x4000 /* Inverse of nLNK pin */ 67#define EPHSR_TXUNRN 0x8000 /* Transmit underrun */ 68 69/* Bank 0, Offset 0x4: Receive Control Register */ 70#define RCR 0x4 71#define RCR_RX_ABORT 0x0001 /* RX aborted */ 72#define RCR_PRMS 0x0002 /* Enable/disable promiscuous mode */ 73#define RCR_ALMUL 0x0004 /* Accept all multicast frames */ 74#define RCR_RXEN 0x0100 /* Enable/disable receiver */ 75#define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */ 76#define RCR_ABORT_ENB 0x2000 /* Abort RX on collision */ 77#define RCR_FILT_CAR 0x4000 /* Filter leading 12 bits of carrier */ 78#define RCR_SOFT_RST 0x8000 /* Software reset */ 79 80/* Bank 0, Offset 0x6: Counter Register */ 81#define ECR 0x6 82#define ECR_SNGLCOL_MASK 0x000f /* Single collisions */ 83#define ECR_SNGLCOL_SHIFT 0 84#define ECR_MULCOL_MASK 0x00f0 /* Multiple collisions */ 85#define ECR_MULCOL_SHIFT 4 86#define ECR_TX_DEFR_MASK 0x0f00 /* Transmit deferrals */ 87#define ECR_TX_DEFR_SHIFT 8 88#define ECR_EXC_DEF_MASK 0xf000 /* Excessive deferrals */ 89#define ECR_EXC_DEF_SHIFT 12 90 91/* Bank 0, Offset 0x8: Memory Information Register */ 92#define MIR 0x8 93#define MIR_SIZE_MASK 0x00ff /* Memory size (2k pages) */ 94#define MIR_SIZE_SHIFT 0 95#define MIR_FREE_MASK 0xff00 /* Memory free (2k pages) */ 96#define MIR_FREE_SHIFT 8 97#define MIR_PAGE_SIZE 2048 98 99/* Bank 0, Offset 0xa: Receive/PHY Control Reigster */ 100#define RPCR 0xa 101#define RPCR_ANEG 0x0800 /* Put PHY in autonegotiation mode */ 102#define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */ 103#define RPCR_SPEED 0x2000 /* Manual speed selection */ 104#define RPCR_LSA_MASK 0x00e0 /* Select LED A function */ 105#define RPCR_LSA_SHIFT 5 106#define RPCR_LSB_MASK 0x001c /* Select LED B function */ 107#define RPCR_LSB_SHIFT 2 108#define RPCR_LED_LINK_ANY 0x0 /* 10baseT or 100baseTX link detected */ 109#define RPCR_LED_LINK_10 0x2 /* 10baseT link detected */ 110#define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detected */ 111#define RPCR_LED_LINK_100 0x5 /* 100baseTX link detected */ 112#define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */ 113#define RPCR_LED_ACT_RX 0x6 /* RX activity detected */ 114#define RPCR_LED_ACT_TX 0x7 /* TX activity detected */ 115 116/* Bank 1, Offset 0x0: Configuration Register */ 117#define CR 0x0 118#define CR_EXT_PHY 0x0200 /* Enable/disable external PHY */ 119#define CR_GPCNTRL 0x0400 /* Inverse drives nCNTRL pin */ 120#define CR_NO_WAIT 0x1000 /* Do not request additional waits */ 121#define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */ 122 123/* Bank 1, Offset 0x2: Base Address Register */ 124#define BAR 0x2 125#define BAR_HIGH_MASK 0xe000 126#define BAR_LOW_MASK 0x1f00 127#define BAR_LOW_SHIFT 4 128#define BAR_ADDRESS(val) \ 129 ((val & BAR_HIGH_MASK) | ((val & BAR_LOW_MASK) >> BAR_LOW_SHIFT)) 130 131/* Bank 1, Offsets 0x4: Individual Address Registers */ 132#define IAR0 0x4 133#define IAR1 0x5 134#define IAR2 0x6 135#define IAR3 0x7 136#define IAR4 0x8 137#define IAR5 0x9 138 139/* Bank 1, Offset 0xa: General Purpose Register */ 140#define GPR 0xa 141 142/* Bank 1, Offset 0xc: Control Register */ 143#define CTR 0xa 144#define CTR_STORE 0x0001 /* Store registers to EEPROM */ 145#define CTR_RELOAD 0x0002 /* Reload registers from EEPROM */ 146#define CTR_EEPROM_SELECT 0x0004 /* Select registers to store/reload */ 147#define CTR_TE_ENABLE 0x0020 /* TX error causes EPH interrupt */ 148#define CTR_CR_ENABLE 0x0040 /* Ctr rollover causes EPH interrupt */ 149#define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */ 150#define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */ 151#define CTR_RCV_BAD 0x4000 /* Receive/discard bad CRC packets */ 152 153/* Bank 2, Offset 0x0: MMU Command Register */ 154#define MMUCR 0x0 155#define MMUCR_BUSY 0x0001 /* MMU is busy */ 156#define MMUCR_CMD_NOOP (0<<5) /* No operation */ 157#define MMUCR_CMD_TX_ALLOC (1<<5) /* Alloc TX memory (256b chunks) */ 158#define MMUCR_CMD_MMU_RESET (2<<5) /* Reset MMU */ 159#define MMUCR_CMD_REMOVE (3<<5) /* Remove frame from RX FIFO */ 160#define MMUCR_CMD_RELEASE (4<<5) /* Remove and release from RX FIFO */ 161#define MMUCR_CMD_RELEASE_PKT (5<<5) /* Release packet specified in PNR */ 162#define MMUCR_CMD_ENQUEUE (6<<5) /* Enqueue packet for TX */ 163#define MMUCR_CMD_TX_RESET (7<<5) /* Reset TX FIFOs */ 164 165/* Bank 2, Offset 0x2: Packet Number Register */ 166#define PNR 0x2 167#define PNR_MASK 0x3fff 168 169/* Bank 2, Offset 0x3: Allocation Result Register */ 170#define ARR 0x3 171#define ARR_FAILED 0x8000 /* Last allocation request failed */ 172#define ARR_MASK 0x3000 173 174/* Bank 2, Offset 0x4: FIFO Ports Register */ 175#define FIFO_TX 0x4 176#define FIFO_RX 0x5 177#define FIFO_EMPTY 0x80 /* FIFO empty */ 178#define FIFO_PACKET_MASK 0x3f /* Packet number mask */ 179 180/* Bank 2, Offset 0x6: Pointer Register */ 181#define PTR 0x6 182#define PTR_MASK 0x07ff /* Address accessible within TX/RX */ 183#define PTR_NOT_EMPTY 0x0800 /* Write Data FIFO not empty */ 184#define PTR_ETEN 0x1000 /* Enable early TX underrun detection */ 185#define PTR_READ 0x2000 /* Set read/write */ 186#define PTR_AUTO_INCR 0x4000 /* Auto increment on read/write */ 187#define PTR_RCV 0x8000 /* Read/write to/from RX/TX */ 188 189/* Bank 2, Offset 0x8: Data Registers */ 190#define DATA0 0x8 191#define DATA1 0xa 192 193/* Bank 2, Offset 0xc: Interrupt Status Registers */ 194#define IST 0xc /* read only */ 195#define ACK 0xc /* write only */ 196#define MSK 0xd 197 198#define RCV_INT 0x0001 /* RX */ 199#define TX_INT 0x0002 /* TX */ 200#define TX_EMPTY_INT 0x0004 /* TX empty */ 201#define ALLOC_INT 0x0008 /* Allocation complete */ 202#define RX_OVRN_INT 0x0010 /* RX overrun */ 203#define EPH_INT 0x0020 /* EPH interrupt */ 204#define ERCV_INT 0x0040 /* Early RX */ 205#define MD_INT 0x0080 /* MII */ 206 207#define IST_PRINTF "\20\01RCV\02TX\03TX_EMPTY\04ALLOC" \ 208 "\05RX_OVRN\06EPH\07ERCV\10MD" 209 210/* Bank 3, Offset 0x0: Multicast Table Registers */ 211#define MT 0x0 212 213/* Bank 3, Offset 0x8: Management Interface */ 214#define MGMT 0x8 215#define MGMT_MDO 0x0001 /* MII management output */ 216#define MGMT_MDI 0x0002 /* MII management input */ 217#define MGMT_MCLK 0x0004 /* MII management clock */ 218#define MGMT_MDOE 0x0008 /* MII management output enable */ 219#define MGMT_MSK_CRS100 0x4000 /* Disable CRS100 detection during TX */ 220 221/* Bank 3, Offset 0xa: Revision Register */ 222#define REV 0xa 223#define REV_CHIP_MASK 0x00f0 /* Chip ID */ 224#define REV_CHIP_SHIFT 4 225#define REV_REV_MASK 0x000f /* Revision ID */ 226#define REV_REV_SHIFT 0 227 228#define REV_CHIP_9192 3 229#define REV_CHIP_9194 4 230#define REV_CHIP_9195 5 231#define REV_CHIP_9196 6 232#define REV_CHIP_91100 7 233#define REV_CHIP_91100FD 8 234#define REV_CHIP_91110FD 9 235 236/* Bank 3, Offset 0xc: Early RCV Register */ 237#define ERCV 0xc 238#define ERCV_THRESHOLD_MASK 0x001f /* ERCV int threshold (64b chunks) */ 239#define ERCV_RCV_DISCARD 0x0080 /* Discard packet being received */ 240 241/* Control Byte */ 242#define CTRL_CRC 0x10 /* Frame has CRC */ 243#define CTRL_ODD 0x20 /* Frame has odd byte count */ 244 245/* Receive Frame Status */ 246#define RX_MULTCAST 0x0001 /* Frame was multicast */ 247#define RX_HASH_MASK 0x007e /* Hash value for multicast */ 248#define RX_HASH_SHIFT 1 249#define RX_TOOSHORT 0x0400 /* Frame was too short */ 250#define RX_TOOLNG 0x0800 /* Frame was too long */ 251#define RX_ODDFRM 0x1000 /* Frame has odd number of bytes */ 252#define RX_BADCRC 0x2000 /* Frame failed CRC */ 253#define RX_BROADCAST 0x4000 /* Frame was broadcast */ 254#define RX_ALGNERR 0x8000 /* Frame had alignment error */ 255#define RX_LEN_MASK 0x07ff 256 257/* Length of status word + byte count + control bytes for packets */ 258#define PKT_CTRL_DATA_LEN 6 259 260/* Number of times to spin on TX allocations */ 261#define TX_ALLOC_WAIT_TIME 1000 262 263#endif /* IF_SMCREG_H_ */ 264