1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007-2016 Solarflare Communications Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * The views and conclusions contained in the software and documentation are 29 * those of the authors and should not be interpreted as representing official 30 * policies, either expressed or implied, of the FreeBSD Project. 31 * 32 * $FreeBSD$ 33 */ 34 35#ifndef _SYS_EFX_REGS_H 36#define _SYS_EFX_REGS_H 37 38 39#ifdef __cplusplus 40extern "C" { 41#endif 42 43 44/************************************************************************** 45 * 46 * Falcon/Siena registers and descriptors 47 * 48 ************************************************************************** 49 */ 50 51/* 52 * FR_AB_EE_VPD_CFG0_REG_SF(128bit): 53 * SPI/VPD configuration register 0 54 */ 55#define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300 56/* falcona0,falconb0=eeprom_flash */ 57/* 58 * FR_AB_EE_VPD_CFG0_REG(128bit): 59 * SPI/VPD configuration register 0 60 */ 61#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140 62/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 63 64#define FRF_AB_EE_SF_FASTRD_EN_LBN 127 65#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 66#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 67#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 68#define FRF_AB_EE_VPD_WIP_POLL_LBN 119 69#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 70#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 71#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 72#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 73#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 74#define FRF_AB_EE_VPDW_LENGTH_LBN 80 75#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 76#define FRF_AB_EE_VPDW_BASE_LBN 64 77#define FRF_AB_EE_VPDW_BASE_WIDTH 15 78#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 79#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 80#define FRF_AB_EE_VPD_BASE_LBN 32 81#define FRF_AB_EE_VPD_BASE_WIDTH 24 82#define FRF_AB_EE_VPD_LENGTH_LBN 16 83#define FRF_AB_EE_VPD_LENGTH_WIDTH 15 84#define FRF_AB_EE_VPD_AD_SIZE_LBN 8 85#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 86#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 87#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 88#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 89#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 90#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 91#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 92#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 93#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 94#define FRF_AB_EE_VPD_EN_LBN 0 95#define FRF_AB_EE_VPD_EN_WIDTH 1 96 97 98/* 99 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): 100 * PCIE SerDes control register 0 to 3 101 */ 102#define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320 103/* falcona0,falconb0=eeprom_flash */ 104/* 105 * FR_AB_PCIE_SD_CTL0123_REG(128bit): 106 * PCIE SerDes control register 0 to 3 107 */ 108#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320 109/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 110 111#define FRF_AB_PCIE_TESTSIG_H_LBN 96 112#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 113#define FRF_AB_PCIE_TESTSIG_L_LBN 64 114#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 115#define FRF_AB_PCIE_OFFSET_LBN 56 116#define FRF_AB_PCIE_OFFSET_WIDTH 8 117#define FRF_AB_PCIE_OFFSETEN_H_LBN 55 118#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 119#define FRF_AB_PCIE_OFFSETEN_L_LBN 54 120#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 121#define FRF_AB_PCIE_HIVMODE_H_LBN 53 122#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 123#define FRF_AB_PCIE_HIVMODE_L_LBN 52 124#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 125#define FRF_AB_PCIE_PARRESET_H_LBN 51 126#define FRF_AB_PCIE_PARRESET_H_WIDTH 1 127#define FRF_AB_PCIE_PARRESET_L_LBN 50 128#define FRF_AB_PCIE_PARRESET_L_WIDTH 1 129#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 130#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 131#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 132#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 133#define FRF_AB_PCIE_LPBK_LBN 40 134#define FRF_AB_PCIE_LPBK_WIDTH 8 135#define FRF_AB_PCIE_PARLPBK_LBN 32 136#define FRF_AB_PCIE_PARLPBK_WIDTH 8 137#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 138#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 139#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 140#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 141#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 142#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 143#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 144#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 145#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 146#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 147#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 148#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 149#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 150#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 151#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 152#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 153#define FRF_AB_PCIE_RXEQCTL_H_LBN 18 154#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 155#define FRF_AB_PCIE_RXEQCTL_L_LBN 16 156#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 157#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 158#define FFE_AB_PCIE_RXEQCTL_OFF 2 159#define FFE_AB_PCIE_RXEQCTL_MIN 1 160#define FFE_AB_PCIE_RXEQCTL_MAX 0 161#define FRF_AB_PCIE_HIDRV_LBN 8 162#define FRF_AB_PCIE_HIDRV_WIDTH 8 163#define FRF_AB_PCIE_LODRV_LBN 0 164#define FRF_AB_PCIE_LODRV_WIDTH 8 165 166 167/* 168 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): 169 * PCIE SerDes control register 4 and 5 170 */ 171#define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330 172/* falcona0,falconb0=eeprom_flash */ 173/* 174 * FR_AB_PCIE_SD_CTL45_REG(128bit): 175 * PCIE SerDes control register 4 and 5 176 */ 177#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330 178/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 179 180#define FRF_AB_PCIE_DTX7_LBN 60 181#define FRF_AB_PCIE_DTX7_WIDTH 4 182#define FRF_AB_PCIE_DTX6_LBN 56 183#define FRF_AB_PCIE_DTX6_WIDTH 4 184#define FRF_AB_PCIE_DTX5_LBN 52 185#define FRF_AB_PCIE_DTX5_WIDTH 4 186#define FRF_AB_PCIE_DTX4_LBN 48 187#define FRF_AB_PCIE_DTX4_WIDTH 4 188#define FRF_AB_PCIE_DTX3_LBN 44 189#define FRF_AB_PCIE_DTX3_WIDTH 4 190#define FRF_AB_PCIE_DTX2_LBN 40 191#define FRF_AB_PCIE_DTX2_WIDTH 4 192#define FRF_AB_PCIE_DTX1_LBN 36 193#define FRF_AB_PCIE_DTX1_WIDTH 4 194#define FRF_AB_PCIE_DTX0_LBN 32 195#define FRF_AB_PCIE_DTX0_WIDTH 4 196#define FRF_AB_PCIE_DEQ7_LBN 28 197#define FRF_AB_PCIE_DEQ7_WIDTH 4 198#define FRF_AB_PCIE_DEQ6_LBN 24 199#define FRF_AB_PCIE_DEQ6_WIDTH 4 200#define FRF_AB_PCIE_DEQ5_LBN 20 201#define FRF_AB_PCIE_DEQ5_WIDTH 4 202#define FRF_AB_PCIE_DEQ4_LBN 16 203#define FRF_AB_PCIE_DEQ4_WIDTH 4 204#define FRF_AB_PCIE_DEQ3_LBN 12 205#define FRF_AB_PCIE_DEQ3_WIDTH 4 206#define FRF_AB_PCIE_DEQ2_LBN 8 207#define FRF_AB_PCIE_DEQ2_WIDTH 4 208#define FRF_AB_PCIE_DEQ1_LBN 4 209#define FRF_AB_PCIE_DEQ1_WIDTH 4 210#define FRF_AB_PCIE_DEQ0_LBN 0 211#define FRF_AB_PCIE_DEQ0_WIDTH 4 212 213 214/* 215 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): 216 * PCIE PCS control and status register 217 */ 218#define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340 219/* falcona0,falconb0=eeprom_flash */ 220/* 221 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit): 222 * PCIE PCS control and status register 223 */ 224#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340 225/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 226 227#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 228#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 229#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 230#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 231#define FRF_AB_PCIE_PRBSERR_LBN 40 232#define FRF_AB_PCIE_PRBSERR_WIDTH 8 233#define FRF_AB_PCIE_PRBSERRH0_LBN 32 234#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 235#define FRF_AB_PCIE_FASTINIT_H_LBN 15 236#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 237#define FRF_AB_PCIE_FASTINIT_L_LBN 14 238#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 239#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 240#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 241#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 242#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 243#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 244#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 245#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 246#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 247#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 248#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 249#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 250#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 251#define FRF_AB_PCIE_PRBSSEL_LBN 0 252#define FRF_AB_PCIE_PRBSSEL_WIDTH 8 253 254 255/* 256 * FR_AB_HW_INIT_REG_SF(128bit): 257 * Hardware initialization register 258 */ 259#define FR_AB_HW_INIT_REG_SF_OFST 0x00000350 260/* falcona0,falconb0=eeprom_flash */ 261/* 262 * FR_AZ_HW_INIT_REG(128bit): 263 * Hardware initialization register 264 */ 265#define FR_AZ_HW_INIT_REG_OFST 0x000000c0 266/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 267 268#define FRF_BB_BDMRD_CPLF_FULL_LBN 124 269#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 270#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 271#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 272#define FRF_CZ_TX_MRG_TAGS_LBN 120 273#define FRF_CZ_TX_MRG_TAGS_WIDTH 1 274#define FRF_AZ_TRGT_MASK_ALL_LBN 100 275#define FRF_AZ_TRGT_MASK_ALL_WIDTH 1 276#define FRF_AZ_DOORBELL_DROP_LBN 92 277#define FRF_AZ_DOORBELL_DROP_WIDTH 8 278#define FRF_AB_TX_RREQ_MASK_EN_LBN 76 279#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 280#define FRF_AB_PE_EIDLE_DIS_LBN 75 281#define FRF_AB_PE_EIDLE_DIS_WIDTH 1 282#define FRF_AZ_FC_BLOCKING_EN_LBN 45 283#define FRF_AZ_FC_BLOCKING_EN_WIDTH 1 284#define FRF_AZ_B2B_REQ_EN_LBN 44 285#define FRF_AZ_B2B_REQ_EN_WIDTH 1 286#define FRF_AZ_POST_WR_MASK_LBN 40 287#define FRF_AZ_POST_WR_MASK_WIDTH 4 288#define FRF_AZ_TLP_TC_LBN 34 289#define FRF_AZ_TLP_TC_WIDTH 3 290#define FRF_AZ_TLP_ATTR_LBN 32 291#define FRF_AZ_TLP_ATTR_WIDTH 2 292#define FRF_AB_INTB_VEC_LBN 24 293#define FRF_AB_INTB_VEC_WIDTH 5 294#define FRF_AB_INTA_VEC_LBN 16 295#define FRF_AB_INTA_VEC_WIDTH 5 296#define FRF_AZ_WD_TIMER_LBN 8 297#define FRF_AZ_WD_TIMER_WIDTH 8 298#define FRF_AZ_US_DISABLE_LBN 5 299#define FRF_AZ_US_DISABLE_WIDTH 1 300#define FRF_AZ_TLP_EP_LBN 4 301#define FRF_AZ_TLP_EP_WIDTH 1 302#define FRF_AZ_ATTR_SEL_LBN 3 303#define FRF_AZ_ATTR_SEL_WIDTH 1 304#define FRF_AZ_TD_SEL_LBN 1 305#define FRF_AZ_TD_SEL_WIDTH 1 306#define FRF_AZ_TLP_TD_LBN 0 307#define FRF_AZ_TLP_TD_WIDTH 1 308 309 310/* 311 * FR_AB_NIC_STAT_REG_SF(128bit): 312 * NIC status register 313 */ 314#define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360 315/* falcona0,falconb0=eeprom_flash */ 316/* 317 * FR_AB_NIC_STAT_REG(128bit): 318 * NIC status register 319 */ 320#define FR_AB_NIC_STAT_REG_OFST 0x00000200 321/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 322 323#define FRF_BB_AER_DIS_LBN 34 324#define FRF_BB_AER_DIS_WIDTH 1 325#define FRF_BB_EE_STRAP_EN_LBN 31 326#define FRF_BB_EE_STRAP_EN_WIDTH 1 327#define FRF_BB_EE_STRAP_LBN 24 328#define FRF_BB_EE_STRAP_WIDTH 4 329#define FRF_BB_REVISION_ID_LBN 17 330#define FRF_BB_REVISION_ID_WIDTH 7 331#define FRF_AB_ONCHIP_SRAM_LBN 16 332#define FRF_AB_ONCHIP_SRAM_WIDTH 1 333#define FRF_AB_SF_PRST_LBN 9 334#define FRF_AB_SF_PRST_WIDTH 1 335#define FRF_AB_EE_PRST_LBN 8 336#define FRF_AB_EE_PRST_WIDTH 1 337#define FRF_AB_ATE_MODE_LBN 3 338#define FRF_AB_ATE_MODE_WIDTH 1 339#define FRF_AB_STRAP_PINS_LBN 0 340#define FRF_AB_STRAP_PINS_WIDTH 3 341 342 343/* 344 * FR_AB_GLB_CTL_REG_SF(128bit): 345 * Global control register 346 */ 347#define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370 348/* falcona0,falconb0=eeprom_flash */ 349/* 350 * FR_AB_GLB_CTL_REG(128bit): 351 * Global control register 352 */ 353#define FR_AB_GLB_CTL_REG_OFST 0x00000220 354/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 355 356#define FRF_AB_EXT_PHY_RST_CTL_LBN 63 357#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 358#define FRF_AB_XAUI_SD_RST_CTL_LBN 62 359#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 360#define FRF_AB_PCIE_SD_RST_CTL_LBN 61 361#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 362#define FRF_AA_PCIX_RST_CTL_LBN 60 363#define FRF_AA_PCIX_RST_CTL_WIDTH 1 364#define FRF_BB_BIU_RST_CTL_LBN 60 365#define FRF_BB_BIU_RST_CTL_WIDTH 1 366#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 367#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 368#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 369#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 370#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 371#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 372#define FRF_AB_XGRX_RST_CTL_LBN 56 373#define FRF_AB_XGRX_RST_CTL_WIDTH 1 374#define FRF_AB_XGTX_RST_CTL_LBN 55 375#define FRF_AB_XGTX_RST_CTL_WIDTH 1 376#define FRF_AB_EM_RST_CTL_LBN 54 377#define FRF_AB_EM_RST_CTL_WIDTH 1 378#define FRF_AB_EV_RST_CTL_LBN 53 379#define FRF_AB_EV_RST_CTL_WIDTH 1 380#define FRF_AB_SR_RST_CTL_LBN 52 381#define FRF_AB_SR_RST_CTL_WIDTH 1 382#define FRF_AB_RX_RST_CTL_LBN 51 383#define FRF_AB_RX_RST_CTL_WIDTH 1 384#define FRF_AB_TX_RST_CTL_LBN 50 385#define FRF_AB_TX_RST_CTL_WIDTH 1 386#define FRF_AB_EE_RST_CTL_LBN 49 387#define FRF_AB_EE_RST_CTL_WIDTH 1 388#define FRF_AB_CS_RST_CTL_LBN 48 389#define FRF_AB_CS_RST_CTL_WIDTH 1 390#define FRF_AB_HOT_RST_CTL_LBN 40 391#define FRF_AB_HOT_RST_CTL_WIDTH 2 392#define FRF_AB_RST_EXT_PHY_LBN 31 393#define FRF_AB_RST_EXT_PHY_WIDTH 1 394#define FRF_AB_RST_XAUI_SD_LBN 30 395#define FRF_AB_RST_XAUI_SD_WIDTH 1 396#define FRF_AB_RST_PCIE_SD_LBN 29 397#define FRF_AB_RST_PCIE_SD_WIDTH 1 398#define FRF_AA_RST_PCIX_LBN 28 399#define FRF_AA_RST_PCIX_WIDTH 1 400#define FRF_BB_RST_BIU_LBN 28 401#define FRF_BB_RST_BIU_WIDTH 1 402#define FRF_AB_RST_PCIE_STKY_LBN 27 403#define FRF_AB_RST_PCIE_STKY_WIDTH 1 404#define FRF_AB_RST_PCIE_NSTKY_LBN 26 405#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 406#define FRF_AB_RST_PCIE_CORE_LBN 25 407#define FRF_AB_RST_PCIE_CORE_WIDTH 1 408#define FRF_AB_RST_XGRX_LBN 24 409#define FRF_AB_RST_XGRX_WIDTH 1 410#define FRF_AB_RST_XGTX_LBN 23 411#define FRF_AB_RST_XGTX_WIDTH 1 412#define FRF_AB_RST_EM_LBN 22 413#define FRF_AB_RST_EM_WIDTH 1 414#define FRF_AB_RST_EV_LBN 21 415#define FRF_AB_RST_EV_WIDTH 1 416#define FRF_AB_RST_SR_LBN 20 417#define FRF_AB_RST_SR_WIDTH 1 418#define FRF_AB_RST_RX_LBN 19 419#define FRF_AB_RST_RX_WIDTH 1 420#define FRF_AB_RST_TX_LBN 18 421#define FRF_AB_RST_TX_WIDTH 1 422#define FRF_AB_RST_SF_LBN 17 423#define FRF_AB_RST_SF_WIDTH 1 424#define FRF_AB_RST_CS_LBN 16 425#define FRF_AB_RST_CS_WIDTH 1 426#define FRF_AB_INT_RST_DUR_LBN 4 427#define FRF_AB_INT_RST_DUR_WIDTH 3 428#define FRF_AB_EXT_PHY_RST_DUR_LBN 1 429#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 430#define FFE_AB_EXT_PHY_RST_DUR_10240US 7 431#define FFE_AB_EXT_PHY_RST_DUR_5120US 6 432#define FFE_AB_EXT_PHY_RST_DUR_2560US 5 433#define FFE_AB_EXT_PHY_RST_DUR_1280US 4 434#define FFE_AB_EXT_PHY_RST_DUR_640US 3 435#define FFE_AB_EXT_PHY_RST_DUR_320US 2 436#define FFE_AB_EXT_PHY_RST_DUR_160US 1 437#define FFE_AB_EXT_PHY_RST_DUR_80US 0 438#define FRF_AB_SWRST_LBN 0 439#define FRF_AB_SWRST_WIDTH 1 440 441 442/* 443 * FR_AZ_IOM_IND_ADR_REG(32bit): 444 * IO-mapped indirect access address register 445 */ 446#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000 447/* falcona0,falconb0,sienaa0=net_func_bar0 */ 448 449#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24 450#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1 451#define FRF_AZ_IOM_IND_ADR_LBN 0 452#define FRF_AZ_IOM_IND_ADR_WIDTH 24 453 454 455/* 456 * FR_AZ_IOM_IND_DAT_REG(32bit): 457 * IO-mapped indirect access data register 458 */ 459#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004 460/* falcona0,falconb0,sienaa0=net_func_bar0 */ 461 462#define FRF_AZ_IOM_IND_DAT_LBN 0 463#define FRF_AZ_IOM_IND_DAT_WIDTH 32 464 465 466/* 467 * FR_AZ_ADR_REGION_REG(128bit): 468 * Address region register 469 */ 470#define FR_AZ_ADR_REGION_REG_OFST 0x00000000 471/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 472 473#define FRF_AZ_ADR_REGION3_LBN 96 474#define FRF_AZ_ADR_REGION3_WIDTH 18 475#define FRF_AZ_ADR_REGION2_LBN 64 476#define FRF_AZ_ADR_REGION2_WIDTH 18 477#define FRF_AZ_ADR_REGION1_LBN 32 478#define FRF_AZ_ADR_REGION1_WIDTH 18 479#define FRF_AZ_ADR_REGION0_LBN 0 480#define FRF_AZ_ADR_REGION0_WIDTH 18 481 482 483/* 484 * FR_AZ_INT_EN_REG_KER(128bit): 485 * Kernel driver Interrupt enable register 486 */ 487#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010 488/* falcona0,falconb0,sienaa0=net_func_bar2 */ 489 490#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 491#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 492#define FRF_AZ_KER_INT_CHAR_LBN 4 493#define FRF_AZ_KER_INT_CHAR_WIDTH 1 494#define FRF_AZ_KER_INT_KER_LBN 3 495#define FRF_AZ_KER_INT_KER_WIDTH 1 496#define FRF_AZ_DRV_INT_EN_KER_LBN 0 497#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 498 499 500/* 501 * FR_AZ_INT_EN_REG_CHAR(128bit): 502 * Char Driver interrupt enable register 503 */ 504#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020 505/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 506 507#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8 508#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6 509#define FRF_AZ_CHAR_INT_CHAR_LBN 4 510#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1 511#define FRF_AZ_CHAR_INT_KER_LBN 3 512#define FRF_AZ_CHAR_INT_KER_WIDTH 1 513#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 514#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 515 516 517/* 518 * FR_AZ_INT_ADR_REG_KER(128bit): 519 * Interrupt host address for Kernel driver 520 */ 521#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030 522/* falcona0,falconb0,sienaa0=net_func_bar2 */ 523 524#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 525#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 526#define FRF_AZ_INT_ADR_KER_LBN 0 527#define FRF_AZ_INT_ADR_KER_WIDTH 64 528#define FRF_AZ_INT_ADR_KER_DW0_LBN 0 529#define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32 530#define FRF_AZ_INT_ADR_KER_DW1_LBN 32 531#define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 532 533 534/* 535 * FR_AZ_INT_ADR_REG_CHAR(128bit): 536 * Interrupt host address for Char driver 537 */ 538#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040 539/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 540 541#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64 542#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 543#define FRF_AZ_INT_ADR_CHAR_LBN 0 544#define FRF_AZ_INT_ADR_CHAR_WIDTH 64 545#define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0 546#define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32 547#define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 548#define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 549 550 551/* 552 * FR_AA_INT_ACK_KER(32bit): 553 * Kernel interrupt acknowledge register 554 */ 555#define FR_AA_INT_ACK_KER_OFST 0x00000050 556/* falcona0=net_func_bar2 */ 557 558#define FRF_AA_INT_ACK_KER_FIELD_LBN 0 559#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 560 561 562/* 563 * FR_BZ_INT_ISR0_REG(128bit): 564 * Function 0 Interrupt Acknowlege Status register 565 */ 566#define FR_BZ_INT_ISR0_REG_OFST 0x00000090 567/* falconb0,sienaa0=net_func_bar2 */ 568 569#define FRF_BZ_INT_ISR_REG_LBN 0 570#define FRF_BZ_INT_ISR_REG_WIDTH 64 571#define FRF_BZ_INT_ISR_REG_DW0_LBN 0 572#define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32 573#define FRF_BZ_INT_ISR_REG_DW1_LBN 32 574#define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 575 576 577/* 578 * FR_AB_EE_SPI_HCMD_REG(128bit): 579 * SPI host command register 580 */ 581#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100 582/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 583 584#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 585#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 586#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 587#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 588#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 589#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 590#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 591#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 592#define FRF_AB_EE_SPI_HCMD_READ_LBN 15 593#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 594#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 595#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 596#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 597#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 598#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 599#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 600 601 602/* 603 * FR_CZ_USR_EV_CFG(32bit): 604 * User Level Event Configuration register 605 */ 606#define FR_CZ_USR_EV_CFG_OFST 0x00000100 607/* sienaa0=net_func_bar2 */ 608 609#define FRF_CZ_USREV_DIS_LBN 16 610#define FRF_CZ_USREV_DIS_WIDTH 1 611#define FRF_CZ_DFLT_EVQ_LBN 0 612#define FRF_CZ_DFLT_EVQ_WIDTH 10 613 614 615/* 616 * FR_AB_EE_SPI_HADR_REG(128bit): 617 * SPI host address register 618 */ 619#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110 620/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 621 622#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 623#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 624#define FRF_AB_EE_SPI_HADR_ADR_LBN 0 625#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 626 627 628/* 629 * FR_AB_EE_SPI_HDATA_REG(128bit): 630 * SPI host data register 631 */ 632#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120 633/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 634 635#define FRF_AB_EE_SPI_HDATA3_LBN 96 636#define FRF_AB_EE_SPI_HDATA3_WIDTH 32 637#define FRF_AB_EE_SPI_HDATA2_LBN 64 638#define FRF_AB_EE_SPI_HDATA2_WIDTH 32 639#define FRF_AB_EE_SPI_HDATA1_LBN 32 640#define FRF_AB_EE_SPI_HDATA1_WIDTH 32 641#define FRF_AB_EE_SPI_HDATA0_LBN 0 642#define FRF_AB_EE_SPI_HDATA0_WIDTH 32 643 644 645/* 646 * FR_AB_EE_BASE_PAGE_REG(128bit): 647 * Expansion ROM base mirror register 648 */ 649#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130 650/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 651 652#define FRF_AB_EE_EXPROM_MASK_LBN 16 653#define FRF_AB_EE_EXPROM_MASK_WIDTH 13 654#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 655#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 656 657 658/* 659 * FR_AB_EE_VPD_SW_CNTL_REG(128bit): 660 * VPD access SW control register 661 */ 662#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150 663/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 664 665#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 666#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 667#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 668#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 669#define FRF_AB_EE_VPD_CYC_ADR_LBN 0 670#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 671 672 673/* 674 * FR_AB_EE_VPD_SW_DATA_REG(128bit): 675 * VPD access SW data register 676 */ 677#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160 678/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 679 680#define FRF_AB_EE_VPD_CYC_DAT_LBN 0 681#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 682 683 684/* 685 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): 686 * Indirect Access to PCIE Core registers 687 */ 688#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0 689/* falconb0=net_func_bar2 */ 690 691#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 692#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 693#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 694#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 695#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 696#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 697 698 699/* 700 * FR_AB_GPIO_CTL_REG(128bit): 701 * GPIO control register 702 */ 703#define FR_AB_GPIO_CTL_REG_OFST 0x00000210 704/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 705 706#define FRF_AB_GPIO15_OEN_LBN 63 707#define FRF_AB_GPIO15_OEN_WIDTH 1 708#define FRF_AB_GPIO14_OEN_LBN 62 709#define FRF_AB_GPIO14_OEN_WIDTH 1 710#define FRF_AB_GPIO13_OEN_LBN 61 711#define FRF_AB_GPIO13_OEN_WIDTH 1 712#define FRF_AB_GPIO12_OEN_LBN 60 713#define FRF_AB_GPIO12_OEN_WIDTH 1 714#define FRF_AB_GPIO11_OEN_LBN 59 715#define FRF_AB_GPIO11_OEN_WIDTH 1 716#define FRF_AB_GPIO10_OEN_LBN 58 717#define FRF_AB_GPIO10_OEN_WIDTH 1 718#define FRF_AB_GPIO9_OEN_LBN 57 719#define FRF_AB_GPIO9_OEN_WIDTH 1 720#define FRF_AB_GPIO8_OEN_LBN 56 721#define FRF_AB_GPIO8_OEN_WIDTH 1 722#define FRF_AB_GPIO15_OUT_LBN 55 723#define FRF_AB_GPIO15_OUT_WIDTH 1 724#define FRF_AB_GPIO14_OUT_LBN 54 725#define FRF_AB_GPIO14_OUT_WIDTH 1 726#define FRF_AB_GPIO13_OUT_LBN 53 727#define FRF_AB_GPIO13_OUT_WIDTH 1 728#define FRF_AB_GPIO12_OUT_LBN 52 729#define FRF_AB_GPIO12_OUT_WIDTH 1 730#define FRF_AB_GPIO11_OUT_LBN 51 731#define FRF_AB_GPIO11_OUT_WIDTH 1 732#define FRF_AB_GPIO10_OUT_LBN 50 733#define FRF_AB_GPIO10_OUT_WIDTH 1 734#define FRF_AB_GPIO9_OUT_LBN 49 735#define FRF_AB_GPIO9_OUT_WIDTH 1 736#define FRF_AB_GPIO8_OUT_LBN 48 737#define FRF_AB_GPIO8_OUT_WIDTH 1 738#define FRF_AB_GPIO15_IN_LBN 47 739#define FRF_AB_GPIO15_IN_WIDTH 1 740#define FRF_AB_GPIO14_IN_LBN 46 741#define FRF_AB_GPIO14_IN_WIDTH 1 742#define FRF_AB_GPIO13_IN_LBN 45 743#define FRF_AB_GPIO13_IN_WIDTH 1 744#define FRF_AB_GPIO12_IN_LBN 44 745#define FRF_AB_GPIO12_IN_WIDTH 1 746#define FRF_AB_GPIO11_IN_LBN 43 747#define FRF_AB_GPIO11_IN_WIDTH 1 748#define FRF_AB_GPIO10_IN_LBN 42 749#define FRF_AB_GPIO10_IN_WIDTH 1 750#define FRF_AB_GPIO9_IN_LBN 41 751#define FRF_AB_GPIO9_IN_WIDTH 1 752#define FRF_AB_GPIO8_IN_LBN 40 753#define FRF_AB_GPIO8_IN_WIDTH 1 754#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 755#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 756#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 757#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 758#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 759#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 760#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 761#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 762#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 763#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 764#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 765#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 766#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 767#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 768#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 769#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 770#define FRF_BB_CLK156_OUT_EN_LBN 31 771#define FRF_BB_CLK156_OUT_EN_WIDTH 1 772#define FRF_BB_USE_NIC_CLK_LBN 30 773#define FRF_BB_USE_NIC_CLK_WIDTH 1 774#define FRF_AB_GPIO5_OEN_LBN 29 775#define FRF_AB_GPIO5_OEN_WIDTH 1 776#define FRF_AB_GPIO4_OEN_LBN 28 777#define FRF_AB_GPIO4_OEN_WIDTH 1 778#define FRF_AB_GPIO3_OEN_LBN 27 779#define FRF_AB_GPIO3_OEN_WIDTH 1 780#define FRF_AB_GPIO2_OEN_LBN 26 781#define FRF_AB_GPIO2_OEN_WIDTH 1 782#define FRF_AB_GPIO1_OEN_LBN 25 783#define FRF_AB_GPIO1_OEN_WIDTH 1 784#define FRF_AB_GPIO0_OEN_LBN 24 785#define FRF_AB_GPIO0_OEN_WIDTH 1 786#define FRF_AB_GPIO5_OUT_LBN 21 787#define FRF_AB_GPIO5_OUT_WIDTH 1 788#define FRF_AB_GPIO4_OUT_LBN 20 789#define FRF_AB_GPIO4_OUT_WIDTH 1 790#define FRF_AB_GPIO3_OUT_LBN 19 791#define FRF_AB_GPIO3_OUT_WIDTH 1 792#define FRF_AB_GPIO2_OUT_LBN 18 793#define FRF_AB_GPIO2_OUT_WIDTH 1 794#define FRF_AB_GPIO1_OUT_LBN 17 795#define FRF_AB_GPIO1_OUT_WIDTH 1 796#define FRF_AB_GPIO0_OUT_LBN 16 797#define FRF_AB_GPIO0_OUT_WIDTH 1 798#define FRF_AB_GPIO5_IN_LBN 13 799#define FRF_AB_GPIO5_IN_WIDTH 1 800#define FRF_AB_GPIO4_IN_LBN 12 801#define FRF_AB_GPIO4_IN_WIDTH 1 802#define FRF_AB_GPIO3_IN_LBN 11 803#define FRF_AB_GPIO3_IN_WIDTH 1 804#define FRF_AB_GPIO2_IN_LBN 10 805#define FRF_AB_GPIO2_IN_WIDTH 1 806#define FRF_AB_GPIO1_IN_LBN 9 807#define FRF_AB_GPIO1_IN_WIDTH 1 808#define FRF_AB_GPIO0_IN_LBN 8 809#define FRF_AB_GPIO0_IN_WIDTH 1 810#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 811#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 812#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 813#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 814#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 815#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 816#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 817#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 818#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 819#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 820#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 821#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 822 823 824/* 825 * FR_AZ_FATAL_INTR_REG_KER(128bit): 826 * Fatal interrupt register for Kernel 827 */ 828#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230 829/* falcona0,falconb0,sienaa0=net_func_bar2 */ 830 831#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 832#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 833#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 834#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 835#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 836#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 837#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 838#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 839#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 840#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 841#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 842#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 843#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 844#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 845#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 846#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 847#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 848#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 849#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 850#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 851#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 852#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 853#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 854#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 855#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 856#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 857#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 858#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 859#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 860#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 861#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 862#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 863#define FRF_CZ_MBU_PERR_INT_KER_LBN 11 864#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 865#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 866#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 867#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 868#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 869#define FRF_AZ_MEM_PERR_INT_KER_LBN 8 870#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 871#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 872#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 873#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 874#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 875#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 876#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 877#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 878#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 879#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 880#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 881#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 882#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 883#define FRF_AZ_ILL_ADR_INT_KER_LBN 1 884#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 885#define FRF_AZ_SRM_PERR_INT_KER_LBN 0 886#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 887 888 889/* 890 * FR_AZ_FATAL_INTR_REG_CHAR(128bit): 891 * Fatal interrupt register for Char 892 */ 893#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240 894/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 895 896#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 897#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 898#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43 899#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 900#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 901#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 902#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42 903#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 904#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41 905#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 906#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40 907#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 908#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39 909#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 910#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38 911#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 912#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 913#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 914#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 915#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 916#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35 917#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 918#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34 919#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 920#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33 921#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 922#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32 923#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 924#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 925#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 926#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11 927#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1 928#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 929#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 930#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10 931#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1 932#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9 933#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 934#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8 935#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1 936#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7 937#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1 938#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6 939#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1 940#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5 941#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 942#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4 943#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 944#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3 945#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1 946#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2 947#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1 948#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1 949#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1 950#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 951#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 952 953 954/* 955 * FR_AZ_DP_CTRL_REG(128bit): 956 * Datapath control register 957 */ 958#define FR_AZ_DP_CTRL_REG_OFST 0x00000250 959/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 960 961#define FRF_AZ_FLS_EVQ_ID_LBN 0 962#define FRF_AZ_FLS_EVQ_ID_WIDTH 12 963 964 965/* 966 * FR_AZ_MEM_STAT_REG(128bit): 967 * Memory status register 968 */ 969#define FR_AZ_MEM_STAT_REG_OFST 0x00000260 970/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 971 972#define FRF_AB_MEM_PERR_VEC_LBN 53 973#define FRF_AB_MEM_PERR_VEC_WIDTH 40 974#define FRF_AB_MEM_PERR_VEC_DW0_LBN 53 975#define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32 976#define FRF_AB_MEM_PERR_VEC_DW1_LBN 85 977#define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6 978#define FRF_AB_MBIST_CORR_LBN 38 979#define FRF_AB_MBIST_CORR_WIDTH 15 980#define FRF_AB_MBIST_ERR_LBN 0 981#define FRF_AB_MBIST_ERR_WIDTH 40 982#define FRF_AB_MBIST_ERR_DW0_LBN 0 983#define FRF_AB_MBIST_ERR_DW0_WIDTH 32 984#define FRF_AB_MBIST_ERR_DW1_LBN 32 985#define FRF_AB_MBIST_ERR_DW1_WIDTH 6 986#define FRF_CZ_MEM_PERR_VEC_LBN 0 987#define FRF_CZ_MEM_PERR_VEC_WIDTH 35 988#define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0 989#define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32 990#define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 991#define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 992 993 994/* 995 * FR_PORT0_CS_DEBUG_REG(128bit): 996 * Debug register 997 */ 998 999#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270 1000/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1001 1002#define FRF_AB_GLB_DEBUG2_SEL_LBN 50 1003#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 1004#define FRF_AB_DEBUG_BLK_SEL2_LBN 47 1005#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 1006#define FRF_AB_DEBUG_BLK_SEL1_LBN 44 1007#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 1008#define FRF_AB_DEBUG_BLK_SEL0_LBN 41 1009#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 1010#define FRF_CZ_CS_PORT_NUM_LBN 40 1011#define FRF_CZ_CS_PORT_NUM_WIDTH 2 1012#define FRF_AB_MISC_DEBUG_ADDR_LBN 36 1013#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 1014#define FRF_CZ_CS_RESERVED_LBN 36 1015#define FRF_CZ_CS_RESERVED_WIDTH 4 1016#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 1017#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 1018#define FRF_CZ_CS_PORT_FPE_DW0_LBN 1 1019#define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32 1020#define FRF_CZ_CS_PORT_FPE_DW1_LBN 33 1021#define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3 1022#define FRF_CZ_CS_PORT_FPE_LBN 1 1023#define FRF_CZ_CS_PORT_FPE_WIDTH 35 1024#define FRF_AB_EM_DEBUG_ADDR_LBN 26 1025#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 1026#define FRF_AB_SR_DEBUG_ADDR_LBN 21 1027#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 1028#define FRF_AB_EV_DEBUG_ADDR_LBN 16 1029#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 1030#define FRF_AB_RX_DEBUG_ADDR_LBN 11 1031#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 1032#define FRF_AB_TX_DEBUG_ADDR_LBN 6 1033#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 1034#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 1035#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 1036#define FRF_AZ_CS_DEBUG_EN_LBN 0 1037#define FRF_AZ_CS_DEBUG_EN_WIDTH 1 1038 1039 1040/* 1041 * FR_AZ_DRIVER_REG(128bit): 1042 * Driver scratch register [0-7] 1043 */ 1044#define FR_AZ_DRIVER_REG_OFST 0x00000280 1045/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1046#define FR_AZ_DRIVER_REG_STEP 16 1047#define FR_AZ_DRIVER_REG_ROWS 8 1048 1049#define FRF_AZ_DRIVER_DW0_LBN 0 1050#define FRF_AZ_DRIVER_DW0_WIDTH 32 1051 1052 1053/* 1054 * FR_AZ_ALTERA_BUILD_REG(128bit): 1055 * Altera build register 1056 */ 1057#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300 1058/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1059 1060#define FRF_AZ_ALTERA_BUILD_VER_LBN 0 1061#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 1062 1063 1064/* 1065 * FR_AZ_CSR_SPARE_REG(128bit): 1066 * Spare register 1067 */ 1068#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310 1069/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1070 1071#define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72 1072#define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2 1073#define FRF_AZ_MEM_PERR_EN_LBN 64 1074#define FRF_AZ_MEM_PERR_EN_WIDTH 38 1075#define FRF_AZ_MEM_PERR_EN_DW0_LBN 64 1076#define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32 1077#define FRF_AZ_MEM_PERR_EN_DW1_LBN 96 1078#define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6 1079#define FRF_AZ_CSR_SPARE_BITS_LBN 0 1080#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 1081 1082 1083/* 1084 * FR_BZ_DEBUG_DATA_OUT_REG(128bit): 1085 * Live Debug and Debug 2 out ports 1086 */ 1087#define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350 1088/* falconb0,sienaa0=net_func_bar2 */ 1089 1090#define FRF_BZ_DEBUG2_PORT_LBN 25 1091#define FRF_BZ_DEBUG2_PORT_WIDTH 15 1092#define FRF_BZ_DEBUG1_PORT_LBN 0 1093#define FRF_BZ_DEBUG1_PORT_WIDTH 25 1094 1095 1096/* 1097 * FR_BZ_EVQ_RPTR_REGP0(32bit): 1098 * Event queue read pointer register 1099 */ 1100#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400 1101/* falconb0,sienaa0=net_func_bar2 */ 1102#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192 1103#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024 1104/* 1105 * FR_AA_EVQ_RPTR_REG_KER(32bit): 1106 * Event queue read pointer register 1107 */ 1108#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00 1109/* falcona0=net_func_bar2 */ 1110#define FR_AA_EVQ_RPTR_REG_KER_STEP 4 1111#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4 1112/* 1113 * FR_AZ_EVQ_RPTR_REG(32bit): 1114 * Event queue read pointer register 1115 */ 1116#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000 1117/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1118#define FR_AZ_EVQ_RPTR_REG_STEP 16 1119#define FR_AB_EVQ_RPTR_REG_ROWS 4096 1120#define FR_CZ_EVQ_RPTR_REG_ROWS 1024 1121/* 1122 * FR_BB_EVQ_RPTR_REGP123(32bit): 1123 * Event queue read pointer register 1124 */ 1125#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400 1126/* falconb0=net_func_bar2 */ 1127#define FR_BB_EVQ_RPTR_REGP123_STEP 8192 1128#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072 1129 1130#define FRF_AZ_EVQ_RPTR_VLD_LBN 15 1131#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 1132#define FRF_AZ_EVQ_RPTR_LBN 0 1133#define FRF_AZ_EVQ_RPTR_WIDTH 15 1134 1135 1136/* 1137 * FR_BZ_TIMER_COMMAND_REGP0(128bit): 1138 * Timer Command Registers 1139 */ 1140#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420 1141/* falconb0,sienaa0=net_func_bar2 */ 1142#define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192 1143#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024 1144/* 1145 * FR_AA_TIMER_COMMAND_REG_KER(128bit): 1146 * Timer Command Registers 1147 */ 1148#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420 1149/* falcona0=net_func_bar2 */ 1150#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192 1151#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4 1152/* 1153 * FR_AB_TIMER_COMMAND_REGP123(128bit): 1154 * Timer Command Registers 1155 */ 1156#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420 1157/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1158#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192 1159#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072 1160/* 1161 * FR_AA_TIMER_COMMAND_REGP0(128bit): 1162 * Timer Command Registers 1163 */ 1164#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420 1165/* falcona0=char_func_bar0 */ 1166#define FR_AA_TIMER_COMMAND_REGP0_STEP 8192 1167#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020 1168 1169#define FRF_CZ_TC_TIMER_MODE_LBN 14 1170#define FRF_CZ_TC_TIMER_MODE_WIDTH 2 1171#define FRF_AB_TC_TIMER_MODE_LBN 12 1172#define FRF_AB_TC_TIMER_MODE_WIDTH 2 1173#define FRF_CZ_TC_TIMER_VAL_LBN 0 1174#define FRF_CZ_TC_TIMER_VAL_WIDTH 14 1175#define FRF_AB_TC_TIMER_VAL_LBN 0 1176#define FRF_AB_TC_TIMER_VAL_WIDTH 12 1177 1178 1179/* 1180 * FR_AZ_DRV_EV_REG(128bit): 1181 * Driver generated event register 1182 */ 1183#define FR_AZ_DRV_EV_REG_OFST 0x00000440 1184/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1185 1186#define FRF_AZ_DRV_EV_QID_LBN 64 1187#define FRF_AZ_DRV_EV_QID_WIDTH 12 1188#define FRF_AZ_DRV_EV_DATA_LBN 0 1189#define FRF_AZ_DRV_EV_DATA_WIDTH 64 1190#define FRF_AZ_DRV_EV_DATA_DW0_LBN 0 1191#define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32 1192#define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 1193#define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 1194 1195 1196/* 1197 * FR_AZ_EVQ_CTL_REG(128bit): 1198 * Event queue control register 1199 */ 1200#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450 1201/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1202 1203#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 1204#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 1205#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 1206#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 1207#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 1208#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 1209#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 1210#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 1211#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 1212#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 1213 1214 1215/* 1216 * FR_AZ_EVQ_CNT1_REG(128bit): 1217 * Event counter 1 register 1218 */ 1219#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460 1220/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1221 1222#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 1223#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 1224#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 1225#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 1226#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 1227#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 1228#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 1229#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 1230#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 1231#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 1232#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 1233#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 1234#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 1235#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 1236 1237 1238/* 1239 * FR_AZ_EVQ_CNT2_REG(128bit): 1240 * Event counter 2 register 1241 */ 1242#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470 1243/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1244 1245#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 1246#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 1247#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 1248#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 1249#define FRF_AZ_EVQ_RDY_CNT_LBN 80 1250#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 1251#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 1252#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 1253#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 1254#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 1255#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 1256#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 1257#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 1258#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 1259 1260 1261/* 1262 * FR_CZ_USR_EV_REG(32bit): 1263 * Event mailbox register 1264 */ 1265#define FR_CZ_USR_EV_REG_OFST 0x00000540 1266/* sienaa0=net_func_bar2 */ 1267#define FR_CZ_USR_EV_REG_STEP 8192 1268#define FR_CZ_USR_EV_REG_ROWS 1024 1269 1270#define FRF_CZ_USR_EV_DATA_LBN 0 1271#define FRF_CZ_USR_EV_DATA_WIDTH 32 1272 1273 1274/* 1275 * FR_AZ_BUF_TBL_CFG_REG(128bit): 1276 * Buffer table configuration register 1277 */ 1278#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600 1279/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1280 1281#define FRF_AZ_BUF_TBL_MODE_LBN 3 1282#define FRF_AZ_BUF_TBL_MODE_WIDTH 1 1283 1284 1285/* 1286 * FR_AZ_SRM_RX_DC_CFG_REG(128bit): 1287 * SRAM receive descriptor cache configuration register 1288 */ 1289#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610 1290/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1291 1292#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 1293#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 1294#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 1295#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 1296 1297 1298/* 1299 * FR_AZ_SRM_TX_DC_CFG_REG(128bit): 1300 * SRAM transmit descriptor cache configuration register 1301 */ 1302#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620 1303/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1304 1305#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 1306#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 1307 1308 1309/* 1310 * FR_AZ_SRM_CFG_REG(128bit): 1311 * SRAM configuration register 1312 */ 1313#define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380 1314/* falcona0,falconb0=eeprom_flash */ 1315/* 1316 * FR_AZ_SRM_CFG_REG(128bit): 1317 * SRAM configuration register 1318 */ 1319#define FR_AZ_SRM_CFG_REG_OFST 0x00000630 1320/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1321 1322#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 1323#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 1324#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 1325#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 1326#define FRF_AZ_SRM_INIT_EN_LBN 3 1327#define FRF_AZ_SRM_INIT_EN_WIDTH 1 1328#define FRF_AZ_SRM_NUM_BANK_LBN 2 1329#define FRF_AZ_SRM_NUM_BANK_WIDTH 1 1330#define FRF_AZ_SRM_BANK_SIZE_LBN 0 1331#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 1332 1333 1334/* 1335 * FR_AZ_BUF_TBL_UPD_REG(128bit): 1336 * Buffer table update register 1337 */ 1338#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650 1339/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1340 1341#define FRF_AZ_BUF_UPD_CMD_LBN 63 1342#define FRF_AZ_BUF_UPD_CMD_WIDTH 1 1343#define FRF_AZ_BUF_CLR_CMD_LBN 62 1344#define FRF_AZ_BUF_CLR_CMD_WIDTH 1 1345#define FRF_AZ_BUF_CLR_END_ID_LBN 32 1346#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 1347#define FRF_AZ_BUF_CLR_START_ID_LBN 0 1348#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 1349 1350 1351/* 1352 * FR_AZ_SRM_UPD_EVQ_REG(128bit): 1353 * Buffer table update register 1354 */ 1355#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660 1356/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1357 1358#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 1359#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 1360 1361 1362/* 1363 * FR_AZ_SRAM_PARITY_REG(128bit): 1364 * SRAM parity register. 1365 */ 1366#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670 1367/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1368 1369#define FRF_CZ_BYPASS_ECC_LBN 3 1370#define FRF_CZ_BYPASS_ECC_WIDTH 1 1371#define FRF_CZ_SEC_INT_LBN 2 1372#define FRF_CZ_SEC_INT_WIDTH 1 1373#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 1374#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 1375#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 1376#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 1377#define FRF_AB_FORCE_SRAM_PERR_LBN 0 1378#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 1379 1380 1381/* 1382 * FR_AZ_RX_CFG_REG(128bit): 1383 * Receive configuration register 1384 */ 1385#define FR_AZ_RX_CFG_REG_OFST 0x00000800 1386/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1387 1388#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 1389#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 1390#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 1391#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 1392#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 1393#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 1394#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 1395#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 1396#define FRF_BZ_RX_TCP_SUP_LBN 48 1397#define FRF_BZ_RX_TCP_SUP_WIDTH 1 1398#define FRF_BZ_RX_INGR_EN_LBN 47 1399#define FRF_BZ_RX_INGR_EN_WIDTH 1 1400#define FRF_BZ_RX_IP_HASH_LBN 46 1401#define FRF_BZ_RX_IP_HASH_WIDTH 1 1402#define FRF_BZ_RX_HASH_ALG_LBN 45 1403#define FRF_BZ_RX_HASH_ALG_WIDTH 1 1404#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 1405#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 1406#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 1407#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 1408#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 1409#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 1410#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 1411#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 1412#define FRF_BZ_RX_OWNERR_CTL_LBN 38 1413#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 1414#define FRF_BZ_RX_XON_TX_TH_LBN 33 1415#define FRF_BZ_RX_XON_TX_TH_WIDTH 5 1416#define FRF_AA_RX_DESC_PUSH_EN_LBN 35 1417#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 1418#define FRF_AA_RX_RDW_PATCH_EN_LBN 34 1419#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 1420#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 1421#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 1422#define FRF_BZ_RX_XOFF_TX_TH_LBN 28 1423#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 1424#define FRF_AA_RX_OWNERR_CTL_LBN 30 1425#define FRF_AA_RX_OWNERR_CTL_WIDTH 1 1426#define FRF_AA_RX_XON_TX_TH_LBN 25 1427#define FRF_AA_RX_XON_TX_TH_WIDTH 5 1428#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 1429#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 1430#define FRF_AA_RX_XOFF_TX_TH_LBN 20 1431#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 1432#define FRF_AA_RX_USR_BUF_SIZE_LBN 11 1433#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 1434#define FRF_BZ_RX_XON_MAC_TH_LBN 10 1435#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 1436#define FRF_AA_RX_XON_MAC_TH_LBN 6 1437#define FRF_AA_RX_XON_MAC_TH_WIDTH 5 1438#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 1439#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 1440#define FRF_AA_RX_XOFF_MAC_TH_LBN 1 1441#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 1442#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 1443#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 1444 1445 1446/* 1447 * FR_AZ_RX_FILTER_CTL_REG(128bit): 1448 * Receive filter control registers 1449 */ 1450#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810 1451/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1452 1453#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 1454#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 1455#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 1456#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 1457#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 1458#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 1459#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 1460#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 1461#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 1462#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 1463#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 1464#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1465#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 1466#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1467#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 1468#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 1469#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 1470#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1471#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 1472#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1473#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 1474#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 1475#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32 1476#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 1477#define FRF_AZ_NUM_KER_LBN 24 1478#define FRF_AZ_NUM_KER_WIDTH 2 1479#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16 1480#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 1481#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8 1482#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 1483#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 1484#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 1485 1486 1487/* 1488 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): 1489 * Receive flush descriptor queue register 1490 */ 1491#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820 1492/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1493 1494#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 1495#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 1496#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 1497#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 1498 1499 1500/* 1501 * FR_BZ_RX_DESC_UPD_REGP0(128bit): 1502 * Receive descriptor update register. 1503 */ 1504#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830 1505/* falconb0,sienaa0=net_func_bar2 */ 1506#define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192 1507#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024 1508/* 1509 * FR_AA_RX_DESC_UPD_REG_KER(128bit): 1510 * Receive descriptor update register. 1511 */ 1512#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830 1513/* falcona0=net_func_bar2 */ 1514#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192 1515#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4 1516/* 1517 * FR_AB_RX_DESC_UPD_REGP123(128bit): 1518 * Receive descriptor update register. 1519 */ 1520#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830 1521/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1522#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192 1523#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072 1524/* 1525 * FR_AA_RX_DESC_UPD_REGP0(128bit): 1526 * Receive descriptor update register. 1527 */ 1528#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830 1529/* falcona0=char_func_bar0 */ 1530#define FR_AA_RX_DESC_UPD_REGP0_STEP 8192 1531#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020 1532 1533#define FRF_AZ_RX_DESC_WPTR_LBN 96 1534#define FRF_AZ_RX_DESC_WPTR_WIDTH 12 1535#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 1536#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 1537#define FRF_AZ_RX_DESC_LBN 0 1538#define FRF_AZ_RX_DESC_WIDTH 64 1539#define FRF_AZ_RX_DESC_DW0_LBN 0 1540#define FRF_AZ_RX_DESC_DW0_WIDTH 32 1541#define FRF_AZ_RX_DESC_DW1_LBN 32 1542#define FRF_AZ_RX_DESC_DW1_WIDTH 32 1543 1544 1545/* 1546 * FR_AZ_RX_DC_CFG_REG(128bit): 1547 * Receive descriptor cache configuration register 1548 */ 1549#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840 1550/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1551 1552#define FRF_AZ_RX_MAX_PF_LBN 2 1553#define FRF_AZ_RX_MAX_PF_WIDTH 2 1554#define FRF_AZ_RX_DC_SIZE_LBN 0 1555#define FRF_AZ_RX_DC_SIZE_WIDTH 2 1556#define FFE_AZ_RX_DC_SIZE_64 3 1557#define FFE_AZ_RX_DC_SIZE_32 2 1558#define FFE_AZ_RX_DC_SIZE_16 1 1559#define FFE_AZ_RX_DC_SIZE_8 0 1560 1561 1562/* 1563 * FR_AZ_RX_DC_PF_WM_REG(128bit): 1564 * Receive descriptor cache pre-fetch watermark register 1565 */ 1566#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850 1567/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1568 1569#define FRF_AZ_RX_DC_PF_HWM_LBN 6 1570#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 1571#define FRF_AZ_RX_DC_PF_LWM_LBN 0 1572#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 1573 1574 1575/* 1576 * FR_BZ_RX_RSS_TKEY_REG(128bit): 1577 * RSS Toeplitz hash key 1578 */ 1579#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860 1580/* falconb0,sienaa0=net_func_bar2 */ 1581 1582#define FRF_BZ_RX_RSS_TKEY_LBN 96 1583#define FRF_BZ_RX_RSS_TKEY_WIDTH 32 1584#define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96 1585#define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32 1586#define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64 1587#define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32 1588#define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32 1589#define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32 1590#define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 1591#define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 1592 1593 1594/* 1595 * FR_AZ_RX_NODESC_DROP_REG(128bit): 1596 * Receive dropped packet counter register 1597 */ 1598#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880 1599/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1600 1601#define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 1602#define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 1603 1604 1605/* 1606 * FR_AZ_RX_SELF_RST_REG(128bit): 1607 * Receive self reset register 1608 */ 1609#define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890 1610/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1611 1612#define FRF_AZ_RX_ISCSI_DIS_LBN 17 1613#define FRF_AZ_RX_ISCSI_DIS_WIDTH 1 1614#define FRF_AB_RX_SW_RST_REG_LBN 16 1615#define FRF_AB_RX_SW_RST_REG_WIDTH 1 1616#define FRF_AB_RX_SELF_RST_EN_LBN 8 1617#define FRF_AB_RX_SELF_RST_EN_WIDTH 1 1618#define FRF_AZ_RX_MAX_PF_LAT_LBN 4 1619#define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4 1620#define FRF_AZ_RX_MAX_LU_LAT_LBN 0 1621#define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 1622 1623 1624/* 1625 * FR_AZ_RX_DEBUG_REG(128bit): 1626 * undocumented register 1627 */ 1628#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0 1629/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1630 1631#define FRF_AZ_RX_DEBUG_LBN 0 1632#define FRF_AZ_RX_DEBUG_WIDTH 64 1633#define FRF_AZ_RX_DEBUG_DW0_LBN 0 1634#define FRF_AZ_RX_DEBUG_DW0_WIDTH 32 1635#define FRF_AZ_RX_DEBUG_DW1_LBN 32 1636#define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 1637 1638 1639/* 1640 * FR_AZ_RX_PUSH_DROP_REG(128bit): 1641 * Receive descriptor push dropped counter register 1642 */ 1643#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0 1644/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1645 1646#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 1647#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 1648 1649 1650/* 1651 * FR_CZ_RX_RSS_IPV6_REG1(128bit): 1652 * IPv6 RSS Toeplitz hash key low bytes 1653 */ 1654#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0 1655/* sienaa0=net_func_bar2 */ 1656 1657#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 1658#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 1659#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0 1660#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32 1661#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32 1662#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32 1663#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64 1664#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32 1665#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 1666#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 1667 1668 1669/* 1670 * FR_CZ_RX_RSS_IPV6_REG2(128bit): 1671 * IPv6 RSS Toeplitz hash key middle bytes 1672 */ 1673#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0 1674/* sienaa0=net_func_bar2 */ 1675 1676#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 1677#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 1678#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0 1679#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32 1680#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32 1681#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32 1682#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64 1683#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32 1684#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 1685#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 1686 1687 1688/* 1689 * FR_CZ_RX_RSS_IPV6_REG3(128bit): 1690 * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings 1691 */ 1692#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0 1693/* sienaa0=net_func_bar2 */ 1694 1695#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 1696#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 1697#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 1698#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 1699#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 1700#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 1701#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 1702#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 1703#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0 1704#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32 1705#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 1706#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 1707 1708 1709/* 1710 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): 1711 * Transmit flush descriptor queue register 1712 */ 1713#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00 1714/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1715 1716#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 1717#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 1718#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 1719#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 1720 1721 1722/* 1723 * FR_BZ_TX_DESC_UPD_REGP0(128bit): 1724 * Transmit descriptor update register. 1725 */ 1726#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10 1727/* falconb0,sienaa0=net_func_bar2 */ 1728#define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192 1729#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024 1730/* 1731 * FR_AA_TX_DESC_UPD_REG_KER(128bit): 1732 * Transmit descriptor update register. 1733 */ 1734#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10 1735/* falcona0=net_func_bar2 */ 1736#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192 1737#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8 1738/* 1739 * FR_AB_TX_DESC_UPD_REGP123(128bit): 1740 * Transmit descriptor update register. 1741 */ 1742#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10 1743/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1744#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192 1745#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072 1746/* 1747 * FR_AA_TX_DESC_UPD_REGP0(128bit): 1748 * Transmit descriptor update register. 1749 */ 1750#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10 1751/* falcona0=char_func_bar0 */ 1752#define FR_AA_TX_DESC_UPD_REGP0_STEP 8192 1753#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020 1754 1755#define FRF_AZ_TX_DESC_WPTR_LBN 96 1756#define FRF_AZ_TX_DESC_WPTR_WIDTH 12 1757#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 1758#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 1759#define FRF_AZ_TX_DESC_LBN 0 1760#define FRF_AZ_TX_DESC_WIDTH 95 1761#define FRF_AZ_TX_DESC_DW0_LBN 0 1762#define FRF_AZ_TX_DESC_DW0_WIDTH 32 1763#define FRF_AZ_TX_DESC_DW1_LBN 32 1764#define FRF_AZ_TX_DESC_DW1_WIDTH 32 1765#define FRF_AZ_TX_DESC_DW2_LBN 64 1766#define FRF_AZ_TX_DESC_DW2_WIDTH 31 1767 1768 1769/* 1770 * FR_AZ_TX_DC_CFG_REG(128bit): 1771 * Transmit descriptor cache configuration register 1772 */ 1773#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20 1774/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1775 1776#define FRF_AZ_TX_DC_SIZE_LBN 0 1777#define FRF_AZ_TX_DC_SIZE_WIDTH 2 1778#define FFE_AZ_TX_DC_SIZE_32 2 1779#define FFE_AZ_TX_DC_SIZE_16 1 1780#define FFE_AZ_TX_DC_SIZE_8 0 1781 1782 1783/* 1784 * FR_AA_TX_CHKSM_CFG_REG(128bit): 1785 * Transmit checksum configuration register 1786 */ 1787#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30 1788/* falcona0=net_func_bar2,falcona0=char_func_bar0 */ 1789 1790#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 1791#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 1792#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 1793#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 1794#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 1795#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 1796#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 1797#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 1798 1799 1800/* 1801 * FR_AZ_TX_CFG_REG(128bit): 1802 * Transmit configuration register 1803 */ 1804#define FR_AZ_TX_CFG_REG_OFST 0x00000a50 1805/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1806 1807#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 1808#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 1809#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 1810#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 1811#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 1812#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1813#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 1814#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1815#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 1816#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1817#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 1818#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1819#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 1820#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1821#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 1822#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1823#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 1824#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 1825#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 1826#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 1827#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 1828#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 1829#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 1830#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 1831#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 1832#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 1833#define FRF_AZ_TX_P1_PRI_EN_LBN 4 1834#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 1835#define FRF_AZ_TX_OWNERR_CTL_LBN 2 1836#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 1837#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 1838#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 1839#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 1840#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 1841 1842 1843/* 1844 * FR_AZ_TX_PUSH_DROP_REG(128bit): 1845 * Transmit push dropped register 1846 */ 1847#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60 1848/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1849 1850#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 1851#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 1852 1853 1854/* 1855 * FR_AZ_TX_RESERVED_REG(128bit): 1856 * Transmit configuration register 1857 */ 1858#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80 1859/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1860 1861#define FRF_AZ_TX_EVT_CNT_LBN 121 1862#define FRF_AZ_TX_EVT_CNT_WIDTH 7 1863#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 1864#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 1865#define FRF_AZ_TX_RD_COMP_TMR_LBN 96 1866#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 1867#define FRF_AZ_TX_PUSH_EN_LBN 89 1868#define FRF_AZ_TX_PUSH_EN_WIDTH 1 1869#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 1870#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 1871#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 1872#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 1873#define FRF_AZ_TX_DMAR_ST_P0_LBN 81 1874#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 1875#define FRF_AZ_TX_DMAQ_ST_LBN 78 1876#define FRF_AZ_TX_DMAQ_ST_WIDTH 1 1877#define FRF_AZ_TX_RX_SPACER_LBN 64 1878#define FRF_AZ_TX_RX_SPACER_WIDTH 8 1879#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 1880#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 1881#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 1882#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 1883#define FRF_AZ_TX_PS_EVT_DIS_LBN 58 1884#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 1885#define FRF_AZ_TX_RX_SPACER_EN_LBN 57 1886#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 1887#define FRF_AZ_TX_XP_TIMER_LBN 52 1888#define FRF_AZ_TX_XP_TIMER_WIDTH 5 1889#define FRF_AZ_TX_PREF_SPACER_LBN 44 1890#define FRF_AZ_TX_PREF_SPACER_WIDTH 8 1891#define FRF_AZ_TX_PREF_WD_TMR_LBN 22 1892#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 1893#define FRF_AZ_TX_ONLY1TAG_LBN 21 1894#define FRF_AZ_TX_ONLY1TAG_WIDTH 1 1895#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 1896#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 1897#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 1898#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 1899#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 1900#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 1901#define FRF_AA_TX_DMA_FF_THR_LBN 16 1902#define FRF_AA_TX_DMA_FF_THR_WIDTH 1 1903#define FRF_AZ_TX_DMA_SPACER_LBN 8 1904#define FRF_AZ_TX_DMA_SPACER_WIDTH 8 1905#define FRF_AA_TX_TCP_DIS_LBN 7 1906#define FRF_AA_TX_TCP_DIS_WIDTH 1 1907#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 1908#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 1909#define FRF_AA_TX_IP_DIS_LBN 6 1910#define FRF_AA_TX_IP_DIS_WIDTH 1 1911#define FRF_AZ_TX_MAX_CPL_LBN 2 1912#define FRF_AZ_TX_MAX_CPL_WIDTH 2 1913#define FFE_AZ_TX_MAX_CPL_16 3 1914#define FFE_AZ_TX_MAX_CPL_8 2 1915#define FFE_AZ_TX_MAX_CPL_4 1 1916#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 1917#define FRF_AZ_TX_MAX_PREF_LBN 0 1918#define FRF_AZ_TX_MAX_PREF_WIDTH 2 1919#define FFE_AZ_TX_MAX_PREF_32 3 1920#define FFE_AZ_TX_MAX_PREF_16 2 1921#define FFE_AZ_TX_MAX_PREF_8 1 1922#define FFE_AZ_TX_MAX_PREF_OFF 0 1923 1924 1925/* 1926 * FR_BZ_TX_PACE_REG(128bit): 1927 * Transmit pace control register 1928 */ 1929#define FR_BZ_TX_PACE_REG_OFST 0x00000a90 1930/* falconb0,sienaa0=net_func_bar2 */ 1931/* 1932 * FR_AA_TX_PACE_REG(128bit): 1933 * Transmit pace control register 1934 */ 1935#define FR_AA_TX_PACE_REG_OFST 0x00f80000 1936/* falcona0=char_func_bar0 */ 1937 1938#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19 1939#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10 1940#define FRF_AZ_TX_PACE_SB_AF_LBN 9 1941#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10 1942#define FRF_AZ_TX_PACE_FB_BASE_LBN 5 1943#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4 1944#define FRF_AZ_TX_PACE_BIN_TH_LBN 0 1945#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 1946 1947 1948/* 1949 * FR_AZ_TX_PACE_DROP_QID_REG(128bit): 1950 * PACE Drop QID Counter 1951 */ 1952#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0 1953/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1954 1955#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 1956#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 1957 1958 1959/* 1960 * FR_AB_TX_VLAN_REG(128bit): 1961 * Transmit VLAN tag register 1962 */ 1963#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0 1964/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1965 1966#define FRF_AB_TX_VLAN_EN_LBN 127 1967#define FRF_AB_TX_VLAN_EN_WIDTH 1 1968#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125 1969#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1 1970#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124 1971#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1 1972#define FRF_AB_TX_VLAN7_LBN 112 1973#define FRF_AB_TX_VLAN7_WIDTH 12 1974#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109 1975#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1 1976#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108 1977#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1 1978#define FRF_AB_TX_VLAN6_LBN 96 1979#define FRF_AB_TX_VLAN6_WIDTH 12 1980#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93 1981#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1 1982#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92 1983#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1 1984#define FRF_AB_TX_VLAN5_LBN 80 1985#define FRF_AB_TX_VLAN5_WIDTH 12 1986#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77 1987#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1 1988#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76 1989#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1 1990#define FRF_AB_TX_VLAN4_LBN 64 1991#define FRF_AB_TX_VLAN4_WIDTH 12 1992#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61 1993#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1 1994#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60 1995#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1 1996#define FRF_AB_TX_VLAN3_LBN 48 1997#define FRF_AB_TX_VLAN3_WIDTH 12 1998#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45 1999#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1 2000#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44 2001#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1 2002#define FRF_AB_TX_VLAN2_LBN 32 2003#define FRF_AB_TX_VLAN2_WIDTH 12 2004#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29 2005#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1 2006#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28 2007#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1 2008#define FRF_AB_TX_VLAN1_LBN 16 2009#define FRF_AB_TX_VLAN1_WIDTH 12 2010#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13 2011#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1 2012#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12 2013#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1 2014#define FRF_AB_TX_VLAN0_LBN 0 2015#define FRF_AB_TX_VLAN0_WIDTH 12 2016 2017 2018/* 2019 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): 2020 * Transmit filter control register 2021 */ 2022#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0 2023/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 2024 2025#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64 2026#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1 2027#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62 2028#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1 2029#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60 2030#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1 2031#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58 2032#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1 2033#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56 2034#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1 2035#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54 2036#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1 2037#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52 2038#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1 2039#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50 2040#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1 2041#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48 2042#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1 2043#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46 2044#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1 2045#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44 2046#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1 2047#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42 2048#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1 2049#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40 2050#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1 2051#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38 2052#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1 2053#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36 2054#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1 2055#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34 2056#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1 2057#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32 2058#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1 2059#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30 2060#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1 2061#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28 2062#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1 2063#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26 2064#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1 2065#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24 2066#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1 2067#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22 2068#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1 2069#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20 2070#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1 2071#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18 2072#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1 2073#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16 2074#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1 2075#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14 2076#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1 2077#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12 2078#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1 2079#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10 2080#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1 2081#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8 2082#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1 2083#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6 2084#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1 2085#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4 2086#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1 2087#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2 2088#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1 2089#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 2090#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 2091 2092 2093/* 2094 * FR_AB_TX_IPFIL_TBL(128bit): 2095 * Transmit IP source address filter table 2096 */ 2097#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00 2098/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2099#define FR_AB_TX_IPFIL_TBL_STEP 16 2100#define FR_AB_TX_IPFIL_TBL_ROWS 16 2101 2102#define FRF_AB_TX_IPFIL_MASK_1_LBN 96 2103#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32 2104#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64 2105#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32 2106#define FRF_AB_TX_IPFIL_MASK_0_LBN 32 2107#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32 2108#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 2109#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 2110 2111 2112/* 2113 * FR_AB_MD_TXD_REG(128bit): 2114 * PHY management transmit data register 2115 */ 2116#define FR_AB_MD_TXD_REG_OFST 0x00000c00 2117/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2118 2119#define FRF_AB_MD_TXD_LBN 0 2120#define FRF_AB_MD_TXD_WIDTH 16 2121 2122 2123/* 2124 * FR_AB_MD_RXD_REG(128bit): 2125 * PHY management receive data register 2126 */ 2127#define FR_AB_MD_RXD_REG_OFST 0x00000c10 2128/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2129 2130#define FRF_AB_MD_RXD_LBN 0 2131#define FRF_AB_MD_RXD_WIDTH 16 2132 2133 2134/* 2135 * FR_AB_MD_CS_REG(128bit): 2136 * PHY management configuration & status register 2137 */ 2138#define FR_AB_MD_CS_REG_OFST 0x00000c20 2139/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2140 2141#define FRF_AB_MD_RD_EN_LBN 15 2142#define FRF_AB_MD_RD_EN_WIDTH 1 2143#define FRF_AB_MD_WR_EN_LBN 14 2144#define FRF_AB_MD_WR_EN_WIDTH 1 2145#define FRF_AB_MD_ADDR_CMD_LBN 13 2146#define FRF_AB_MD_ADDR_CMD_WIDTH 1 2147#define FRF_AB_MD_PT_LBN 7 2148#define FRF_AB_MD_PT_WIDTH 3 2149#define FRF_AB_MD_PL_LBN 6 2150#define FRF_AB_MD_PL_WIDTH 1 2151#define FRF_AB_MD_INT_CLR_LBN 5 2152#define FRF_AB_MD_INT_CLR_WIDTH 1 2153#define FRF_AB_MD_GC_LBN 4 2154#define FRF_AB_MD_GC_WIDTH 1 2155#define FRF_AB_MD_PRSP_LBN 3 2156#define FRF_AB_MD_PRSP_WIDTH 1 2157#define FRF_AB_MD_RIC_LBN 2 2158#define FRF_AB_MD_RIC_WIDTH 1 2159#define FRF_AB_MD_RDC_LBN 1 2160#define FRF_AB_MD_RDC_WIDTH 1 2161#define FRF_AB_MD_WRC_LBN 0 2162#define FRF_AB_MD_WRC_WIDTH 1 2163 2164 2165/* 2166 * FR_AB_MD_PHY_ADR_REG(128bit): 2167 * PHY management PHY address register 2168 */ 2169#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30 2170/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2171 2172#define FRF_AB_MD_PHY_ADR_LBN 0 2173#define FRF_AB_MD_PHY_ADR_WIDTH 16 2174 2175 2176/* 2177 * FR_AB_MD_ID_REG(128bit): 2178 * PHY management ID register 2179 */ 2180#define FR_AB_MD_ID_REG_OFST 0x00000c40 2181/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2182 2183#define FRF_AB_MD_PRT_ADR_LBN 11 2184#define FRF_AB_MD_PRT_ADR_WIDTH 5 2185#define FRF_AB_MD_DEV_ADR_LBN 6 2186#define FRF_AB_MD_DEV_ADR_WIDTH 5 2187 2188 2189/* 2190 * FR_AB_MD_STAT_REG(128bit): 2191 * PHY management status & mask register 2192 */ 2193#define FR_AB_MD_STAT_REG_OFST 0x00000c50 2194/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2195 2196#define FRF_AB_MD_PINT_LBN 4 2197#define FRF_AB_MD_PINT_WIDTH 1 2198#define FRF_AB_MD_DONE_LBN 3 2199#define FRF_AB_MD_DONE_WIDTH 1 2200#define FRF_AB_MD_BSERR_LBN 2 2201#define FRF_AB_MD_BSERR_WIDTH 1 2202#define FRF_AB_MD_LNFL_LBN 1 2203#define FRF_AB_MD_LNFL_WIDTH 1 2204#define FRF_AB_MD_BSY_LBN 0 2205#define FRF_AB_MD_BSY_WIDTH 1 2206 2207 2208/* 2209 * FR_AB_MAC_STAT_DMA_REG(128bit): 2210 * Port MAC statistical counter DMA register 2211 */ 2212#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60 2213/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2214 2215#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 2216#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 2217#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 2218#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 2219#define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0 2220#define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32 2221#define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 2222#define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 2223 2224 2225/* 2226 * FR_AB_MAC_CTRL_REG(128bit): 2227 * Port MAC control register 2228 */ 2229#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80 2230/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2231 2232#define FRF_AB_MAC_XOFF_VAL_LBN 16 2233#define FRF_AB_MAC_XOFF_VAL_WIDTH 16 2234#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 2235#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 2236#define FRF_AB_MAC_XG_DISTXCRC_LBN 5 2237#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 2238#define FRF_AB_MAC_BCAD_ACPT_LBN 4 2239#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 2240#define FRF_AB_MAC_UC_PROM_LBN 3 2241#define FRF_AB_MAC_UC_PROM_WIDTH 1 2242#define FRF_AB_MAC_LINK_STATUS_LBN 2 2243#define FRF_AB_MAC_LINK_STATUS_WIDTH 1 2244#define FRF_AB_MAC_SPEED_LBN 0 2245#define FRF_AB_MAC_SPEED_WIDTH 2 2246#define FRF_AB_MAC_SPEED_10M 0 2247#define FRF_AB_MAC_SPEED_100M 1 2248#define FRF_AB_MAC_SPEED_1G 2 2249#define FRF_AB_MAC_SPEED_10G 3 2250 2251/* 2252 * FR_BB_GEN_MODE_REG(128bit): 2253 * General Purpose mode register (external interrupt mask) 2254 */ 2255#define FR_BB_GEN_MODE_REG_OFST 0x00000c90 2256/* falconb0=net_func_bar2 */ 2257 2258#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 2259#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 2260#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 2261#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 2262#define FRF_BB_XFP_PHY_INT_MASK_LBN 1 2263#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 2264#define FRF_BB_XG_PHY_INT_MASK_LBN 0 2265#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 2266 2267 2268/* 2269 * FR_AB_MAC_MC_HASH_REG0(128bit): 2270 * Multicast address hash table 2271 */ 2272#define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0 2273/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2274 2275#define FRF_AB_MAC_MCAST_HASH0_LBN 0 2276#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 2277#define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0 2278#define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32 2279#define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32 2280#define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32 2281#define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64 2282#define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32 2283#define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 2284#define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 2285 2286 2287/* 2288 * FR_AB_MAC_MC_HASH_REG1(128bit): 2289 * Multicast address hash table 2290 */ 2291#define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0 2292/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2293 2294#define FRF_AB_MAC_MCAST_HASH1_LBN 0 2295#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 2296#define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0 2297#define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32 2298#define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32 2299#define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32 2300#define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64 2301#define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32 2302#define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 2303#define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 2304 2305 2306/* 2307 * FR_AB_GM_CFG1_REG(32bit): 2308 * GMAC configuration register 1 2309 */ 2310#define FR_AB_GM_CFG1_REG_OFST 0x00000e00 2311/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2312 2313#define FRF_AB_GM_SW_RST_LBN 31 2314#define FRF_AB_GM_SW_RST_WIDTH 1 2315#define FRF_AB_GM_SIM_RST_LBN 30 2316#define FRF_AB_GM_SIM_RST_WIDTH 1 2317#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 2318#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 2319#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 2320#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 2321#define FRF_AB_GM_RST_RX_FUNC_LBN 17 2322#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 2323#define FRF_AB_GM_RST_TX_FUNC_LBN 16 2324#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 2325#define FRF_AB_GM_LOOP_LBN 8 2326#define FRF_AB_GM_LOOP_WIDTH 1 2327#define FRF_AB_GM_RX_FC_EN_LBN 5 2328#define FRF_AB_GM_RX_FC_EN_WIDTH 1 2329#define FRF_AB_GM_TX_FC_EN_LBN 4 2330#define FRF_AB_GM_TX_FC_EN_WIDTH 1 2331#define FRF_AB_GM_SYNC_RXEN_LBN 3 2332#define FRF_AB_GM_SYNC_RXEN_WIDTH 1 2333#define FRF_AB_GM_RX_EN_LBN 2 2334#define FRF_AB_GM_RX_EN_WIDTH 1 2335#define FRF_AB_GM_SYNC_TXEN_LBN 1 2336#define FRF_AB_GM_SYNC_TXEN_WIDTH 1 2337#define FRF_AB_GM_TX_EN_LBN 0 2338#define FRF_AB_GM_TX_EN_WIDTH 1 2339 2340 2341/* 2342 * FR_AB_GM_CFG2_REG(32bit): 2343 * GMAC configuration register 2 2344 */ 2345#define FR_AB_GM_CFG2_REG_OFST 0x00000e10 2346/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2347 2348#define FRF_AB_GM_PAMBL_LEN_LBN 12 2349#define FRF_AB_GM_PAMBL_LEN_WIDTH 4 2350#define FRF_AB_GM_IF_MODE_LBN 8 2351#define FRF_AB_GM_IF_MODE_WIDTH 2 2352#define FRF_AB_GM_IF_MODE_BYTE_MODE 2 2353#define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1 2354#define FRF_AB_GM_HUGE_FRM_EN_LBN 5 2355#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 2356#define FRF_AB_GM_LEN_CHK_LBN 4 2357#define FRF_AB_GM_LEN_CHK_WIDTH 1 2358#define FRF_AB_GM_PAD_CRC_EN_LBN 2 2359#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 2360#define FRF_AB_GM_CRC_EN_LBN 1 2361#define FRF_AB_GM_CRC_EN_WIDTH 1 2362#define FRF_AB_GM_FD_LBN 0 2363#define FRF_AB_GM_FD_WIDTH 1 2364 2365 2366/* 2367 * FR_AB_GM_IPG_REG(32bit): 2368 * GMAC IPG register 2369 */ 2370#define FR_AB_GM_IPG_REG_OFST 0x00000e20 2371/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2372 2373#define FRF_AB_GM_NONB2B_IPG1_LBN 24 2374#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 2375#define FRF_AB_GM_NONB2B_IPG2_LBN 16 2376#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 2377#define FRF_AB_GM_MIN_IPG_ENF_LBN 8 2378#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 2379#define FRF_AB_GM_B2B_IPG_LBN 0 2380#define FRF_AB_GM_B2B_IPG_WIDTH 7 2381 2382 2383/* 2384 * FR_AB_GM_HD_REG(32bit): 2385 * GMAC half duplex register 2386 */ 2387#define FR_AB_GM_HD_REG_OFST 0x00000e30 2388/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2389 2390#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 2391#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 2392#define FRF_AB_GM_ALT_BOFF_EN_LBN 19 2393#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 2394#define FRF_AB_GM_BP_NO_BOFF_LBN 18 2395#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 2396#define FRF_AB_GM_DIS_BOFF_LBN 17 2397#define FRF_AB_GM_DIS_BOFF_WIDTH 1 2398#define FRF_AB_GM_EXDEF_TX_EN_LBN 16 2399#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 2400#define FRF_AB_GM_RTRY_LIMIT_LBN 12 2401#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 2402#define FRF_AB_GM_COL_WIN_LBN 0 2403#define FRF_AB_GM_COL_WIN_WIDTH 10 2404 2405 2406/* 2407 * FR_AB_GM_MAX_FLEN_REG(32bit): 2408 * GMAC maximum frame length register 2409 */ 2410#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40 2411/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2412 2413#define FRF_AB_GM_MAX_FLEN_LBN 0 2414#define FRF_AB_GM_MAX_FLEN_WIDTH 16 2415 2416 2417/* 2418 * FR_AB_GM_TEST_REG(32bit): 2419 * GMAC test register 2420 */ 2421#define FR_AB_GM_TEST_REG_OFST 0x00000e70 2422/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2423 2424#define FRF_AB_GM_MAX_BOFF_LBN 3 2425#define FRF_AB_GM_MAX_BOFF_WIDTH 1 2426#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 2427#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 2428#define FRF_AB_GM_TEST_PAUSE_LBN 1 2429#define FRF_AB_GM_TEST_PAUSE_WIDTH 1 2430#define FRF_AB_GM_SHORT_SLOT_LBN 0 2431#define FRF_AB_GM_SHORT_SLOT_WIDTH 1 2432 2433 2434/* 2435 * FR_AB_GM_ADR1_REG(32bit): 2436 * GMAC station address register 1 2437 */ 2438#define FR_AB_GM_ADR1_REG_OFST 0x00000f00 2439/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2440 2441#define FRF_AB_GM_ADR_B0_LBN 24 2442#define FRF_AB_GM_ADR_B0_WIDTH 8 2443#define FRF_AB_GM_ADR_B1_LBN 16 2444#define FRF_AB_GM_ADR_B1_WIDTH 8 2445#define FRF_AB_GM_ADR_B2_LBN 8 2446#define FRF_AB_GM_ADR_B2_WIDTH 8 2447#define FRF_AB_GM_ADR_B3_LBN 0 2448#define FRF_AB_GM_ADR_B3_WIDTH 8 2449 2450 2451/* 2452 * FR_AB_GM_ADR2_REG(32bit): 2453 * GMAC station address register 2 2454 */ 2455#define FR_AB_GM_ADR2_REG_OFST 0x00000f10 2456/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2457 2458#define FRF_AB_GM_ADR_B4_LBN 24 2459#define FRF_AB_GM_ADR_B4_WIDTH 8 2460#define FRF_AB_GM_ADR_B5_LBN 16 2461#define FRF_AB_GM_ADR_B5_WIDTH 8 2462 2463 2464/* 2465 * FR_AB_GMF_CFG0_REG(32bit): 2466 * GMAC FIFO configuration register 0 2467 */ 2468#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20 2469/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2470 2471#define FRF_AB_GMF_FTFENRPLY_LBN 20 2472#define FRF_AB_GMF_FTFENRPLY_WIDTH 1 2473#define FRF_AB_GMF_STFENRPLY_LBN 19 2474#define FRF_AB_GMF_STFENRPLY_WIDTH 1 2475#define FRF_AB_GMF_FRFENRPLY_LBN 18 2476#define FRF_AB_GMF_FRFENRPLY_WIDTH 1 2477#define FRF_AB_GMF_SRFENRPLY_LBN 17 2478#define FRF_AB_GMF_SRFENRPLY_WIDTH 1 2479#define FRF_AB_GMF_WTMENRPLY_LBN 16 2480#define FRF_AB_GMF_WTMENRPLY_WIDTH 1 2481#define FRF_AB_GMF_FTFENREQ_LBN 12 2482#define FRF_AB_GMF_FTFENREQ_WIDTH 1 2483#define FRF_AB_GMF_STFENREQ_LBN 11 2484#define FRF_AB_GMF_STFENREQ_WIDTH 1 2485#define FRF_AB_GMF_FRFENREQ_LBN 10 2486#define FRF_AB_GMF_FRFENREQ_WIDTH 1 2487#define FRF_AB_GMF_SRFENREQ_LBN 9 2488#define FRF_AB_GMF_SRFENREQ_WIDTH 1 2489#define FRF_AB_GMF_WTMENREQ_LBN 8 2490#define FRF_AB_GMF_WTMENREQ_WIDTH 1 2491#define FRF_AB_GMF_HSTRSTFT_LBN 4 2492#define FRF_AB_GMF_HSTRSTFT_WIDTH 1 2493#define FRF_AB_GMF_HSTRSTST_LBN 3 2494#define FRF_AB_GMF_HSTRSTST_WIDTH 1 2495#define FRF_AB_GMF_HSTRSTFR_LBN 2 2496#define FRF_AB_GMF_HSTRSTFR_WIDTH 1 2497#define FRF_AB_GMF_HSTRSTSR_LBN 1 2498#define FRF_AB_GMF_HSTRSTSR_WIDTH 1 2499#define FRF_AB_GMF_HSTRSTWT_LBN 0 2500#define FRF_AB_GMF_HSTRSTWT_WIDTH 1 2501 2502 2503/* 2504 * FR_AB_GMF_CFG1_REG(32bit): 2505 * GMAC FIFO configuration register 1 2506 */ 2507#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30 2508/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2509 2510#define FRF_AB_GMF_CFGFRTH_LBN 16 2511#define FRF_AB_GMF_CFGFRTH_WIDTH 5 2512#define FRF_AB_GMF_CFGXOFFRTX_LBN 0 2513#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 2514 2515 2516/* 2517 * FR_AB_GMF_CFG2_REG(32bit): 2518 * GMAC FIFO configuration register 2 2519 */ 2520#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40 2521/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2522 2523#define FRF_AB_GMF_CFGHWM_LBN 16 2524#define FRF_AB_GMF_CFGHWM_WIDTH 6 2525#define FRF_AB_GMF_CFGLWM_LBN 0 2526#define FRF_AB_GMF_CFGLWM_WIDTH 6 2527 2528 2529/* 2530 * FR_AB_GMF_CFG3_REG(32bit): 2531 * GMAC FIFO configuration register 3 2532 */ 2533#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50 2534/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2535 2536#define FRF_AB_GMF_CFGHWMFT_LBN 16 2537#define FRF_AB_GMF_CFGHWMFT_WIDTH 6 2538#define FRF_AB_GMF_CFGFTTH_LBN 0 2539#define FRF_AB_GMF_CFGFTTH_WIDTH 6 2540 2541 2542/* 2543 * FR_AB_GMF_CFG4_REG(32bit): 2544 * GMAC FIFO configuration register 4 2545 */ 2546#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60 2547/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2548 2549#define FRF_AB_GMF_HSTFLTRFRM_LBN 0 2550#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 2551 2552 2553/* 2554 * FR_AB_GMF_CFG5_REG(32bit): 2555 * GMAC FIFO configuration register 5 2556 */ 2557#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70 2558/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2559 2560#define FRF_AB_GMF_CFGHDPLX_LBN 22 2561#define FRF_AB_GMF_CFGHDPLX_WIDTH 1 2562#define FRF_AB_GMF_SRFULL_LBN 21 2563#define FRF_AB_GMF_SRFULL_WIDTH 1 2564#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 2565#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 2566#define FRF_AB_GMF_CFGBYTMODE_LBN 19 2567#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 2568#define FRF_AB_GMF_HSTDRPLT64_LBN 18 2569#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 2570#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 2571#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 2572 2573 2574/* 2575 * FR_BB_TX_SRC_MAC_TBL(128bit): 2576 * Transmit IP source address filter table 2577 */ 2578#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000 2579/* falconb0=net_func_bar2 */ 2580#define FR_BB_TX_SRC_MAC_TBL_STEP 16 2581#define FR_BB_TX_SRC_MAC_TBL_ROWS 16 2582 2583#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 2584#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 2585#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64 2586#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32 2587#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96 2588#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16 2589#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 2590#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 2591#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0 2592#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32 2593#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 2594#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 2595 2596 2597/* 2598 * FR_BB_TX_SRC_MAC_CTL_REG(128bit): 2599 * Transmit MAC source address filter control 2600 */ 2601#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100 2602/* falconb0=net_func_bar2 */ 2603 2604#define FRF_BB_TX_SRC_DROP_CTR_LBN 16 2605#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 2606#define FRF_BB_TX_SRC_FLTR_EN_LBN 15 2607#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 2608#define FRF_BB_TX_DROP_CTR_CLR_LBN 12 2609#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 2610#define FRF_BB_TX_MAC_QID_SEL_LBN 0 2611#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 2612 2613 2614/* 2615 * FR_AB_XM_ADR_LO_REG(128bit): 2616 * XGMAC address register low 2617 */ 2618#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200 2619/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2620 2621#define FRF_AB_XM_ADR_LO_LBN 0 2622#define FRF_AB_XM_ADR_LO_WIDTH 32 2623 2624 2625/* 2626 * FR_AB_XM_ADR_HI_REG(128bit): 2627 * XGMAC address register high 2628 */ 2629#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210 2630/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2631 2632#define FRF_AB_XM_ADR_HI_LBN 0 2633#define FRF_AB_XM_ADR_HI_WIDTH 16 2634 2635 2636/* 2637 * FR_AB_XM_GLB_CFG_REG(128bit): 2638 * XGMAC global configuration 2639 */ 2640#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220 2641/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2642 2643#define FRF_AB_XM_RMTFLT_GEN_LBN 17 2644#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 2645#define FRF_AB_XM_DEBUG_MODE_LBN 16 2646#define FRF_AB_XM_DEBUG_MODE_WIDTH 1 2647#define FRF_AB_XM_RX_STAT_EN_LBN 11 2648#define FRF_AB_XM_RX_STAT_EN_WIDTH 1 2649#define FRF_AB_XM_TX_STAT_EN_LBN 10 2650#define FRF_AB_XM_TX_STAT_EN_WIDTH 1 2651#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 2652#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 2653#define FRF_AB_XM_WAN_MODE_LBN 5 2654#define FRF_AB_XM_WAN_MODE_WIDTH 1 2655#define FRF_AB_XM_INTCLR_MODE_LBN 3 2656#define FRF_AB_XM_INTCLR_MODE_WIDTH 1 2657#define FRF_AB_XM_CORE_RST_LBN 0 2658#define FRF_AB_XM_CORE_RST_WIDTH 1 2659 2660 2661/* 2662 * FR_AB_XM_TX_CFG_REG(128bit): 2663 * XGMAC transmit configuration 2664 */ 2665#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230 2666/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2667 2668#define FRF_AB_XM_TX_PROG_LBN 24 2669#define FRF_AB_XM_TX_PROG_WIDTH 1 2670#define FRF_AB_XM_IPG_LBN 16 2671#define FRF_AB_XM_IPG_WIDTH 4 2672#define FRF_AB_XM_FCNTL_LBN 10 2673#define FRF_AB_XM_FCNTL_WIDTH 1 2674#define FRF_AB_XM_TXCRC_LBN 8 2675#define FRF_AB_XM_TXCRC_WIDTH 1 2676#define FRF_AB_XM_EDRC_LBN 6 2677#define FRF_AB_XM_EDRC_WIDTH 1 2678#define FRF_AB_XM_AUTO_PAD_LBN 5 2679#define FRF_AB_XM_AUTO_PAD_WIDTH 1 2680#define FRF_AB_XM_TX_PRMBL_LBN 2 2681#define FRF_AB_XM_TX_PRMBL_WIDTH 1 2682#define FRF_AB_XM_TXEN_LBN 1 2683#define FRF_AB_XM_TXEN_WIDTH 1 2684#define FRF_AB_XM_TX_RST_LBN 0 2685#define FRF_AB_XM_TX_RST_WIDTH 1 2686 2687 2688/* 2689 * FR_AB_XM_RX_CFG_REG(128bit): 2690 * XGMAC receive configuration 2691 */ 2692#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240 2693/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2694 2695#define FRF_AB_XM_PASS_LENERR_LBN 26 2696#define FRF_AB_XM_PASS_LENERR_WIDTH 1 2697#define FRF_AB_XM_PASS_CRC_ERR_LBN 25 2698#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 2699#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 2700#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 2701#define FRF_AB_XM_REJ_BCAST_LBN 20 2702#define FRF_AB_XM_REJ_BCAST_WIDTH 1 2703#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 2704#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 2705#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 2706#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 2707#define FRF_AB_XM_AUTO_DEPAD_LBN 8 2708#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 2709#define FRF_AB_XM_RXCRC_LBN 3 2710#define FRF_AB_XM_RXCRC_WIDTH 1 2711#define FRF_AB_XM_RX_PRMBL_LBN 2 2712#define FRF_AB_XM_RX_PRMBL_WIDTH 1 2713#define FRF_AB_XM_RXEN_LBN 1 2714#define FRF_AB_XM_RXEN_WIDTH 1 2715#define FRF_AB_XM_RX_RST_LBN 0 2716#define FRF_AB_XM_RX_RST_WIDTH 1 2717 2718 2719/* 2720 * FR_AB_XM_MGT_INT_MASK(128bit): 2721 * documentation to be written for sum_XM_MGT_INT_MASK 2722 */ 2723#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250 2724/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2725 2726#define FRF_AB_XM_MSK_STA_INTR_LBN 16 2727#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 2728#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 2729#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 2730#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 2731#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 2732#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 2733#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 2734#define FRF_AB_XM_MSK_RMTFLT_LBN 1 2735#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 2736#define FRF_AB_XM_MSK_LCLFLT_LBN 0 2737#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 2738 2739 2740/* 2741 * FR_AB_XM_FC_REG(128bit): 2742 * XGMAC flow control register 2743 */ 2744#define FR_AB_XM_FC_REG_OFST 0x00001270 2745/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2746 2747#define FRF_AB_XM_PAUSE_TIME_LBN 16 2748#define FRF_AB_XM_PAUSE_TIME_WIDTH 16 2749#define FRF_AB_XM_RX_MAC_STAT_LBN 11 2750#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 2751#define FRF_AB_XM_TX_MAC_STAT_LBN 10 2752#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 2753#define FRF_AB_XM_MCNTL_PASS_LBN 8 2754#define FRF_AB_XM_MCNTL_PASS_WIDTH 2 2755#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 2756#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 2757#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 2758#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 2759#define FRF_AB_XM_ZPAUSE_LBN 2 2760#define FRF_AB_XM_ZPAUSE_WIDTH 1 2761#define FRF_AB_XM_XMIT_PAUSE_LBN 1 2762#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 2763#define FRF_AB_XM_DIS_FCNTL_LBN 0 2764#define FRF_AB_XM_DIS_FCNTL_WIDTH 1 2765 2766 2767/* 2768 * FR_AB_XM_PAUSE_TIME_REG(128bit): 2769 * XGMAC pause time register 2770 */ 2771#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290 2772/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2773 2774#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 2775#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 2776#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 2777#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 2778 2779 2780/* 2781 * FR_AB_XM_TX_PARAM_REG(128bit): 2782 * XGMAC transmit parameter register 2783 */ 2784#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0 2785/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2786 2787#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 2788#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 2789#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 2790#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 2791#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 2792#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 2793#define FRF_AB_XM_PAD_CHAR_LBN 0 2794#define FRF_AB_XM_PAD_CHAR_WIDTH 8 2795 2796 2797/* 2798 * FR_AB_XM_RX_PARAM_REG(128bit): 2799 * XGMAC receive parameter register 2800 */ 2801#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0 2802/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2803 2804#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 2805#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 2806#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 2807#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 2808 2809 2810/* 2811 * FR_AB_XM_MGT_INT_MSK_REG(128bit): 2812 * XGMAC management interrupt mask register 2813 */ 2814#define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0 2815/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2816 2817#define FRF_AB_XM_STAT_CNTR_OF_LBN 9 2818#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 2819#define FRF_AB_XM_STAT_CNTR_HF_LBN 8 2820#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 2821#define FRF_AB_XM_PRMBLE_ERR_LBN 2 2822#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 2823#define FRF_AB_XM_RMTFLT_LBN 1 2824#define FRF_AB_XM_RMTFLT_WIDTH 1 2825#define FRF_AB_XM_LCLFLT_LBN 0 2826#define FRF_AB_XM_LCLFLT_WIDTH 1 2827 2828 2829/* 2830 * FR_AB_XX_PWR_RST_REG(128bit): 2831 * XGXS/XAUI powerdown/reset register 2832 */ 2833#define FR_AB_XX_PWR_RST_REG_OFST 0x00001300 2834/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2835 2836#define FRF_AB_XX_PWRDND_SIG_LBN 31 2837#define FRF_AB_XX_PWRDND_SIG_WIDTH 1 2838#define FRF_AB_XX_PWRDNC_SIG_LBN 30 2839#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 2840#define FRF_AB_XX_PWRDNB_SIG_LBN 29 2841#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 2842#define FRF_AB_XX_PWRDNA_SIG_LBN 28 2843#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 2844#define FRF_AB_XX_SIM_MODE_LBN 27 2845#define FRF_AB_XX_SIM_MODE_WIDTH 1 2846#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 2847#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 2848#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 2849#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 2850#define FRF_AB_XX_RESETD_SIG_LBN 23 2851#define FRF_AB_XX_RESETD_SIG_WIDTH 1 2852#define FRF_AB_XX_RESETC_SIG_LBN 22 2853#define FRF_AB_XX_RESETC_SIG_WIDTH 1 2854#define FRF_AB_XX_RESETB_SIG_LBN 21 2855#define FRF_AB_XX_RESETB_SIG_WIDTH 1 2856#define FRF_AB_XX_RESETA_SIG_LBN 20 2857#define FRF_AB_XX_RESETA_SIG_WIDTH 1 2858#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 2859#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 2860#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 2861#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 2862#define FRF_AB_XX_SD_RST_ACT_LBN 16 2863#define FRF_AB_XX_SD_RST_ACT_WIDTH 1 2864#define FRF_AB_XX_PWRDND_EN_LBN 15 2865#define FRF_AB_XX_PWRDND_EN_WIDTH 1 2866#define FRF_AB_XX_PWRDNC_EN_LBN 14 2867#define FRF_AB_XX_PWRDNC_EN_WIDTH 1 2868#define FRF_AB_XX_PWRDNB_EN_LBN 13 2869#define FRF_AB_XX_PWRDNB_EN_WIDTH 1 2870#define FRF_AB_XX_PWRDNA_EN_LBN 12 2871#define FRF_AB_XX_PWRDNA_EN_WIDTH 1 2872#define FRF_AB_XX_RSTPLLCD_EN_LBN 9 2873#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 2874#define FRF_AB_XX_RSTPLLAB_EN_LBN 8 2875#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 2876#define FRF_AB_XX_RESETD_EN_LBN 7 2877#define FRF_AB_XX_RESETD_EN_WIDTH 1 2878#define FRF_AB_XX_RESETC_EN_LBN 6 2879#define FRF_AB_XX_RESETC_EN_WIDTH 1 2880#define FRF_AB_XX_RESETB_EN_LBN 5 2881#define FRF_AB_XX_RESETB_EN_WIDTH 1 2882#define FRF_AB_XX_RESETA_EN_LBN 4 2883#define FRF_AB_XX_RESETA_EN_WIDTH 1 2884#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 2885#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 2886#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 2887#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 2888#define FRF_AB_XX_RST_XX_EN_LBN 0 2889#define FRF_AB_XX_RST_XX_EN_WIDTH 1 2890 2891 2892/* 2893 * FR_AB_XX_SD_CTL_REG(128bit): 2894 * XGXS/XAUI powerdown/reset control register 2895 */ 2896#define FR_AB_XX_SD_CTL_REG_OFST 0x00001310 2897/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2898 2899#define FRF_AB_XX_TERMADJ1_LBN 17 2900#define FRF_AB_XX_TERMADJ1_WIDTH 1 2901#define FRF_AB_XX_TERMADJ0_LBN 16 2902#define FRF_AB_XX_TERMADJ0_WIDTH 1 2903#define FRF_AB_XX_HIDRVD_LBN 15 2904#define FRF_AB_XX_HIDRVD_WIDTH 1 2905#define FRF_AB_XX_LODRVD_LBN 14 2906#define FRF_AB_XX_LODRVD_WIDTH 1 2907#define FRF_AB_XX_HIDRVC_LBN 13 2908#define FRF_AB_XX_HIDRVC_WIDTH 1 2909#define FRF_AB_XX_LODRVC_LBN 12 2910#define FRF_AB_XX_LODRVC_WIDTH 1 2911#define FRF_AB_XX_HIDRVB_LBN 11 2912#define FRF_AB_XX_HIDRVB_WIDTH 1 2913#define FRF_AB_XX_LODRVB_LBN 10 2914#define FRF_AB_XX_LODRVB_WIDTH 1 2915#define FRF_AB_XX_HIDRVA_LBN 9 2916#define FRF_AB_XX_HIDRVA_WIDTH 1 2917#define FRF_AB_XX_LODRVA_LBN 8 2918#define FRF_AB_XX_LODRVA_WIDTH 1 2919#define FRF_AB_XX_LPBKD_LBN 3 2920#define FRF_AB_XX_LPBKD_WIDTH 1 2921#define FRF_AB_XX_LPBKC_LBN 2 2922#define FRF_AB_XX_LPBKC_WIDTH 1 2923#define FRF_AB_XX_LPBKB_LBN 1 2924#define FRF_AB_XX_LPBKB_WIDTH 1 2925#define FRF_AB_XX_LPBKA_LBN 0 2926#define FRF_AB_XX_LPBKA_WIDTH 1 2927 2928 2929/* 2930 * FR_AB_XX_TXDRV_CTL_REG(128bit): 2931 * XAUI SerDes transmit drive control register 2932 */ 2933#define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320 2934/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2935 2936#define FRF_AB_XX_DEQD_LBN 28 2937#define FRF_AB_XX_DEQD_WIDTH 4 2938#define FRF_AB_XX_DEQC_LBN 24 2939#define FRF_AB_XX_DEQC_WIDTH 4 2940#define FRF_AB_XX_DEQB_LBN 20 2941#define FRF_AB_XX_DEQB_WIDTH 4 2942#define FRF_AB_XX_DEQA_LBN 16 2943#define FRF_AB_XX_DEQA_WIDTH 4 2944#define FRF_AB_XX_DTXD_LBN 12 2945#define FRF_AB_XX_DTXD_WIDTH 4 2946#define FRF_AB_XX_DTXC_LBN 8 2947#define FRF_AB_XX_DTXC_WIDTH 4 2948#define FRF_AB_XX_DTXB_LBN 4 2949#define FRF_AB_XX_DTXB_WIDTH 4 2950#define FRF_AB_XX_DTXA_LBN 0 2951#define FRF_AB_XX_DTXA_WIDTH 4 2952 2953 2954/* 2955 * FR_AB_XX_PRBS_CTL_REG(128bit): 2956 * documentation to be written for sum_XX_PRBS_CTL_REG 2957 */ 2958#define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330 2959/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2960 2961#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 2962#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 2963#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 2964#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 2965#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 2966#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 2967#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 2968#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 2969#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 2970#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 2971#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 2972#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 2973#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 2974#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 2975#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 2976#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 2977#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 2978#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 2979#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 2980#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 2981#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 2982#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 2983#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 2984#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 2985#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 2986#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 2987#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 2988#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 2989#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 2990#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 2991#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 2992#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 2993#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 2994#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 2995#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 2996#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 2997#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 2998#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 2999#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 3000#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 3001#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 3002#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 3003#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 3004#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 3005#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 3006#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 3007#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 3008#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 3009 3010 3011/* 3012 * FR_AB_XX_PRBS_CHK_REG(128bit): 3013 * documentation to be written for sum_XX_PRBS_CHK_REG 3014 */ 3015#define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340 3016/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3017 3018#define FRF_AB_XX_REV_LB_EN_LBN 16 3019#define FRF_AB_XX_REV_LB_EN_WIDTH 1 3020#define FRF_AB_XX_CH3_DEG_DET_LBN 15 3021#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 3022#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 3023#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 3024#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 3025#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 3026#define FRF_AB_XX_CH3_ERR_CHK_LBN 12 3027#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 3028#define FRF_AB_XX_CH2_DEG_DET_LBN 11 3029#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 3030#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 3031#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 3032#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 3033#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 3034#define FRF_AB_XX_CH2_ERR_CHK_LBN 8 3035#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 3036#define FRF_AB_XX_CH1_DEG_DET_LBN 7 3037#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 3038#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 3039#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 3040#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 3041#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 3042#define FRF_AB_XX_CH1_ERR_CHK_LBN 4 3043#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 3044#define FRF_AB_XX_CH0_DEG_DET_LBN 3 3045#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 3046#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 3047#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 3048#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 3049#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 3050#define FRF_AB_XX_CH0_ERR_CHK_LBN 0 3051#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 3052 3053 3054/* 3055 * FR_AB_XX_PRBS_ERR_REG(128bit): 3056 * documentation to be written for sum_XX_PRBS_ERR_REG 3057 */ 3058#define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350 3059/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3060 3061#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 3062#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 3063#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 3064#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 3065#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 3066#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 3067#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 3068#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 3069 3070 3071/* 3072 * FR_AB_XX_CORE_STAT_REG(128bit): 3073 * XAUI XGXS core status register 3074 */ 3075#define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360 3076/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3077 3078#define FRF_AB_XX_FORCE_SIG3_LBN 31 3079#define FRF_AB_XX_FORCE_SIG3_WIDTH 1 3080#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 3081#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 3082#define FRF_AB_XX_FORCE_SIG2_LBN 29 3083#define FRF_AB_XX_FORCE_SIG2_WIDTH 1 3084#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 3085#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 3086#define FRF_AB_XX_FORCE_SIG1_LBN 27 3087#define FRF_AB_XX_FORCE_SIG1_WIDTH 1 3088#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 3089#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 3090#define FRF_AB_XX_FORCE_SIG0_LBN 25 3091#define FRF_AB_XX_FORCE_SIG0_WIDTH 1 3092#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 3093#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 3094#define FRF_AB_XX_XGXS_LB_EN_LBN 23 3095#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 3096#define FRF_AB_XX_XGMII_LB_EN_LBN 22 3097#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 3098#define FRF_AB_XX_MATCH_FAULT_LBN 21 3099#define FRF_AB_XX_MATCH_FAULT_WIDTH 1 3100#define FRF_AB_XX_ALIGN_DONE_LBN 20 3101#define FRF_AB_XX_ALIGN_DONE_WIDTH 1 3102#define FRF_AB_XX_SYNC_STAT3_LBN 19 3103#define FRF_AB_XX_SYNC_STAT3_WIDTH 1 3104#define FRF_AB_XX_SYNC_STAT2_LBN 18 3105#define FRF_AB_XX_SYNC_STAT2_WIDTH 1 3106#define FRF_AB_XX_SYNC_STAT1_LBN 17 3107#define FRF_AB_XX_SYNC_STAT1_WIDTH 1 3108#define FRF_AB_XX_SYNC_STAT0_LBN 16 3109#define FRF_AB_XX_SYNC_STAT0_WIDTH 1 3110#define FRF_AB_XX_COMMA_DET_CH3_LBN 15 3111#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 3112#define FRF_AB_XX_COMMA_DET_CH2_LBN 14 3113#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 3114#define FRF_AB_XX_COMMA_DET_CH1_LBN 13 3115#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 3116#define FRF_AB_XX_COMMA_DET_CH0_LBN 12 3117#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 3118#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 3119#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 3120#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 3121#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 3122#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 3123#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 3124#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 3125#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 3126#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 3127#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 3128#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 3129#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 3130#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 3131#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 3132#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 3133#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 3134#define FRF_AB_XX_DISPERR_CH3_LBN 3 3135#define FRF_AB_XX_DISPERR_CH3_WIDTH 1 3136#define FRF_AB_XX_DISPERR_CH2_LBN 2 3137#define FRF_AB_XX_DISPERR_CH2_WIDTH 1 3138#define FRF_AB_XX_DISPERR_CH1_LBN 1 3139#define FRF_AB_XX_DISPERR_CH1_WIDTH 1 3140#define FRF_AB_XX_DISPERR_CH0_LBN 0 3141#define FRF_AB_XX_DISPERR_CH0_WIDTH 1 3142 3143 3144/* 3145 * FR_AA_RX_DESC_PTR_TBL_KER(128bit): 3146 * Receive descriptor pointer table 3147 */ 3148#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800 3149/* falcona0=net_func_bar2 */ 3150#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 3151#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 3152/* 3153 * FR_AZ_RX_DESC_PTR_TBL(128bit): 3154 * Receive descriptor pointer table 3155 */ 3156#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000 3157/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3158#define FR_AZ_RX_DESC_PTR_TBL_STEP 16 3159#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 3160#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096 3161 3162#define FRF_CZ_RX_HDR_SPLIT_LBN 90 3163#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 3164#define FRF_AZ_RX_RESET_LBN 89 3165#define FRF_AZ_RX_RESET_WIDTH 1 3166#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 3167#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 3168#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 3169#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 3170#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 3171#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 3172#define FRF_AZ_RX_DC_HW_RPTR_LBN 80 3173#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 3174#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 3175#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 3176#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 3177#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 3178#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 3179#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 3180#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 3181#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 3182#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 3183#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 3184#define FRF_AZ_RX_DESCQ_LABEL_LBN 5 3185#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 3186#define FRF_AZ_RX_DESCQ_SIZE_LBN 3 3187#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 3188#define FFE_AZ_RX_DESCQ_SIZE_4K 3 3189#define FFE_AZ_RX_DESCQ_SIZE_2K 2 3190#define FFE_AZ_RX_DESCQ_SIZE_1K 1 3191#define FFE_AZ_RX_DESCQ_SIZE_512 0 3192#define FRF_AZ_RX_DESCQ_TYPE_LBN 2 3193#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 3194#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 3195#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 3196#define FRF_AZ_RX_DESCQ_EN_LBN 0 3197#define FRF_AZ_RX_DESCQ_EN_WIDTH 1 3198 3199 3200/* 3201 * FR_AA_TX_DESC_PTR_TBL_KER(128bit): 3202 * Transmit descriptor pointer 3203 */ 3204#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900 3205/* falcona0=net_func_bar2 */ 3206#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 3207#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 3208/* 3209 * FR_AZ_TX_DESC_PTR_TBL(128bit): 3210 * Transmit descriptor pointer 3211 */ 3212#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000 3213/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3214#define FR_AZ_TX_DESC_PTR_TBL_STEP 16 3215#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096 3216#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 3217 3218#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 3219#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 3220#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 3221#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 3222#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 3223#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 3224#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 3225#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 3226#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 3227#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 3228#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 3229#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 3230#define FRF_AZ_TX_DESCQ_EN_LBN 88 3231#define FRF_AZ_TX_DESCQ_EN_WIDTH 1 3232#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 3233#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 3234#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 3235#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 3236#define FRF_AZ_TX_DC_HW_RPTR_LBN 80 3237#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 3238#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 3239#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 3240#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 3241#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 3242#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 3243#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 3244#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 3245#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 3246#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 3247#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 3248#define FRF_AZ_TX_DESCQ_LABEL_LBN 5 3249#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 3250#define FRF_AZ_TX_DESCQ_SIZE_LBN 3 3251#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 3252#define FFE_AZ_TX_DESCQ_SIZE_4K 3 3253#define FFE_AZ_TX_DESCQ_SIZE_2K 2 3254#define FFE_AZ_TX_DESCQ_SIZE_1K 1 3255#define FFE_AZ_TX_DESCQ_SIZE_512 0 3256#define FRF_AZ_TX_DESCQ_TYPE_LBN 1 3257#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 3258#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 3259#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 3260 3261 3262/* 3263 * FR_AA_EVQ_PTR_TBL_KER(128bit): 3264 * Event queue pointer table 3265 */ 3266#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00 3267/* falcona0=net_func_bar2 */ 3268#define FR_AA_EVQ_PTR_TBL_KER_STEP 16 3269#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 3270/* 3271 * FR_AZ_EVQ_PTR_TBL(128bit): 3272 * Event queue pointer table 3273 */ 3274#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000 3275/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3276#define FR_AZ_EVQ_PTR_TBL_STEP 16 3277#define FR_CZ_EVQ_PTR_TBL_ROWS 1024 3278#define FR_AB_EVQ_PTR_TBL_ROWS 4096 3279 3280#define FRF_BZ_EVQ_RPTR_IGN_LBN 40 3281#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 3282#define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39 3283#define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1 3284#define FRF_AZ_EVQ_NXT_WPTR_LBN 24 3285#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 3286#define FRF_AZ_EVQ_EN_LBN 23 3287#define FRF_AZ_EVQ_EN_WIDTH 1 3288#define FRF_AZ_EVQ_SIZE_LBN 20 3289#define FRF_AZ_EVQ_SIZE_WIDTH 3 3290#define FFE_AZ_EVQ_SIZE_32K 6 3291#define FFE_AZ_EVQ_SIZE_16K 5 3292#define FFE_AZ_EVQ_SIZE_8K 4 3293#define FFE_AZ_EVQ_SIZE_4K 3 3294#define FFE_AZ_EVQ_SIZE_2K 2 3295#define FFE_AZ_EVQ_SIZE_1K 1 3296#define FFE_AZ_EVQ_SIZE_512 0 3297#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 3298#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 3299 3300 3301/* 3302 * FR_AA_BUF_HALF_TBL_KER(64bit): 3303 * Buffer table in half buffer table mode direct access by driver 3304 */ 3305#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000 3306/* falcona0=net_func_bar2 */ 3307#define FR_AA_BUF_HALF_TBL_KER_STEP 8 3308#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 3309/* 3310 * FR_AZ_BUF_HALF_TBL(64bit): 3311 * Buffer table in half buffer table mode direct access by driver 3312 */ 3313#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000 3314/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3315#define FR_AZ_BUF_HALF_TBL_STEP 8 3316#define FR_CZ_BUF_HALF_TBL_ROWS 147456 3317#define FR_AB_BUF_HALF_TBL_ROWS 524288 3318 3319#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 3320#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 3321#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 3322#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 3323#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 3324#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 3325#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 3326#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 3327 3328 3329/* 3330 * FR_AA_BUF_FULL_TBL_KER(64bit): 3331 * Buffer table in full buffer table mode direct access by driver 3332 */ 3333#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000 3334/* falcona0=net_func_bar2 */ 3335#define FR_AA_BUF_FULL_TBL_KER_STEP 8 3336#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 3337/* 3338 * FR_AZ_BUF_FULL_TBL(64bit): 3339 * Buffer table in full buffer table mode direct access by driver 3340 */ 3341#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000 3342/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3343#define FR_AZ_BUF_FULL_TBL_STEP 8 3344 3345#define FR_CZ_BUF_FULL_TBL_ROWS 147456 3346#define FR_AB_BUF_FULL_TBL_ROWS 917504 3347 3348#define FRF_AZ_BUF_FULL_UNUSED_LBN 51 3349#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 3350#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 3351#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 3352#define FRF_AZ_BUF_ADR_REGION_LBN 48 3353#define FRF_AZ_BUF_ADR_REGION_WIDTH 2 3354#define FFE_AZ_BUF_ADR_REGN3 3 3355#define FFE_AZ_BUF_ADR_REGN2 2 3356#define FFE_AZ_BUF_ADR_REGN1 1 3357#define FFE_AZ_BUF_ADR_REGN0 0 3358#define FRF_AZ_BUF_ADR_FBUF_LBN 14 3359#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 3360#define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14 3361#define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32 3362#define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46 3363#define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2 3364#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 3365#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 3366 3367 3368/* 3369 * FR_AZ_RX_FILTER_TBL0(128bit): 3370 * TCP/IPv4 Receive filter table 3371 */ 3372#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000 3373/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3374#define FR_AZ_RX_FILTER_TBL0_STEP 32 3375#define FR_AZ_RX_FILTER_TBL0_ROWS 8192 3376/* 3377 * FR_AB_RX_FILTER_TBL1(128bit): 3378 * TCP/IPv4 Receive filter table 3379 */ 3380#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010 3381/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3382#define FR_AB_RX_FILTER_TBL1_STEP 32 3383#define FR_AB_RX_FILTER_TBL1_ROWS 8192 3384 3385#define FRF_BZ_RSS_EN_LBN 110 3386#define FRF_BZ_RSS_EN_WIDTH 1 3387#define FRF_BZ_SCATTER_EN_LBN 109 3388#define FRF_BZ_SCATTER_EN_WIDTH 1 3389#define FRF_AZ_TCP_UDP_LBN 108 3390#define FRF_AZ_TCP_UDP_WIDTH 1 3391#define FRF_AZ_RXQ_ID_LBN 96 3392#define FRF_AZ_RXQ_ID_WIDTH 12 3393#define FRF_AZ_DEST_IP_LBN 64 3394#define FRF_AZ_DEST_IP_WIDTH 32 3395#define FRF_AZ_DEST_PORT_TCP_LBN 48 3396#define FRF_AZ_DEST_PORT_TCP_WIDTH 16 3397#define FRF_AZ_SRC_IP_LBN 16 3398#define FRF_AZ_SRC_IP_WIDTH 32 3399#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 3400#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 3401 3402 3403/* 3404 * FR_CZ_RX_MAC_FILTER_TBL0(128bit): 3405 * Receive Ethernet filter table 3406 */ 3407#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010 3408/* sienaa0=net_func_bar2 */ 3409#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 3410#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 3411 3412#define FRF_CZ_RMFT_RSS_EN_LBN 75 3413#define FRF_CZ_RMFT_RSS_EN_WIDTH 1 3414#define FRF_CZ_RMFT_SCATTER_EN_LBN 74 3415#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 3416#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 3417#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 3418#define FRF_CZ_RMFT_RXQ_ID_LBN 61 3419#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 3420#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 3421#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 3422#define FRF_CZ_RMFT_DEST_MAC_LBN 12 3423#define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 3424#define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12 3425#define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32 3426#define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44 3427#define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16 3428#define FRF_CZ_RMFT_VLAN_ID_LBN 0 3429#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 3430 3431 3432/* 3433 * FR_AZ_TIMER_TBL(128bit): 3434 * Timer table 3435 */ 3436#define FR_AZ_TIMER_TBL_OFST 0x00f70000 3437/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3438#define FR_AZ_TIMER_TBL_STEP 16 3439#define FR_CZ_TIMER_TBL_ROWS 1024 3440#define FR_AB_TIMER_TBL_ROWS 4096 3441 3442#define FRF_CZ_TIMER_Q_EN_LBN 33 3443#define FRF_CZ_TIMER_Q_EN_WIDTH 1 3444#define FRF_CZ_INT_ARMD_LBN 32 3445#define FRF_CZ_INT_ARMD_WIDTH 1 3446#define FRF_CZ_INT_PEND_LBN 31 3447#define FRF_CZ_INT_PEND_WIDTH 1 3448#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 3449#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 3450#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 3451#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 3452#define FRF_CZ_TIMER_MODE_LBN 14 3453#define FRF_CZ_TIMER_MODE_WIDTH 2 3454#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 3455#define FFE_CZ_TIMER_MODE_TRIG_START 2 3456#define FFE_CZ_TIMER_MODE_IMMED_START 1 3457#define FFE_CZ_TIMER_MODE_DIS 0 3458#define FRF_AB_TIMER_MODE_LBN 12 3459#define FRF_AB_TIMER_MODE_WIDTH 2 3460#define FFE_AB_TIMER_MODE_INT_HLDOFF 2 3461#define FFE_AB_TIMER_MODE_TRIG_START 2 3462#define FFE_AB_TIMER_MODE_IMMED_START 1 3463#define FFE_AB_TIMER_MODE_DIS 0 3464#define FRF_CZ_TIMER_VAL_LBN 0 3465#define FRF_CZ_TIMER_VAL_WIDTH 14 3466#define FRF_AB_TIMER_VAL_LBN 0 3467#define FRF_AB_TIMER_VAL_WIDTH 12 3468 3469 3470/* 3471 * FR_BZ_TX_PACE_TBL(128bit): 3472 * Transmit pacing table 3473 */ 3474#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000 3475/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */ 3476#define FR_AZ_TX_PACE_TBL_STEP 16 3477#define FR_CZ_TX_PACE_TBL_ROWS 1024 3478#define FR_BB_TX_PACE_TBL_ROWS 4096 3479/* 3480 * FR_AA_TX_PACE_TBL(128bit): 3481 * Transmit pacing table 3482 */ 3483#define FR_AA_TX_PACE_TBL_OFST 0x00f80040 3484/* falcona0=char_func_bar0 */ 3485/* FR_AZ_TX_PACE_TBL_STEP 16 */ 3486#define FR_AA_TX_PACE_TBL_ROWS 4092 3487 3488#define FRF_AZ_TX_PACE_LBN 0 3489#define FRF_AZ_TX_PACE_WIDTH 5 3490 3491 3492/* 3493 * FR_BZ_RX_INDIRECTION_TBL(7bit): 3494 * RX Indirection Table 3495 */ 3496#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000 3497/* falconb0,sienaa0=net_func_bar2 */ 3498#define FR_BZ_RX_INDIRECTION_TBL_STEP 16 3499#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 3500 3501#define FRF_BZ_IT_QUEUE_LBN 0 3502#define FRF_BZ_IT_QUEUE_WIDTH 6 3503 3504 3505/* 3506 * FR_CZ_TX_FILTER_TBL0(128bit): 3507 * TCP/IPv4 Transmit filter table 3508 */ 3509#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000 3510/* sienaa0=net_func_bar2 */ 3511#define FR_CZ_TX_FILTER_TBL0_STEP 16 3512#define FR_CZ_TX_FILTER_TBL0_ROWS 8192 3513 3514#define FRF_CZ_TIFT_TCP_UDP_LBN 108 3515#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 3516#define FRF_CZ_TIFT_TXQ_ID_LBN 96 3517#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 3518#define FRF_CZ_TIFT_DEST_IP_LBN 64 3519#define FRF_CZ_TIFT_DEST_IP_WIDTH 32 3520#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 3521#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 3522#define FRF_CZ_TIFT_SRC_IP_LBN 16 3523#define FRF_CZ_TIFT_SRC_IP_WIDTH 32 3524#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 3525#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 3526 3527 3528/* 3529 * FR_CZ_TX_MAC_FILTER_TBL0(128bit): 3530 * Transmit Ethernet filter table 3531 */ 3532#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000 3533/* sienaa0=net_func_bar2 */ 3534#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 3535#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 3536 3537#define FRF_CZ_TMFT_TXQ_ID_LBN 61 3538#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 3539#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 3540#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 3541#define FRF_CZ_TMFT_SRC_MAC_LBN 12 3542#define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 3543#define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12 3544#define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32 3545#define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44 3546#define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16 3547#define FRF_CZ_TMFT_VLAN_ID_LBN 0 3548#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 3549 3550 3551/* 3552 * FR_CZ_MC_TREG_SMEM(32bit): 3553 * MC Shared Memory 3554 */ 3555#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000 3556/* sienaa0=net_func_bar2 */ 3557#define FR_CZ_MC_TREG_SMEM_STEP 4 3558#define FR_CZ_MC_TREG_SMEM_ROWS 512 3559 3560#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 3561#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 3562 3563 3564/* 3565 * FR_BB_MSIX_VECTOR_TABLE(128bit): 3566 * MSIX Vector Table 3567 */ 3568#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000 3569/* falconb0=net_func_bar2 */ 3570#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 3571#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 3572/* 3573 * FR_CZ_MSIX_VECTOR_TABLE(128bit): 3574 * MSIX Vector Table 3575 */ 3576#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000 3577/* sienaa0=pci_f0_bar4 */ 3578/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ 3579#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 3580 3581#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 3582#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 3583#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 3584#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 3585#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 3586#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 3587#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 3588#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 3589#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 3590#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 3591 3592 3593/* 3594 * FR_BB_MSIX_PBA_TABLE(32bit): 3595 * MSIX Pending Bit Array 3596 */ 3597#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000 3598/* falconb0=net_func_bar2 */ 3599#define FR_BZ_MSIX_PBA_TABLE_STEP 4 3600#define FR_BB_MSIX_PBA_TABLE_ROWS 2 3601/* 3602 * FR_CZ_MSIX_PBA_TABLE(32bit): 3603 * MSIX Pending Bit Array 3604 */ 3605#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000 3606/* sienaa0=pci_f0_bar4 */ 3607/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ 3608#define FR_CZ_MSIX_PBA_TABLE_ROWS 32 3609 3610#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 3611#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 3612 3613 3614/* 3615 * FR_AZ_SRM_DBG_REG(64bit): 3616 * SRAM debug access 3617 */ 3618#define FR_AZ_SRM_DBG_REG_OFST 0x03000000 3619/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3620#define FR_AZ_SRM_DBG_REG_STEP 8 3621 3622#define FR_CZ_SRM_DBG_REG_ROWS 262144 3623#define FR_AB_SRM_DBG_REG_ROWS 2097152 3624 3625#define FRF_AZ_SRM_DBG_LBN 0 3626#define FRF_AZ_SRM_DBG_WIDTH 64 3627#define FRF_AZ_SRM_DBG_DW0_LBN 0 3628#define FRF_AZ_SRM_DBG_DW0_WIDTH 32 3629#define FRF_AZ_SRM_DBG_DW1_LBN 32 3630#define FRF_AZ_SRM_DBG_DW1_WIDTH 32 3631 3632 3633/* 3634 * FR_AA_INT_ACK_CHAR(32bit): 3635 * CHAR interrupt acknowledge register 3636 */ 3637#define FR_AA_INT_ACK_CHAR_OFST 0x00000060 3638/* falcona0=char_func_bar0 */ 3639 3640#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 3641#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 3642 3643 3644/* FS_DRIVER_EV */ 3645#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 3646#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 3647#define FSE_AZ_TX_DSC_ERROR_EV 15 3648#define FSE_AZ_RX_DSC_ERROR_EV 14 3649#define FSE_AZ_RX_RECOVER_EV 11 3650#define FSE_AZ_TIMER_EV 10 3651#define FSE_AZ_TX_PKT_NON_TCP_UDP 9 3652#define FSE_AZ_WAKE_UP_EV 6 3653#define FSE_AZ_SRM_UPD_DONE_EV 5 3654#define FSE_AZ_EVQ_NOT_EN_EV 3 3655#define FSE_AZ_EVQ_INIT_DONE_EV 2 3656#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 3657#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 3658#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 3659#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 3660 3661 3662/* FS_EVENT_ENTRY */ 3663#define FSF_AZ_EV_CODE_LBN 60 3664#define FSF_AZ_EV_CODE_WIDTH 4 3665#define FSE_AZ_EV_CODE_USER_EV 8 3666#define FSE_AZ_EV_CODE_DRV_GEN_EV 7 3667#define FSE_AZ_EV_CODE_GLOBAL_EV 6 3668#define FSE_AZ_EV_CODE_DRIVER_EV 5 3669#define FSE_AZ_EV_CODE_TX_EV 2 3670#define FSE_AZ_EV_CODE_RX_EV 0 3671#define FSF_AZ_EV_DATA_LBN 0 3672#define FSF_AZ_EV_DATA_WIDTH 60 3673#define FSF_AZ_EV_DATA_DW0_LBN 0 3674#define FSF_AZ_EV_DATA_DW0_WIDTH 32 3675#define FSF_AZ_EV_DATA_DW1_LBN 32 3676#define FSF_AZ_EV_DATA_DW1_WIDTH 28 3677 3678 3679/* FS_GLOBAL_EV */ 3680#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 3681#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 3682#define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11 3683#define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1 3684#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10 3685#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1 3686#define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9 3687#define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1 3688#define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 3689#define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 3690 3691 3692/* FS_RX_EV */ 3693#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 3694#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 3695#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 3696#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 3697#define FSF_AZ_RX_EV_PKT_OK_LBN 56 3698#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 3699#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 3700#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 3701#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 3702#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3703#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 3704#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 3705#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 3706#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 3707#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 3708#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 3709#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 3710#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 3711#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 3712#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 3713#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 3714#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 3715#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 3716#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 3717#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 3718#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 3719#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 3720#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 3721#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 3722#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 3723#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 3724#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 3725#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 3726#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2 3727#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 3728#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1 3729#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 3730#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0 3731#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 3732#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 3733#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 3734#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 3735#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 3736#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 3737#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 3738#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 3739#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 3740#define FSF_AZ_RX_EV_Q_LABEL_LBN 32 3741#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 3742#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 3743#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 3744#define FSF_AZ_RX_EV_PORT_LBN 30 3745#define FSF_AZ_RX_EV_PORT_WIDTH 1 3746#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 3747#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 3748#define FSF_AZ_RX_EV_SOP_LBN 15 3749#define FSF_AZ_RX_EV_SOP_WIDTH 1 3750#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 3751#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 3752#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 3753#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 3754#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 3755#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 3756#define FSF_AZ_RX_EV_DESC_PTR_LBN 0 3757#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 3758 3759 3760/* FS_RX_KER_DESC */ 3761#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 3762#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 3763#define FSF_AZ_RX_KER_BUF_REGION_LBN 46 3764#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 3765#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 3766#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 3767#define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0 3768#define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 3769#define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 3770#define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 3771 3772 3773/* FS_RX_USER_DESC */ 3774#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 3775#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 3776#define FSF_AZ_RX_USER_BUF_ID_LBN 0 3777#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 3778 3779 3780/* FS_TX_EV */ 3781#define FSF_AZ_TX_EV_PKT_ERR_LBN 38 3782#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 3783#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 3784#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 3785#define FSF_AZ_TX_EV_Q_LABEL_LBN 32 3786#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 3787#define FSF_AZ_TX_EV_PORT_LBN 16 3788#define FSF_AZ_TX_EV_PORT_WIDTH 1 3789#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 3790#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 3791#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 3792#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3793#define FSF_AZ_TX_EV_COMP_LBN 12 3794#define FSF_AZ_TX_EV_COMP_WIDTH 1 3795#define FSF_AZ_TX_EV_DESC_PTR_LBN 0 3796#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 3797 3798 3799/* FS_TX_KER_DESC */ 3800#define FSF_AZ_TX_KER_CONT_LBN 62 3801#define FSF_AZ_TX_KER_CONT_WIDTH 1 3802#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 3803#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 3804#define FSF_AZ_TX_KER_BUF_REGION_LBN 46 3805#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 3806#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 3807#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 3808#define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0 3809#define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 3810#define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 3811#define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 3812 3813 3814/* FS_TX_USER_DESC */ 3815#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 3816#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 3817#define FSF_AZ_TX_USER_CONT_LBN 46 3818#define FSF_AZ_TX_USER_CONT_WIDTH 1 3819#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 3820#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 3821#define FSF_AZ_TX_USER_BUF_ID_LBN 13 3822#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 3823#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 3824#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 3825 3826 3827/* FS_USER_EV */ 3828#define FSF_CZ_USER_QID_LBN 32 3829#define FSF_CZ_USER_QID_WIDTH 10 3830#define FSF_CZ_USER_EV_REG_VALUE_LBN 0 3831#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 3832 3833 3834/* FS_NET_IVEC */ 3835#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 3836#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 3837#define FSF_AZ_NET_IVEC_INT_Q_LBN 40 3838#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 3839#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 3840#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 3841#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 3842#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 3843#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 3844#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 3845 3846 3847/* DRIVER_EV */ 3848/* Sub-fields of an RX flush completion event */ 3849#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 3850#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 3851#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 3852#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 3853 3854 3855 3856/************************************************************************** 3857 * 3858 * Falcon non-volatile configuration 3859 * 3860 ************************************************************************** 3861 */ 3862 3863 3864#define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST 3865 3866 3867#ifdef __cplusplus 3868} 3869#endif 3870 3871 3872 3873 3874#endif /* _SYS_EFX_REGS_H */ 3875