1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006-2016 Solarflare Communications Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 *    this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright notice,
13 *    this list of conditions and the following disclaimer in the documentation
14 *    and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * The views and conclusions contained in the software and documentation are
29 * those of the authors and should not be interpreted as representing official
30 * policies, either expressed or implied, of the FreeBSD Project.
31 *
32 * $FreeBSD$
33 */
34
35#ifndef	_SYS_EFX_H
36#define	_SYS_EFX_H
37
38#include "efsys.h"
39#include "efx_check.h"
40#include "efx_phy_ids.h"
41
42#ifdef	__cplusplus
43extern "C" {
44#endif
45
46#define	EFX_STATIC_ASSERT(_cond)		\
47	((void)sizeof(char[(_cond) ? 1 : -1]))
48
49#define	EFX_ARRAY_SIZE(_array)			\
50	(sizeof(_array) / sizeof((_array)[0]))
51
52#define	EFX_FIELD_OFFSET(_type, _field)		\
53	((size_t) &(((_type *)0)->_field))
54
55/* Round value up to the nearest power of two. */
56#define	EFX_P2ROUNDUP(_type, _value, _align)	\
57	(-(-(_type)(_value) & -(_type)(_align)))
58
59/* Align value down to the nearest power of two. */
60#define	EFX_P2ALIGN(_type, _value, _align)	\
61	((_type)(_value) & -(_type)(_align))
62
63/* Test if value is power of 2 aligned. */
64#define	EFX_IS_P2ALIGNED(_type, _value, _align)	\
65	((((_type)(_value)) & ((_type)(_align) - 1)) == 0)
66
67/* Return codes */
68
69typedef __success(return == 0) int efx_rc_t;
70
71
72/* Chip families */
73
74typedef enum efx_family_e {
75	EFX_FAMILY_INVALID,
76	EFX_FAMILY_FALCON,	/* Obsolete and not supported */
77	EFX_FAMILY_SIENA,
78	EFX_FAMILY_HUNTINGTON,
79	EFX_FAMILY_MEDFORD,
80	EFX_FAMILY_NTYPES
81} efx_family_t;
82
83extern	__checkReturn	efx_rc_t
84efx_family(
85	__in		uint16_t venid,
86	__in		uint16_t devid,
87	__out		efx_family_t *efp);
88
89
90#define	EFX_PCI_VENID_SFC			0x1924
91
92#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
93
94#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
95#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
96#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
97
98#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
99#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
100#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
101
102#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
103#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
104
105#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
106#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
107#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
108
109#define	EFX_MEM_BAR	2
110
111/* Error codes */
112
113enum {
114	EFX_ERR_INVALID,
115	EFX_ERR_SRAM_OOB,
116	EFX_ERR_BUFID_DC_OOB,
117	EFX_ERR_MEM_PERR,
118	EFX_ERR_RBUF_OWN,
119	EFX_ERR_TBUF_OWN,
120	EFX_ERR_RDESQ_OWN,
121	EFX_ERR_TDESQ_OWN,
122	EFX_ERR_EVQ_OWN,
123	EFX_ERR_EVFF_OFLO,
124	EFX_ERR_ILL_ADDR,
125	EFX_ERR_SRAM_PERR,
126	EFX_ERR_NCODES
127};
128
129/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
130extern	__checkReturn		uint32_t
131efx_crc32_calculate(
132	__in			uint32_t crc_init,
133	__in_ecount(length)	uint8_t const *input,
134	__in			int length);
135
136
137/* Type prototypes */
138
139typedef struct efx_rxq_s	efx_rxq_t;
140
141/* NIC */
142
143typedef struct efx_nic_s	efx_nic_t;
144
145extern	__checkReturn	efx_rc_t
146efx_nic_create(
147	__in		efx_family_t family,
148	__in		efsys_identifier_t *esip,
149	__in		efsys_bar_t *esbp,
150	__in		efsys_lock_t *eslp,
151	__deref_out	efx_nic_t **enpp);
152
153extern	__checkReturn	efx_rc_t
154efx_nic_probe(
155	__in		efx_nic_t *enp);
156
157extern	__checkReturn	efx_rc_t
158efx_nic_init(
159	__in		efx_nic_t *enp);
160
161extern	__checkReturn	efx_rc_t
162efx_nic_reset(
163	__in		efx_nic_t *enp);
164
165#if EFSYS_OPT_DIAG
166
167extern	__checkReturn	efx_rc_t
168efx_nic_register_test(
169	__in		efx_nic_t *enp);
170
171#endif	/* EFSYS_OPT_DIAG */
172
173extern		void
174efx_nic_fini(
175	__in		efx_nic_t *enp);
176
177extern		void
178efx_nic_unprobe(
179	__in		efx_nic_t *enp);
180
181extern		void
182efx_nic_destroy(
183	__in	efx_nic_t *enp);
184
185#define	EFX_PCIE_LINK_SPEED_GEN1		1
186#define	EFX_PCIE_LINK_SPEED_GEN2		2
187#define	EFX_PCIE_LINK_SPEED_GEN3		3
188
189typedef enum efx_pcie_link_performance_e {
190	EFX_PCIE_LINK_PERFORMANCE_UNKNOWN_BANDWIDTH,
191	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_BANDWIDTH,
192	EFX_PCIE_LINK_PERFORMANCE_SUBOPTIMAL_LATENCY,
193	EFX_PCIE_LINK_PERFORMANCE_OPTIMAL
194} efx_pcie_link_performance_t;
195
196extern	__checkReturn	efx_rc_t
197efx_nic_calculate_pcie_link_bandwidth(
198	__in		uint32_t pcie_link_width,
199	__in		uint32_t pcie_link_gen,
200	__out		uint32_t *bandwidth_mbpsp);
201
202extern	__checkReturn	efx_rc_t
203efx_nic_check_pcie_link_speed(
204	__in		efx_nic_t *enp,
205	__in		uint32_t pcie_link_width,
206	__in		uint32_t pcie_link_gen,
207	__out		efx_pcie_link_performance_t *resultp);
208
209#if EFSYS_OPT_MCDI
210
211#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
212/* Huntington and Medford require MCDIv2 commands */
213#define	WITH_MCDI_V2 1
214#endif
215
216typedef struct efx_mcdi_req_s efx_mcdi_req_t;
217
218typedef enum efx_mcdi_exception_e {
219	EFX_MCDI_EXCEPTION_MC_REBOOT,
220	EFX_MCDI_EXCEPTION_MC_BADASSERT,
221} efx_mcdi_exception_t;
222
223#if EFSYS_OPT_MCDI_LOGGING
224typedef enum efx_log_msg_e {
225	EFX_LOG_INVALID,
226	EFX_LOG_MCDI_REQUEST,
227	EFX_LOG_MCDI_RESPONSE,
228} efx_log_msg_t;
229#endif /* EFSYS_OPT_MCDI_LOGGING */
230
231typedef struct efx_mcdi_transport_s {
232	void		*emt_context;
233	efsys_mem_t	*emt_dma_mem;
234	void		(*emt_execute)(void *, efx_mcdi_req_t *);
235	void		(*emt_ev_cpl)(void *);
236	void		(*emt_exception)(void *, efx_mcdi_exception_t);
237#if EFSYS_OPT_MCDI_LOGGING
238	void		(*emt_logger)(void *, efx_log_msg_t,
239					void *, size_t, void *, size_t);
240#endif /* EFSYS_OPT_MCDI_LOGGING */
241#if EFSYS_OPT_MCDI_PROXY_AUTH
242	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
243#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
244} efx_mcdi_transport_t;
245
246extern	__checkReturn	efx_rc_t
247efx_mcdi_init(
248	__in		efx_nic_t *enp,
249	__in		const efx_mcdi_transport_t *mtp);
250
251extern	__checkReturn	efx_rc_t
252efx_mcdi_reboot(
253	__in		efx_nic_t *enp);
254
255			void
256efx_mcdi_new_epoch(
257	__in		efx_nic_t *enp);
258
259extern			void
260efx_mcdi_get_timeout(
261	__in		efx_nic_t *enp,
262	__in		efx_mcdi_req_t *emrp,
263	__out		uint32_t *usec_timeoutp);
264
265extern			void
266efx_mcdi_request_start(
267	__in		efx_nic_t *enp,
268	__in		efx_mcdi_req_t *emrp,
269	__in		boolean_t ev_cpl);
270
271extern	__checkReturn	boolean_t
272efx_mcdi_request_poll(
273	__in		efx_nic_t *enp);
274
275extern	__checkReturn	boolean_t
276efx_mcdi_request_abort(
277	__in		efx_nic_t *enp);
278
279extern			void
280efx_mcdi_fini(
281	__in		efx_nic_t *enp);
282
283#endif	/* EFSYS_OPT_MCDI */
284
285/* INTR */
286
287#define	EFX_NINTR_SIENA 1024
288
289typedef enum efx_intr_type_e {
290	EFX_INTR_INVALID = 0,
291	EFX_INTR_LINE,
292	EFX_INTR_MESSAGE,
293	EFX_INTR_NTYPES
294} efx_intr_type_t;
295
296#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
297
298extern	__checkReturn	efx_rc_t
299efx_intr_init(
300	__in		efx_nic_t *enp,
301	__in		efx_intr_type_t type,
302	__in		efsys_mem_t *esmp);
303
304extern			void
305efx_intr_enable(
306	__in		efx_nic_t *enp);
307
308extern			void
309efx_intr_disable(
310	__in		efx_nic_t *enp);
311
312extern			void
313efx_intr_disable_unlocked(
314	__in		efx_nic_t *enp);
315
316#define	EFX_INTR_NEVQS	32
317
318extern	__checkReturn	efx_rc_t
319efx_intr_trigger(
320	__in		efx_nic_t *enp,
321	__in		unsigned int level);
322
323extern			void
324efx_intr_status_line(
325	__in		efx_nic_t *enp,
326	__out		boolean_t *fatalp,
327	__out		uint32_t *maskp);
328
329extern			void
330efx_intr_status_message(
331	__in		efx_nic_t *enp,
332	__in		unsigned int message,
333	__out		boolean_t *fatalp);
334
335extern			void
336efx_intr_fatal(
337	__in		efx_nic_t *enp);
338
339extern			void
340efx_intr_fini(
341	__in		efx_nic_t *enp);
342
343/* MAC */
344
345#if EFSYS_OPT_MAC_STATS
346
347/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
348typedef enum efx_mac_stat_e {
349	EFX_MAC_RX_OCTETS,
350	EFX_MAC_RX_PKTS,
351	EFX_MAC_RX_UNICST_PKTS,
352	EFX_MAC_RX_MULTICST_PKTS,
353	EFX_MAC_RX_BRDCST_PKTS,
354	EFX_MAC_RX_PAUSE_PKTS,
355	EFX_MAC_RX_LE_64_PKTS,
356	EFX_MAC_RX_65_TO_127_PKTS,
357	EFX_MAC_RX_128_TO_255_PKTS,
358	EFX_MAC_RX_256_TO_511_PKTS,
359	EFX_MAC_RX_512_TO_1023_PKTS,
360	EFX_MAC_RX_1024_TO_15XX_PKTS,
361	EFX_MAC_RX_GE_15XX_PKTS,
362	EFX_MAC_RX_ERRORS,
363	EFX_MAC_RX_FCS_ERRORS,
364	EFX_MAC_RX_DROP_EVENTS,
365	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
366	EFX_MAC_RX_SYMBOL_ERRORS,
367	EFX_MAC_RX_ALIGN_ERRORS,
368	EFX_MAC_RX_INTERNAL_ERRORS,
369	EFX_MAC_RX_JABBER_PKTS,
370	EFX_MAC_RX_LANE0_CHAR_ERR,
371	EFX_MAC_RX_LANE1_CHAR_ERR,
372	EFX_MAC_RX_LANE2_CHAR_ERR,
373	EFX_MAC_RX_LANE3_CHAR_ERR,
374	EFX_MAC_RX_LANE0_DISP_ERR,
375	EFX_MAC_RX_LANE1_DISP_ERR,
376	EFX_MAC_RX_LANE2_DISP_ERR,
377	EFX_MAC_RX_LANE3_DISP_ERR,
378	EFX_MAC_RX_MATCH_FAULT,
379	EFX_MAC_RX_NODESC_DROP_CNT,
380	EFX_MAC_TX_OCTETS,
381	EFX_MAC_TX_PKTS,
382	EFX_MAC_TX_UNICST_PKTS,
383	EFX_MAC_TX_MULTICST_PKTS,
384	EFX_MAC_TX_BRDCST_PKTS,
385	EFX_MAC_TX_PAUSE_PKTS,
386	EFX_MAC_TX_LE_64_PKTS,
387	EFX_MAC_TX_65_TO_127_PKTS,
388	EFX_MAC_TX_128_TO_255_PKTS,
389	EFX_MAC_TX_256_TO_511_PKTS,
390	EFX_MAC_TX_512_TO_1023_PKTS,
391	EFX_MAC_TX_1024_TO_15XX_PKTS,
392	EFX_MAC_TX_GE_15XX_PKTS,
393	EFX_MAC_TX_ERRORS,
394	EFX_MAC_TX_SGL_COL_PKTS,
395	EFX_MAC_TX_MULT_COL_PKTS,
396	EFX_MAC_TX_EX_COL_PKTS,
397	EFX_MAC_TX_LATE_COL_PKTS,
398	EFX_MAC_TX_DEF_PKTS,
399	EFX_MAC_TX_EX_DEF_PKTS,
400	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
401	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
402	EFX_MAC_PM_TRUNC_VFIFO_FULL,
403	EFX_MAC_PM_DISCARD_VFIFO_FULL,
404	EFX_MAC_PM_TRUNC_QBB,
405	EFX_MAC_PM_DISCARD_QBB,
406	EFX_MAC_PM_DISCARD_MAPPING,
407	EFX_MAC_RXDP_Q_DISABLED_PKTS,
408	EFX_MAC_RXDP_DI_DROPPED_PKTS,
409	EFX_MAC_RXDP_STREAMING_PKTS,
410	EFX_MAC_RXDP_HLB_FETCH,
411	EFX_MAC_RXDP_HLB_WAIT,
412	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
413	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
414	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
415	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
416	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
417	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
418	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
419	EFX_MAC_VADAPTER_RX_BAD_BYTES,
420	EFX_MAC_VADAPTER_RX_OVERFLOW,
421	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
422	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
423	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
424	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
425	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
426	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
427	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
428	EFX_MAC_VADAPTER_TX_BAD_BYTES,
429	EFX_MAC_VADAPTER_TX_OVERFLOW,
430	EFX_MAC_NSTATS
431} efx_mac_stat_t;
432
433/* END MKCONFIG GENERATED EfxHeaderMacBlock */
434
435#endif	/* EFSYS_OPT_MAC_STATS */
436
437typedef enum efx_link_mode_e {
438	EFX_LINK_UNKNOWN = 0,
439	EFX_LINK_DOWN,
440	EFX_LINK_10HDX,
441	EFX_LINK_10FDX,
442	EFX_LINK_100HDX,
443	EFX_LINK_100FDX,
444	EFX_LINK_1000HDX,
445	EFX_LINK_1000FDX,
446	EFX_LINK_10000FDX,
447	EFX_LINK_40000FDX,
448	EFX_LINK_NMODES
449} efx_link_mode_t;
450
451#define	EFX_MAC_ADDR_LEN 6
452
453#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t *)_address)[0] & 0x01)
454
455#define	EFX_MAC_MULTICAST_LIST_MAX	256
456
457#define	EFX_MAC_SDU_MAX	9202
458
459#define	EFX_MAC_PDU_ADJUSTMENT					\
460	(/* EtherII */ 14					\
461	    + /* VLAN */ 4					\
462	    + /* CRC */ 4					\
463	    + /* bug16011 */ 16)				\
464
465#define	EFX_MAC_PDU(_sdu)					\
466	EFX_P2ROUNDUP(size_t, (_sdu) + EFX_MAC_PDU_ADJUSTMENT, 8)
467
468/*
469 * Due to the EFX_P2ROUNDUP in EFX_MAC_PDU(), EFX_MAC_SDU_FROM_PDU() may give
470 * the SDU rounded up slightly.
471 */
472#define	EFX_MAC_SDU_FROM_PDU(_pdu)	((_pdu) - EFX_MAC_PDU_ADJUSTMENT)
473
474#define	EFX_MAC_PDU_MIN	60
475#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
476
477extern	__checkReturn	efx_rc_t
478efx_mac_pdu_get(
479	__in		efx_nic_t *enp,
480	__out		size_t *pdu);
481
482extern	__checkReturn	efx_rc_t
483efx_mac_pdu_set(
484	__in		efx_nic_t *enp,
485	__in		size_t pdu);
486
487extern	__checkReturn	efx_rc_t
488efx_mac_addr_set(
489	__in		efx_nic_t *enp,
490	__in		uint8_t *addr);
491
492extern	__checkReturn			efx_rc_t
493efx_mac_filter_set(
494	__in				efx_nic_t *enp,
495	__in				boolean_t all_unicst,
496	__in				boolean_t mulcst,
497	__in				boolean_t all_mulcst,
498	__in				boolean_t brdcst);
499
500extern	__checkReturn	efx_rc_t
501efx_mac_multicast_list_set(
502	__in				efx_nic_t *enp,
503	__in_ecount(6*count)		uint8_t const *addrs,
504	__in				int count);
505
506extern	__checkReturn	efx_rc_t
507efx_mac_filter_default_rxq_set(
508	__in		efx_nic_t *enp,
509	__in		efx_rxq_t *erp,
510	__in		boolean_t using_rss);
511
512extern			void
513efx_mac_filter_default_rxq_clear(
514	__in		efx_nic_t *enp);
515
516extern	__checkReturn	efx_rc_t
517efx_mac_drain(
518	__in		efx_nic_t *enp,
519	__in		boolean_t enabled);
520
521extern	__checkReturn	efx_rc_t
522efx_mac_up(
523	__in		efx_nic_t *enp,
524	__out		boolean_t *mac_upp);
525
526#define	EFX_FCNTL_RESPOND	0x00000001
527#define	EFX_FCNTL_GENERATE	0x00000002
528
529extern	__checkReturn	efx_rc_t
530efx_mac_fcntl_set(
531	__in		efx_nic_t *enp,
532	__in		unsigned int fcntl,
533	__in		boolean_t autoneg);
534
535extern			void
536efx_mac_fcntl_get(
537	__in		efx_nic_t *enp,
538	__out		unsigned int *fcntl_wantedp,
539	__out		unsigned int *fcntl_linkp);
540
541
542#if EFSYS_OPT_MAC_STATS
543
544#if EFSYS_OPT_NAMES
545
546extern	__checkReturn			const char *
547efx_mac_stat_name(
548	__in				efx_nic_t *enp,
549	__in				unsigned int id);
550
551#endif	/* EFSYS_OPT_NAMES */
552
553#define	EFX_MAC_STATS_MASK_BITS_PER_PAGE	(8 * sizeof (uint32_t))
554
555#define	EFX_MAC_STATS_MASK_NPAGES				\
556	(EFX_P2ROUNDUP(uint32_t, EFX_MAC_NSTATS,		\
557		       EFX_MAC_STATS_MASK_BITS_PER_PAGE) /	\
558	    EFX_MAC_STATS_MASK_BITS_PER_PAGE)
559
560/*
561 * Get mask of MAC statistics supported by the hardware.
562 *
563 * If mask_size is insufficient to return the mask, EINVAL error is
564 * returned. EFX_MAC_STATS_MASK_NPAGES multiplied by size of the page
565 * (which is sizeof (uint32_t)) is sufficient.
566 */
567extern	__checkReturn			efx_rc_t
568efx_mac_stats_get_mask(
569	__in				efx_nic_t *enp,
570	__out_bcount(mask_size)		uint32_t *maskp,
571	__in				size_t mask_size);
572
573#define	EFX_MAC_STAT_SUPPORTED(_mask, _stat)	\
574	((_mask)[(_stat) / EFX_MAC_STATS_MASK_BITS_PER_PAGE] &	\
575	 (1ULL << ((_stat) & (EFX_MAC_STATS_MASK_BITS_PER_PAGE - 1))))
576
577#define	EFX_MAC_STATS_SIZE 0x400
578
579/*
580 * Upload mac statistics supported by the hardware into the given buffer.
581 *
582 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
583 * and page aligned.
584 *
585 * The hardware will only DMA statistics that it understands (of course).
586 * Drivers should not make any assumptions about which statistics are
587 * supported, especially when the statistics are generated by firmware.
588 *
589 * Thus, drivers should zero this buffer before use, so that not-understood
590 * statistics read back as zero.
591 */
592extern	__checkReturn			efx_rc_t
593efx_mac_stats_upload(
594	__in				efx_nic_t *enp,
595	__in				efsys_mem_t *esmp);
596
597extern	__checkReturn			efx_rc_t
598efx_mac_stats_periodic(
599	__in				efx_nic_t *enp,
600	__in				efsys_mem_t *esmp,
601	__in				uint16_t period_ms,
602	__in				boolean_t events);
603
604extern	__checkReturn			efx_rc_t
605efx_mac_stats_update(
606	__in				efx_nic_t *enp,
607	__in				efsys_mem_t *esmp,
608	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
609	__inout_opt			uint32_t *generationp);
610
611#endif	/* EFSYS_OPT_MAC_STATS */
612
613/* MON */
614
615typedef enum efx_mon_type_e {
616	EFX_MON_INVALID = 0,
617	EFX_MON_SFC90X0,
618	EFX_MON_SFC91X0,
619	EFX_MON_SFC92X0,
620	EFX_MON_NTYPES
621} efx_mon_type_t;
622
623#if EFSYS_OPT_NAMES
624
625extern		const char *
626efx_mon_name(
627	__in	efx_nic_t *enp);
628
629#endif	/* EFSYS_OPT_NAMES */
630
631extern	__checkReturn	efx_rc_t
632efx_mon_init(
633	__in		efx_nic_t *enp);
634
635#if EFSYS_OPT_MON_STATS
636
637#define	EFX_MON_STATS_PAGE_SIZE 0x100
638#define	EFX_MON_MASK_ELEMENT_SIZE 32
639
640/* START MKCONFIG GENERATED MonitorHeaderStatsBlock 5d4ee5185e419abe */
641typedef enum efx_mon_stat_e {
642	EFX_MON_STAT_2_5V,
643	EFX_MON_STAT_VCCP1,
644	EFX_MON_STAT_VCC,
645	EFX_MON_STAT_5V,
646	EFX_MON_STAT_12V,
647	EFX_MON_STAT_VCCP2,
648	EFX_MON_STAT_EXT_TEMP,
649	EFX_MON_STAT_INT_TEMP,
650	EFX_MON_STAT_AIN1,
651	EFX_MON_STAT_AIN2,
652	EFX_MON_STAT_INT_COOLING,
653	EFX_MON_STAT_EXT_COOLING,
654	EFX_MON_STAT_1V,
655	EFX_MON_STAT_1_2V,
656	EFX_MON_STAT_1_8V,
657	EFX_MON_STAT_3_3V,
658	EFX_MON_STAT_1_2VA,
659	EFX_MON_STAT_VREF,
660	EFX_MON_STAT_VAOE,
661	EFX_MON_STAT_AOE_TEMP,
662	EFX_MON_STAT_PSU_AOE_TEMP,
663	EFX_MON_STAT_PSU_TEMP,
664	EFX_MON_STAT_FAN0,
665	EFX_MON_STAT_FAN1,
666	EFX_MON_STAT_FAN2,
667	EFX_MON_STAT_FAN3,
668	EFX_MON_STAT_FAN4,
669	EFX_MON_STAT_VAOE_IN,
670	EFX_MON_STAT_IAOE,
671	EFX_MON_STAT_IAOE_IN,
672	EFX_MON_STAT_NIC_POWER,
673	EFX_MON_STAT_0_9V,
674	EFX_MON_STAT_I0_9V,
675	EFX_MON_STAT_I1_2V,
676	EFX_MON_STAT_0_9V_ADC,
677	EFX_MON_STAT_INT_TEMP2,
678	EFX_MON_STAT_VREG_TEMP,
679	EFX_MON_STAT_VREG_0_9V_TEMP,
680	EFX_MON_STAT_VREG_1_2V_TEMP,
681	EFX_MON_STAT_INT_VPTAT,
682	EFX_MON_STAT_INT_ADC_TEMP,
683	EFX_MON_STAT_EXT_VPTAT,
684	EFX_MON_STAT_EXT_ADC_TEMP,
685	EFX_MON_STAT_AMBIENT_TEMP,
686	EFX_MON_STAT_AIRFLOW,
687	EFX_MON_STAT_VDD08D_VSS08D_CSR,
688	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
689	EFX_MON_STAT_HOTPOINT_TEMP,
690	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
691	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
692	EFX_MON_STAT_MUM_VCC,
693	EFX_MON_STAT_0V9_A,
694	EFX_MON_STAT_I0V9_A,
695	EFX_MON_STAT_0V9_A_TEMP,
696	EFX_MON_STAT_0V9_B,
697	EFX_MON_STAT_I0V9_B,
698	EFX_MON_STAT_0V9_B_TEMP,
699	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
700	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
701	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
702	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
703	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
704	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
705	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
706	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
707	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
708	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
709	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
710	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
711	EFX_MON_STAT_SODIMM_VOUT,
712	EFX_MON_STAT_SODIMM_0_TEMP,
713	EFX_MON_STAT_SODIMM_1_TEMP,
714	EFX_MON_STAT_PHY0_VCC,
715	EFX_MON_STAT_PHY1_VCC,
716	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
717	EFX_MON_STAT_BOARD_FRONT_TEMP,
718	EFX_MON_STAT_BOARD_BACK_TEMP,
719	EFX_MON_NSTATS
720} efx_mon_stat_t;
721
722/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
723
724typedef enum efx_mon_stat_state_e {
725	EFX_MON_STAT_STATE_OK = 0,
726	EFX_MON_STAT_STATE_WARNING = 1,
727	EFX_MON_STAT_STATE_FATAL = 2,
728	EFX_MON_STAT_STATE_BROKEN = 3,
729	EFX_MON_STAT_STATE_NO_READING = 4,
730} efx_mon_stat_state_t;
731
732typedef struct efx_mon_stat_value_s {
733	uint16_t	emsv_value;
734	uint16_t	emsv_state;
735} efx_mon_stat_value_t;
736
737#if EFSYS_OPT_NAMES
738
739extern					const char *
740efx_mon_stat_name(
741	__in				efx_nic_t *enp,
742	__in				efx_mon_stat_t id);
743
744#endif	/* EFSYS_OPT_NAMES */
745
746extern	__checkReturn			efx_rc_t
747efx_mon_stats_update(
748	__in				efx_nic_t *enp,
749	__in				efsys_mem_t *esmp,
750	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
751
752#endif	/* EFSYS_OPT_MON_STATS */
753
754extern		void
755efx_mon_fini(
756	__in	efx_nic_t *enp);
757
758/* PHY */
759
760extern	__checkReturn	efx_rc_t
761efx_phy_verify(
762	__in		efx_nic_t *enp);
763
764#if EFSYS_OPT_PHY_LED_CONTROL
765
766typedef enum efx_phy_led_mode_e {
767	EFX_PHY_LED_DEFAULT = 0,
768	EFX_PHY_LED_OFF,
769	EFX_PHY_LED_ON,
770	EFX_PHY_LED_FLASH,
771	EFX_PHY_LED_NMODES
772} efx_phy_led_mode_t;
773
774extern	__checkReturn	efx_rc_t
775efx_phy_led_set(
776	__in	efx_nic_t *enp,
777	__in	efx_phy_led_mode_t mode);
778
779#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
780
781extern	__checkReturn	efx_rc_t
782efx_port_init(
783	__in		efx_nic_t *enp);
784
785#if EFSYS_OPT_LOOPBACK
786
787typedef enum efx_loopback_type_e {
788	EFX_LOOPBACK_OFF = 0,
789	EFX_LOOPBACK_DATA = 1,
790	EFX_LOOPBACK_GMAC = 2,
791	EFX_LOOPBACK_XGMII = 3,
792	EFX_LOOPBACK_XGXS = 4,
793	EFX_LOOPBACK_XAUI = 5,
794	EFX_LOOPBACK_GMII = 6,
795	EFX_LOOPBACK_SGMII = 7,
796	EFX_LOOPBACK_XGBR = 8,
797	EFX_LOOPBACK_XFI = 9,
798	EFX_LOOPBACK_XAUI_FAR = 10,
799	EFX_LOOPBACK_GMII_FAR = 11,
800	EFX_LOOPBACK_SGMII_FAR = 12,
801	EFX_LOOPBACK_XFI_FAR = 13,
802	EFX_LOOPBACK_GPHY = 14,
803	EFX_LOOPBACK_PHY_XS = 15,
804	EFX_LOOPBACK_PCS = 16,
805	EFX_LOOPBACK_PMA_PMD = 17,
806	EFX_LOOPBACK_XPORT = 18,
807	EFX_LOOPBACK_XGMII_WS = 19,
808	EFX_LOOPBACK_XAUI_WS = 20,
809	EFX_LOOPBACK_XAUI_WS_FAR = 21,
810	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
811	EFX_LOOPBACK_GMII_WS = 23,
812	EFX_LOOPBACK_XFI_WS = 24,
813	EFX_LOOPBACK_XFI_WS_FAR = 25,
814	EFX_LOOPBACK_PHYXS_WS = 26,
815	EFX_LOOPBACK_PMA_INT = 27,
816	EFX_LOOPBACK_SD_NEAR = 28,
817	EFX_LOOPBACK_SD_FAR = 29,
818	EFX_LOOPBACK_PMA_INT_WS = 30,
819	EFX_LOOPBACK_SD_FEP2_WS = 31,
820	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
821	EFX_LOOPBACK_SD_FEP_WS = 33,
822	EFX_LOOPBACK_SD_FES_WS = 34,
823	EFX_LOOPBACK_NTYPES
824} efx_loopback_type_t;
825
826typedef enum efx_loopback_kind_e {
827	EFX_LOOPBACK_KIND_OFF = 0,
828	EFX_LOOPBACK_KIND_ALL,
829	EFX_LOOPBACK_KIND_MAC,
830	EFX_LOOPBACK_KIND_PHY,
831	EFX_LOOPBACK_NKINDS
832} efx_loopback_kind_t;
833
834extern			void
835efx_loopback_mask(
836	__in	efx_loopback_kind_t loopback_kind,
837	__out	efx_qword_t *maskp);
838
839extern	__checkReturn	efx_rc_t
840efx_port_loopback_set(
841	__in	efx_nic_t *enp,
842	__in	efx_link_mode_t link_mode,
843	__in	efx_loopback_type_t type);
844
845#if EFSYS_OPT_NAMES
846
847extern	__checkReturn	const char *
848efx_loopback_type_name(
849	__in		efx_nic_t *enp,
850	__in		efx_loopback_type_t type);
851
852#endif	/* EFSYS_OPT_NAMES */
853
854#endif	/* EFSYS_OPT_LOOPBACK */
855
856extern	__checkReturn	efx_rc_t
857efx_port_poll(
858	__in		efx_nic_t *enp,
859	__out_opt	efx_link_mode_t	*link_modep);
860
861extern		void
862efx_port_fini(
863	__in	efx_nic_t *enp);
864
865typedef enum efx_phy_cap_type_e {
866	EFX_PHY_CAP_INVALID = 0,
867	EFX_PHY_CAP_10HDX,
868	EFX_PHY_CAP_10FDX,
869	EFX_PHY_CAP_100HDX,
870	EFX_PHY_CAP_100FDX,
871	EFX_PHY_CAP_1000HDX,
872	EFX_PHY_CAP_1000FDX,
873	EFX_PHY_CAP_10000FDX,
874	EFX_PHY_CAP_PAUSE,
875	EFX_PHY_CAP_ASYM,
876	EFX_PHY_CAP_AN,
877	EFX_PHY_CAP_40000FDX,
878	EFX_PHY_CAP_NTYPES
879} efx_phy_cap_type_t;
880
881
882#define	EFX_PHY_CAP_CURRENT	0x00000000
883#define	EFX_PHY_CAP_DEFAULT	0x00000001
884#define	EFX_PHY_CAP_PERM	0x00000002
885
886extern		void
887efx_phy_adv_cap_get(
888	__in		efx_nic_t *enp,
889	__in		uint32_t flag,
890	__out		uint32_t *maskp);
891
892extern	__checkReturn	efx_rc_t
893efx_phy_adv_cap_set(
894	__in		efx_nic_t *enp,
895	__in		uint32_t mask);
896
897extern			void
898efx_phy_lp_cap_get(
899	__in		efx_nic_t *enp,
900	__out		uint32_t *maskp);
901
902extern	__checkReturn	efx_rc_t
903efx_phy_oui_get(
904	__in		efx_nic_t *enp,
905	__out		uint32_t *ouip);
906
907typedef enum efx_phy_media_type_e {
908	EFX_PHY_MEDIA_INVALID = 0,
909	EFX_PHY_MEDIA_XAUI,
910	EFX_PHY_MEDIA_CX4,
911	EFX_PHY_MEDIA_KX4,
912	EFX_PHY_MEDIA_XFP,
913	EFX_PHY_MEDIA_SFP_PLUS,
914	EFX_PHY_MEDIA_BASE_T,
915	EFX_PHY_MEDIA_QSFP_PLUS,
916	EFX_PHY_MEDIA_NTYPES
917} efx_phy_media_type_t;
918
919/* Get the type of medium currently used.  If the board has ports for
920 * modules, a module is present, and we recognise the media type of
921 * the module, then this will be the media type of the module.
922 * Otherwise it will be the media type of the port.
923 */
924extern			void
925efx_phy_media_type_get(
926	__in		efx_nic_t *enp,
927	__out		efx_phy_media_type_t *typep);
928
929extern	__checkReturn		efx_rc_t
930efx_phy_module_get_info(
931	__in			efx_nic_t *enp,
932	__in			uint8_t dev_addr,
933	__in			uint8_t offset,
934	__in			uint8_t len,
935	__out_bcount(len)	uint8_t *data);
936
937#if EFSYS_OPT_PHY_STATS
938
939/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
940typedef enum efx_phy_stat_e {
941	EFX_PHY_STAT_OUI,
942	EFX_PHY_STAT_PMA_PMD_LINK_UP,
943	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
944	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
945	EFX_PHY_STAT_PMA_PMD_REV_A,
946	EFX_PHY_STAT_PMA_PMD_REV_B,
947	EFX_PHY_STAT_PMA_PMD_REV_C,
948	EFX_PHY_STAT_PMA_PMD_REV_D,
949	EFX_PHY_STAT_PCS_LINK_UP,
950	EFX_PHY_STAT_PCS_RX_FAULT,
951	EFX_PHY_STAT_PCS_TX_FAULT,
952	EFX_PHY_STAT_PCS_BER,
953	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
954	EFX_PHY_STAT_PHY_XS_LINK_UP,
955	EFX_PHY_STAT_PHY_XS_RX_FAULT,
956	EFX_PHY_STAT_PHY_XS_TX_FAULT,
957	EFX_PHY_STAT_PHY_XS_ALIGN,
958	EFX_PHY_STAT_PHY_XS_SYNC_A,
959	EFX_PHY_STAT_PHY_XS_SYNC_B,
960	EFX_PHY_STAT_PHY_XS_SYNC_C,
961	EFX_PHY_STAT_PHY_XS_SYNC_D,
962	EFX_PHY_STAT_AN_LINK_UP,
963	EFX_PHY_STAT_AN_MASTER,
964	EFX_PHY_STAT_AN_LOCAL_RX_OK,
965	EFX_PHY_STAT_AN_REMOTE_RX_OK,
966	EFX_PHY_STAT_CL22EXT_LINK_UP,
967	EFX_PHY_STAT_SNR_A,
968	EFX_PHY_STAT_SNR_B,
969	EFX_PHY_STAT_SNR_C,
970	EFX_PHY_STAT_SNR_D,
971	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
972	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
973	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
974	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
975	EFX_PHY_STAT_AN_COMPLETE,
976	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
977	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
978	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
979	EFX_PHY_STAT_PCS_FW_VERSION_0,
980	EFX_PHY_STAT_PCS_FW_VERSION_1,
981	EFX_PHY_STAT_PCS_FW_VERSION_2,
982	EFX_PHY_STAT_PCS_FW_VERSION_3,
983	EFX_PHY_STAT_PCS_FW_BUILD_YY,
984	EFX_PHY_STAT_PCS_FW_BUILD_MM,
985	EFX_PHY_STAT_PCS_FW_BUILD_DD,
986	EFX_PHY_STAT_PCS_OP_MODE,
987	EFX_PHY_NSTATS
988} efx_phy_stat_t;
989
990/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
991
992#if EFSYS_OPT_NAMES
993
994extern					const char *
995efx_phy_stat_name(
996	__in				efx_nic_t *enp,
997	__in				efx_phy_stat_t stat);
998
999#endif	/* EFSYS_OPT_NAMES */
1000
1001#define	EFX_PHY_STATS_SIZE 0x100
1002
1003extern	__checkReturn			efx_rc_t
1004efx_phy_stats_update(
1005	__in				efx_nic_t *enp,
1006	__in				efsys_mem_t *esmp,
1007	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
1008
1009#endif	/* EFSYS_OPT_PHY_STATS */
1010
1011
1012#if EFSYS_OPT_BIST
1013
1014typedef enum efx_bist_type_e {
1015	EFX_BIST_TYPE_UNKNOWN,
1016	EFX_BIST_TYPE_PHY_NORMAL,
1017	EFX_BIST_TYPE_PHY_CABLE_SHORT,
1018	EFX_BIST_TYPE_PHY_CABLE_LONG,
1019	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
1020	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
1021	EFX_BIST_TYPE_REG,	/* Test the register memories */
1022	EFX_BIST_TYPE_NTYPES,
1023} efx_bist_type_t;
1024
1025typedef enum efx_bist_result_e {
1026	EFX_BIST_RESULT_UNKNOWN,
1027	EFX_BIST_RESULT_RUNNING,
1028	EFX_BIST_RESULT_PASSED,
1029	EFX_BIST_RESULT_FAILED,
1030} efx_bist_result_t;
1031
1032typedef enum efx_phy_cable_status_e {
1033	EFX_PHY_CABLE_STATUS_OK,
1034	EFX_PHY_CABLE_STATUS_INVALID,
1035	EFX_PHY_CABLE_STATUS_OPEN,
1036	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1037	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1038	EFX_PHY_CABLE_STATUS_BUSY,
1039} efx_phy_cable_status_t;
1040
1041typedef enum efx_bist_value_e {
1042	EFX_BIST_PHY_CABLE_LENGTH_A,
1043	EFX_BIST_PHY_CABLE_LENGTH_B,
1044	EFX_BIST_PHY_CABLE_LENGTH_C,
1045	EFX_BIST_PHY_CABLE_LENGTH_D,
1046	EFX_BIST_PHY_CABLE_STATUS_A,
1047	EFX_BIST_PHY_CABLE_STATUS_B,
1048	EFX_BIST_PHY_CABLE_STATUS_C,
1049	EFX_BIST_PHY_CABLE_STATUS_D,
1050	EFX_BIST_FAULT_CODE,
1051	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1052	 * response. */
1053	EFX_BIST_MEM_TEST,
1054	EFX_BIST_MEM_ADDR,
1055	EFX_BIST_MEM_BUS,
1056	EFX_BIST_MEM_EXPECT,
1057	EFX_BIST_MEM_ACTUAL,
1058	EFX_BIST_MEM_ECC,
1059	EFX_BIST_MEM_ECC_PARITY,
1060	EFX_BIST_MEM_ECC_FATAL,
1061	EFX_BIST_NVALUES,
1062} efx_bist_value_t;
1063
1064extern	__checkReturn		efx_rc_t
1065efx_bist_enable_offline(
1066	__in			efx_nic_t *enp);
1067
1068extern	__checkReturn		efx_rc_t
1069efx_bist_start(
1070	__in			efx_nic_t *enp,
1071	__in			efx_bist_type_t type);
1072
1073extern	__checkReturn		efx_rc_t
1074efx_bist_poll(
1075	__in			efx_nic_t *enp,
1076	__in			efx_bist_type_t type,
1077	__out			efx_bist_result_t *resultp,
1078	__out_opt		uint32_t *value_maskp,
1079	__out_ecount_opt(count)	unsigned long *valuesp,
1080	__in			size_t count);
1081
1082extern				void
1083efx_bist_stop(
1084	__in			efx_nic_t *enp,
1085	__in			efx_bist_type_t type);
1086
1087#endif	/* EFSYS_OPT_BIST */
1088
1089#define	EFX_FEATURE_IPV6		0x00000001
1090#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1091#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1092#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1093#define	EFX_FEATURE_MCDI		0x00000020
1094#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1095#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1096#define	EFX_FEATURE_TURBO		0x00000100
1097#define	EFX_FEATURE_MCDI_DMA		0x00000200
1098#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1099#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1100#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1101#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1102#define	EFX_FEATURE_TXQ_CKSUM_OP_DESC	0x00008000
1103
1104typedef enum efx_tunnel_protocol_e {
1105	EFX_TUNNEL_PROTOCOL_NONE = 0,
1106	EFX_TUNNEL_PROTOCOL_VXLAN,
1107	EFX_TUNNEL_PROTOCOL_GENEVE,
1108	EFX_TUNNEL_PROTOCOL_NVGRE,
1109	EFX_TUNNEL_NPROTOS
1110} efx_tunnel_protocol_t;
1111
1112typedef struct efx_nic_cfg_s {
1113	uint32_t		enc_board_type;
1114	uint32_t		enc_phy_type;
1115#if EFSYS_OPT_NAMES
1116	char			enc_phy_name[21];
1117#endif
1118	char			enc_phy_revision[21];
1119	efx_mon_type_t		enc_mon_type;
1120#if EFSYS_OPT_MON_STATS
1121	uint32_t		enc_mon_stat_dma_buf_size;
1122	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1123#endif
1124	unsigned int		enc_features;
1125	uint8_t			enc_mac_addr[6];
1126	uint8_t			enc_port;	/* PHY port number */
1127	uint32_t		enc_intr_vec_base;
1128	uint32_t		enc_intr_limit;
1129	uint32_t		enc_evq_limit;
1130	uint32_t		enc_txq_limit;
1131	uint32_t		enc_rxq_limit;
1132	uint32_t		enc_txq_max_ndescs;
1133	uint32_t		enc_buftbl_limit;
1134	uint32_t		enc_piobuf_limit;
1135	uint32_t		enc_piobuf_size;
1136	uint32_t		enc_piobuf_min_alloc_size;
1137	uint32_t		enc_evq_timer_quantum_ns;
1138	uint32_t		enc_evq_timer_max_us;
1139	uint32_t		enc_clk_mult;
1140	uint32_t		enc_rx_prefix_size;
1141	uint32_t		enc_rx_buf_align_start;
1142	uint32_t		enc_rx_buf_align_end;
1143#if EFSYS_OPT_LOOPBACK
1144	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1145#endif	/* EFSYS_OPT_LOOPBACK */
1146#if EFSYS_OPT_PHY_FLAGS
1147	uint32_t		enc_phy_flags_mask;
1148#endif	/* EFSYS_OPT_PHY_FLAGS */
1149#if EFSYS_OPT_PHY_LED_CONTROL
1150	uint32_t		enc_led_mask;
1151#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1152#if EFSYS_OPT_PHY_STATS
1153	uint64_t		enc_phy_stat_mask;
1154#endif	/* EFSYS_OPT_PHY_STATS */
1155#if EFSYS_OPT_MCDI
1156	uint8_t			enc_mcdi_mdio_channel;
1157#if EFSYS_OPT_PHY_STATS
1158	uint32_t		enc_mcdi_phy_stat_mask;
1159#endif	/* EFSYS_OPT_PHY_STATS */
1160#if EFSYS_OPT_MON_STATS
1161	uint32_t		*enc_mcdi_sensor_maskp;
1162	uint32_t		enc_mcdi_sensor_mask_size;
1163#endif	/* EFSYS_OPT_MON_STATS */
1164#endif	/* EFSYS_OPT_MCDI */
1165#if EFSYS_OPT_BIST
1166	uint32_t		enc_bist_mask;
1167#endif	/* EFSYS_OPT_BIST */
1168#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1169	uint32_t		enc_pf;
1170	uint32_t		enc_vf;
1171	uint32_t		enc_privilege_mask;
1172#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1173	boolean_t		enc_bug26807_workaround;
1174	boolean_t		enc_bug35388_workaround;
1175	boolean_t		enc_bug41750_workaround;
1176	boolean_t		enc_bug61265_workaround;
1177	boolean_t		enc_rx_batching_enabled;
1178	/* Maximum number of descriptors completed in an rx event. */
1179	uint32_t		enc_rx_batch_max;
1180	/* Number of rx descriptors the hardware requires for a push. */
1181	uint32_t		enc_rx_push_align;
1182	/* Maximum amount of data in DMA descriptor */
1183	uint32_t		enc_tx_dma_desc_size_max;
1184	/*
1185	 * Boundary which DMA descriptor data must not cross or 0 if no
1186	 * limitation.
1187	 */
1188	uint32_t		enc_tx_dma_desc_boundary;
1189	/*
1190	 * Maximum number of bytes into the packet the TCP header can start for
1191	 * the hardware to apply TSO packet edits.
1192	 */
1193	uint32_t		enc_tx_tso_tcp_header_offset_limit;
1194	boolean_t		enc_fw_assisted_tso_enabled;
1195	boolean_t		enc_fw_assisted_tso_v2_enabled;
1196	/* Number of TSO contexts on the NIC (FATSOv2) */
1197	uint32_t		enc_fw_assisted_tso_v2_n_contexts;
1198	boolean_t		enc_hw_tx_insert_vlan_enabled;
1199	/* Number of PFs on the NIC */
1200	uint32_t		enc_hw_pf_count;
1201	/* Datapath firmware vadapter/vport/vswitch support */
1202	boolean_t		enc_datapath_cap_evb;
1203	boolean_t		enc_rx_disable_scatter_supported;
1204	boolean_t		enc_allow_set_mac_with_installed_filters;
1205	boolean_t		enc_enhanced_set_mac_supported;
1206	boolean_t		enc_init_evq_v2_supported;
1207	boolean_t		enc_pm_and_rxdp_counters;
1208	boolean_t		enc_mac_stats_40g_tx_size_bins;
1209	uint32_t		enc_tunnel_encapsulations_supported;
1210	/* External port identifier */
1211	uint8_t			enc_external_port;
1212	uint32_t		enc_mcdi_max_payload_length;
1213	/* VPD may be per-PF or global */
1214	boolean_t		enc_vpd_is_global;
1215	/* Minimum unidirectional bandwidth in Mb/s to max out all ports */
1216	uint32_t		enc_required_pcie_bandwidth_mbps;
1217	uint32_t		enc_max_pcie_link_gen;
1218	/* Firmware verifies integrity of NVRAM updates */
1219	uint32_t		enc_fw_verified_nvram_update_required;
1220} efx_nic_cfg_t;
1221
1222#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1223#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1224
1225#define	EFX_PCI_FUNCTION(_encp)	\
1226	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1227
1228#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1229
1230extern			const efx_nic_cfg_t *
1231efx_nic_cfg_get(
1232	__in		efx_nic_t *enp);
1233
1234/* Driver resource limits (minimum required/maximum usable). */
1235typedef struct efx_drv_limits_s {
1236	uint32_t	edl_min_evq_count;
1237	uint32_t	edl_max_evq_count;
1238
1239	uint32_t	edl_min_rxq_count;
1240	uint32_t	edl_max_rxq_count;
1241
1242	uint32_t	edl_min_txq_count;
1243	uint32_t	edl_max_txq_count;
1244
1245	/* PIO blocks (sub-allocated from piobuf) */
1246	uint32_t	edl_min_pio_alloc_size;
1247	uint32_t	edl_max_pio_alloc_count;
1248} efx_drv_limits_t;
1249
1250extern	__checkReturn	efx_rc_t
1251efx_nic_set_drv_limits(
1252	__inout		efx_nic_t *enp,
1253	__in		efx_drv_limits_t *edlp);
1254
1255typedef enum efx_nic_region_e {
1256	EFX_REGION_VI,			/* Memory BAR UC mapping */
1257	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1258} efx_nic_region_t;
1259
1260extern	__checkReturn	efx_rc_t
1261efx_nic_get_bar_region(
1262	__in		efx_nic_t *enp,
1263	__in		efx_nic_region_t region,
1264	__out		uint32_t *offsetp,
1265	__out		size_t *sizep);
1266
1267extern	__checkReturn	efx_rc_t
1268efx_nic_get_vi_pool(
1269	__in		efx_nic_t *enp,
1270	__out		uint32_t *evq_countp,
1271	__out		uint32_t *rxq_countp,
1272	__out		uint32_t *txq_countp);
1273
1274
1275#if EFSYS_OPT_VPD
1276
1277typedef enum efx_vpd_tag_e {
1278	EFX_VPD_ID = 0x02,
1279	EFX_VPD_END = 0x0f,
1280	EFX_VPD_RO = 0x10,
1281	EFX_VPD_RW = 0x11,
1282} efx_vpd_tag_t;
1283
1284typedef uint16_t efx_vpd_keyword_t;
1285
1286typedef struct efx_vpd_value_s {
1287	efx_vpd_tag_t		evv_tag;
1288	efx_vpd_keyword_t	evv_keyword;
1289	uint8_t			evv_length;
1290	uint8_t			evv_value[0x100];
1291} efx_vpd_value_t;
1292
1293
1294#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1295
1296extern	__checkReturn		efx_rc_t
1297efx_vpd_init(
1298	__in			efx_nic_t *enp);
1299
1300extern	__checkReturn		efx_rc_t
1301efx_vpd_size(
1302	__in			efx_nic_t *enp,
1303	__out			size_t *sizep);
1304
1305extern	__checkReturn		efx_rc_t
1306efx_vpd_read(
1307	__in			efx_nic_t *enp,
1308	__out_bcount(size)	caddr_t data,
1309	__in			size_t size);
1310
1311extern	__checkReturn		efx_rc_t
1312efx_vpd_verify(
1313	__in			efx_nic_t *enp,
1314	__in_bcount(size)	caddr_t data,
1315	__in			size_t size);
1316
1317extern	__checkReturn		efx_rc_t
1318efx_vpd_reinit(
1319	__in			efx_nic_t *enp,
1320	__in_bcount(size)	caddr_t data,
1321	__in			size_t size);
1322
1323extern	__checkReturn		efx_rc_t
1324efx_vpd_get(
1325	__in			efx_nic_t *enp,
1326	__in_bcount(size)	caddr_t data,
1327	__in			size_t size,
1328	__inout			efx_vpd_value_t *evvp);
1329
1330extern	__checkReturn		efx_rc_t
1331efx_vpd_set(
1332	__in			efx_nic_t *enp,
1333	__inout_bcount(size)	caddr_t data,
1334	__in			size_t size,
1335	__in			efx_vpd_value_t *evvp);
1336
1337extern	__checkReturn		efx_rc_t
1338efx_vpd_next(
1339	__in			efx_nic_t *enp,
1340	__inout_bcount(size)	caddr_t data,
1341	__in			size_t size,
1342	__out			efx_vpd_value_t *evvp,
1343	__inout			unsigned int *contp);
1344
1345extern	__checkReturn		efx_rc_t
1346efx_vpd_write(
1347	__in			efx_nic_t *enp,
1348	__in_bcount(size)	caddr_t data,
1349	__in			size_t size);
1350
1351extern				void
1352efx_vpd_fini(
1353	__in			efx_nic_t *enp);
1354
1355#endif	/* EFSYS_OPT_VPD */
1356
1357/* NVRAM */
1358
1359#if EFSYS_OPT_NVRAM
1360
1361typedef enum efx_nvram_type_e {
1362	EFX_NVRAM_INVALID = 0,
1363	EFX_NVRAM_BOOTROM,
1364	EFX_NVRAM_BOOTROM_CFG,
1365	EFX_NVRAM_MC_FIRMWARE,
1366	EFX_NVRAM_MC_GOLDEN,
1367	EFX_NVRAM_PHY,
1368	EFX_NVRAM_NULLPHY,
1369	EFX_NVRAM_FPGA,
1370	EFX_NVRAM_FCFW,
1371	EFX_NVRAM_CPLD,
1372	EFX_NVRAM_FPGA_BACKUP,
1373	EFX_NVRAM_DYNAMIC_CFG,
1374	EFX_NVRAM_LICENSE,
1375	EFX_NVRAM_UEFIROM,
1376	EFX_NVRAM_NTYPES,
1377} efx_nvram_type_t;
1378
1379extern	__checkReturn		efx_rc_t
1380efx_nvram_init(
1381	__in			efx_nic_t *enp);
1382
1383#if EFSYS_OPT_DIAG
1384
1385extern	__checkReturn		efx_rc_t
1386efx_nvram_test(
1387	__in			efx_nic_t *enp);
1388
1389#endif	/* EFSYS_OPT_DIAG */
1390
1391extern	__checkReturn		efx_rc_t
1392efx_nvram_size(
1393	__in			efx_nic_t *enp,
1394	__in			efx_nvram_type_t type,
1395	__out			size_t *sizep);
1396
1397extern	__checkReturn		efx_rc_t
1398efx_nvram_rw_start(
1399	__in			efx_nic_t *enp,
1400	__in			efx_nvram_type_t type,
1401	__out_opt		size_t *pref_chunkp);
1402
1403extern	__checkReturn		efx_rc_t
1404efx_nvram_rw_finish(
1405	__in			efx_nic_t *enp,
1406	__in			efx_nvram_type_t type);
1407
1408extern	__checkReturn		efx_rc_t
1409efx_nvram_get_version(
1410	__in			efx_nic_t *enp,
1411	__in			efx_nvram_type_t type,
1412	__out			uint32_t *subtypep,
1413	__out_ecount(4)		uint16_t version[4]);
1414
1415extern	__checkReturn		efx_rc_t
1416efx_nvram_read_chunk(
1417	__in			efx_nic_t *enp,
1418	__in			efx_nvram_type_t type,
1419	__in			unsigned int offset,
1420	__out_bcount(size)	caddr_t data,
1421	__in			size_t size);
1422
1423extern	__checkReturn		efx_rc_t
1424efx_nvram_set_version(
1425	__in			efx_nic_t *enp,
1426	__in			efx_nvram_type_t type,
1427	__in_ecount(4)		uint16_t version[4]);
1428
1429extern	__checkReturn		efx_rc_t
1430efx_nvram_validate(
1431	__in			efx_nic_t *enp,
1432	__in			efx_nvram_type_t type,
1433	__in_bcount(partn_size)	caddr_t partn_data,
1434	__in			size_t partn_size);
1435
1436extern	 __checkReturn		efx_rc_t
1437efx_nvram_erase(
1438	__in			efx_nic_t *enp,
1439	__in			efx_nvram_type_t type);
1440
1441extern	__checkReturn		efx_rc_t
1442efx_nvram_write_chunk(
1443	__in			efx_nic_t *enp,
1444	__in			efx_nvram_type_t type,
1445	__in			unsigned int offset,
1446	__in_bcount(size)	caddr_t data,
1447	__in			size_t size);
1448
1449extern				void
1450efx_nvram_fini(
1451	__in			efx_nic_t *enp);
1452
1453#endif	/* EFSYS_OPT_NVRAM */
1454
1455#if EFSYS_OPT_BOOTCFG
1456
1457/* Report size and offset of bootcfg sector in NVRAM partition. */
1458extern	__checkReturn		efx_rc_t
1459efx_bootcfg_sector_info(
1460	__in			efx_nic_t *enp,
1461	__in			uint32_t pf,
1462	__out_opt		uint32_t *sector_countp,
1463	__out			size_t *offsetp,
1464	__out			size_t *max_sizep);
1465
1466/*
1467 * Copy bootcfg sector data to a target buffer which may differ in size.
1468 * Optionally corrects format errors in source buffer.
1469 */
1470extern				efx_rc_t
1471efx_bootcfg_copy_sector(
1472	__in			efx_nic_t *enp,
1473	__inout_bcount(sector_length)
1474				uint8_t *sector,
1475	__in			size_t sector_length,
1476	__out_bcount(data_size)	uint8_t *data,
1477	__in			size_t data_size,
1478	__in			boolean_t handle_format_errors);
1479
1480extern				efx_rc_t
1481efx_bootcfg_read(
1482	__in			efx_nic_t *enp,
1483	__out_bcount(size)	uint8_t *data,
1484	__in			size_t size);
1485
1486extern				efx_rc_t
1487efx_bootcfg_write(
1488	__in			efx_nic_t *enp,
1489	__in_bcount(size)	uint8_t *data,
1490	__in			size_t size);
1491
1492#endif	/* EFSYS_OPT_BOOTCFG */
1493
1494#if EFSYS_OPT_DIAG
1495
1496typedef enum efx_pattern_type_t {
1497	EFX_PATTERN_BYTE_INCREMENT = 0,
1498	EFX_PATTERN_ALL_THE_SAME,
1499	EFX_PATTERN_BIT_ALTERNATE,
1500	EFX_PATTERN_BYTE_ALTERNATE,
1501	EFX_PATTERN_BYTE_CHANGING,
1502	EFX_PATTERN_BIT_SWEEP,
1503	EFX_PATTERN_NTYPES
1504} efx_pattern_type_t;
1505
1506typedef			void
1507(*efx_sram_pattern_fn_t)(
1508	__in		size_t row,
1509	__in		boolean_t negate,
1510	__out		efx_qword_t *eqp);
1511
1512extern	__checkReturn	efx_rc_t
1513efx_sram_test(
1514	__in		efx_nic_t *enp,
1515	__in		efx_pattern_type_t type);
1516
1517#endif	/* EFSYS_OPT_DIAG */
1518
1519extern	__checkReturn	efx_rc_t
1520efx_sram_buf_tbl_set(
1521	__in		efx_nic_t *enp,
1522	__in		uint32_t id,
1523	__in		efsys_mem_t *esmp,
1524	__in		size_t n);
1525
1526extern		void
1527efx_sram_buf_tbl_clear(
1528	__in	efx_nic_t *enp,
1529	__in	uint32_t id,
1530	__in	size_t n);
1531
1532#define	EFX_BUF_TBL_SIZE	0x20000
1533
1534#define	EFX_BUF_SIZE		4096
1535
1536/* EV */
1537
1538typedef struct efx_evq_s	efx_evq_t;
1539
1540#if EFSYS_OPT_QSTATS
1541
1542/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1543typedef enum efx_ev_qstat_e {
1544	EV_ALL,
1545	EV_RX,
1546	EV_RX_OK,
1547	EV_RX_FRM_TRUNC,
1548	EV_RX_TOBE_DISC,
1549	EV_RX_PAUSE_FRM_ERR,
1550	EV_RX_BUF_OWNER_ID_ERR,
1551	EV_RX_IPV4_HDR_CHKSUM_ERR,
1552	EV_RX_TCP_UDP_CHKSUM_ERR,
1553	EV_RX_ETH_CRC_ERR,
1554	EV_RX_IP_FRAG_ERR,
1555	EV_RX_MCAST_PKT,
1556	EV_RX_MCAST_HASH_MATCH,
1557	EV_RX_TCP_IPV4,
1558	EV_RX_TCP_IPV6,
1559	EV_RX_UDP_IPV4,
1560	EV_RX_UDP_IPV6,
1561	EV_RX_OTHER_IPV4,
1562	EV_RX_OTHER_IPV6,
1563	EV_RX_NON_IP,
1564	EV_RX_BATCH,
1565	EV_TX,
1566	EV_TX_WQ_FF_FULL,
1567	EV_TX_PKT_ERR,
1568	EV_TX_PKT_TOO_BIG,
1569	EV_TX_UNEXPECTED,
1570	EV_GLOBAL,
1571	EV_GLOBAL_MNT,
1572	EV_DRIVER,
1573	EV_DRIVER_SRM_UPD_DONE,
1574	EV_DRIVER_TX_DESCQ_FLS_DONE,
1575	EV_DRIVER_RX_DESCQ_FLS_DONE,
1576	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1577	EV_DRIVER_RX_DSC_ERROR,
1578	EV_DRIVER_TX_DSC_ERROR,
1579	EV_DRV_GEN,
1580	EV_MCDI_RESPONSE,
1581	EV_NQSTATS
1582} efx_ev_qstat_t;
1583
1584/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1585
1586#endif	/* EFSYS_OPT_QSTATS */
1587
1588extern	__checkReturn	efx_rc_t
1589efx_ev_init(
1590	__in		efx_nic_t *enp);
1591
1592extern		void
1593efx_ev_fini(
1594	__in		efx_nic_t *enp);
1595
1596#define	EFX_EVQ_MAXNEVS		32768
1597#define	EFX_EVQ_MINNEVS		512
1598
1599#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1600#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1601
1602#define	EFX_EVQ_FLAGS_TYPE_MASK		(0x3)
1603#define	EFX_EVQ_FLAGS_TYPE_AUTO		(0x0)
1604#define	EFX_EVQ_FLAGS_TYPE_THROUGHPUT	(0x1)
1605#define	EFX_EVQ_FLAGS_TYPE_LOW_LATENCY	(0x2)
1606
1607#define	EFX_EVQ_FLAGS_NOTIFY_MASK	(0xC)
1608#define	EFX_EVQ_FLAGS_NOTIFY_INTERRUPT	(0x0)	/* Interrupting (default) */
1609#define	EFX_EVQ_FLAGS_NOTIFY_DISABLED	(0x4)	/* Non-interrupting */
1610
1611extern	__checkReturn	efx_rc_t
1612efx_ev_qcreate(
1613	__in		efx_nic_t *enp,
1614	__in		unsigned int index,
1615	__in		efsys_mem_t *esmp,
1616	__in		size_t n,
1617	__in		uint32_t id,
1618	__in		uint32_t us,
1619	__in		uint32_t flags,
1620	__deref_out	efx_evq_t **eepp);
1621
1622extern		void
1623efx_ev_qpost(
1624	__in		efx_evq_t *eep,
1625	__in		uint16_t data);
1626
1627typedef __checkReturn	boolean_t
1628(*efx_initialized_ev_t)(
1629	__in_opt	void *arg);
1630
1631#define	EFX_PKT_UNICAST		0x0004
1632#define	EFX_PKT_START		0x0008
1633
1634#define	EFX_PKT_VLAN_TAGGED	0x0010
1635#define	EFX_CKSUM_TCPUDP	0x0020
1636#define	EFX_CKSUM_IPV4		0x0040
1637#define	EFX_PKT_CONT		0x0080
1638
1639#define	EFX_CHECK_VLAN		0x0100
1640#define	EFX_PKT_TCP		0x0200
1641#define	EFX_PKT_UDP		0x0400
1642#define	EFX_PKT_IPV4		0x0800
1643
1644#define	EFX_PKT_IPV6		0x1000
1645#define	EFX_PKT_PREFIX_LEN	0x2000
1646#define	EFX_ADDR_MISMATCH	0x4000
1647#define	EFX_DISCARD		0x8000
1648
1649#define	EFX_EV_RX_NLABELS	32
1650#define	EFX_EV_TX_NLABELS	32
1651
1652typedef	__checkReturn	boolean_t
1653(*efx_rx_ev_t)(
1654	__in_opt	void *arg,
1655	__in		uint32_t label,
1656	__in		uint32_t id,
1657	__in		uint32_t size,
1658	__in		uint16_t flags);
1659
1660typedef	__checkReturn	boolean_t
1661(*efx_tx_ev_t)(
1662	__in_opt	void *arg,
1663	__in		uint32_t label,
1664	__in		uint32_t id);
1665
1666#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1667#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1668#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1669#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1670#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1671#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1672#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1673#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1674#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1675
1676typedef	__checkReturn	boolean_t
1677(*efx_exception_ev_t)(
1678	__in_opt	void *arg,
1679	__in		uint32_t label,
1680	__in		uint32_t data);
1681
1682typedef	__checkReturn	boolean_t
1683(*efx_rxq_flush_done_ev_t)(
1684	__in_opt	void *arg,
1685	__in		uint32_t rxq_index);
1686
1687typedef	__checkReturn	boolean_t
1688(*efx_rxq_flush_failed_ev_t)(
1689	__in_opt	void *arg,
1690	__in		uint32_t rxq_index);
1691
1692typedef	__checkReturn	boolean_t
1693(*efx_txq_flush_done_ev_t)(
1694	__in_opt	void *arg,
1695	__in		uint32_t txq_index);
1696
1697typedef	__checkReturn	boolean_t
1698(*efx_software_ev_t)(
1699	__in_opt	void *arg,
1700	__in		uint16_t magic);
1701
1702typedef	__checkReturn	boolean_t
1703(*efx_sram_ev_t)(
1704	__in_opt	void *arg,
1705	__in		uint32_t code);
1706
1707#define	EFX_SRAM_CLEAR		0
1708#define	EFX_SRAM_UPDATE		1
1709#define	EFX_SRAM_ILLEGAL_CLEAR	2
1710
1711typedef	__checkReturn	boolean_t
1712(*efx_wake_up_ev_t)(
1713	__in_opt	void *arg,
1714	__in		uint32_t label);
1715
1716typedef	__checkReturn	boolean_t
1717(*efx_timer_ev_t)(
1718	__in_opt	void *arg,
1719	__in		uint32_t label);
1720
1721typedef __checkReturn	boolean_t
1722(*efx_link_change_ev_t)(
1723	__in_opt	void *arg,
1724	__in		efx_link_mode_t	link_mode);
1725
1726#if EFSYS_OPT_MON_STATS
1727
1728typedef __checkReturn	boolean_t
1729(*efx_monitor_ev_t)(
1730	__in_opt	void *arg,
1731	__in		efx_mon_stat_t id,
1732	__in		efx_mon_stat_value_t value);
1733
1734#endif	/* EFSYS_OPT_MON_STATS */
1735
1736#if EFSYS_OPT_MAC_STATS
1737
1738typedef __checkReturn	boolean_t
1739(*efx_mac_stats_ev_t)(
1740	__in_opt	void *arg,
1741	__in		uint32_t generation
1742	);
1743
1744#endif	/* EFSYS_OPT_MAC_STATS */
1745
1746typedef struct efx_ev_callbacks_s {
1747	efx_initialized_ev_t		eec_initialized;
1748	efx_rx_ev_t			eec_rx;
1749	efx_tx_ev_t			eec_tx;
1750	efx_exception_ev_t		eec_exception;
1751	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1752	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1753	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1754	efx_software_ev_t		eec_software;
1755	efx_sram_ev_t			eec_sram;
1756	efx_wake_up_ev_t		eec_wake_up;
1757	efx_timer_ev_t			eec_timer;
1758	efx_link_change_ev_t		eec_link_change;
1759#if EFSYS_OPT_MON_STATS
1760	efx_monitor_ev_t		eec_monitor;
1761#endif	/* EFSYS_OPT_MON_STATS */
1762#if EFSYS_OPT_MAC_STATS
1763	efx_mac_stats_ev_t		eec_mac_stats;
1764#endif	/* EFSYS_OPT_MAC_STATS */
1765} efx_ev_callbacks_t;
1766
1767extern	__checkReturn	boolean_t
1768efx_ev_qpending(
1769	__in		efx_evq_t *eep,
1770	__in		unsigned int count);
1771
1772#if EFSYS_OPT_EV_PREFETCH
1773
1774extern			void
1775efx_ev_qprefetch(
1776	__in		efx_evq_t *eep,
1777	__in		unsigned int count);
1778
1779#endif	/* EFSYS_OPT_EV_PREFETCH */
1780
1781extern			void
1782efx_ev_qpoll(
1783	__in		efx_evq_t *eep,
1784	__inout		unsigned int *countp,
1785	__in		const efx_ev_callbacks_t *eecp,
1786	__in_opt	void *arg);
1787
1788extern	__checkReturn	efx_rc_t
1789efx_ev_usecs_to_ticks(
1790	__in		efx_nic_t *enp,
1791	__in		unsigned int usecs,
1792	__out		unsigned int *ticksp);
1793
1794extern	__checkReturn	efx_rc_t
1795efx_ev_qmoderate(
1796	__in		efx_evq_t *eep,
1797	__in		unsigned int us);
1798
1799extern	__checkReturn	efx_rc_t
1800efx_ev_qprime(
1801	__in		efx_evq_t *eep,
1802	__in		unsigned int count);
1803
1804#if EFSYS_OPT_QSTATS
1805
1806#if EFSYS_OPT_NAMES
1807
1808extern		const char *
1809efx_ev_qstat_name(
1810	__in	efx_nic_t *enp,
1811	__in	unsigned int id);
1812
1813#endif	/* EFSYS_OPT_NAMES */
1814
1815extern					void
1816efx_ev_qstats_update(
1817	__in				efx_evq_t *eep,
1818	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1819
1820#endif	/* EFSYS_OPT_QSTATS */
1821
1822extern		void
1823efx_ev_qdestroy(
1824	__in	efx_evq_t *eep);
1825
1826/* RX */
1827
1828extern	__checkReturn	efx_rc_t
1829efx_rx_init(
1830	__inout		efx_nic_t *enp);
1831
1832extern		void
1833efx_rx_fini(
1834	__in		efx_nic_t *enp);
1835
1836#if EFSYS_OPT_RX_SCATTER
1837	__checkReturn	efx_rc_t
1838efx_rx_scatter_enable(
1839	__in		efx_nic_t *enp,
1840	__in		unsigned int buf_size);
1841#endif	/* EFSYS_OPT_RX_SCATTER */
1842
1843/* Handle to represent use of the default RSS context. */
1844#define	EFX_RSS_CONTEXT_DEFAULT	0xffffffff
1845
1846#if EFSYS_OPT_RX_SCALE
1847
1848typedef enum efx_rx_hash_alg_e {
1849	EFX_RX_HASHALG_LFSR = 0,
1850	EFX_RX_HASHALG_TOEPLITZ
1851} efx_rx_hash_alg_t;
1852
1853#define	EFX_RX_HASH_IPV4	(1U << 0)
1854#define	EFX_RX_HASH_TCPIPV4	(1U << 1)
1855#define	EFX_RX_HASH_IPV6	(1U << 2)
1856#define	EFX_RX_HASH_TCPIPV6	(1U << 3)
1857
1858typedef unsigned int efx_rx_hash_type_t;
1859
1860typedef enum efx_rx_hash_support_e {
1861	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1862	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1863} efx_rx_hash_support_t;
1864
1865#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1866#define	EFX_MAXRSS		64	/* RX indirection entry range */
1867#define	EFX_MAXRSS_LEGACY	16	/* See bug16611 and bug17213 */
1868
1869typedef enum efx_rx_scale_support_e {
1870	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1871	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1872	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1873} efx_rx_scale_support_t;
1874
1875extern	__checkReturn	efx_rc_t
1876efx_rx_hash_support_get(
1877	__in		efx_nic_t *enp,
1878	__out		efx_rx_hash_support_t *supportp);
1879
1880
1881extern	__checkReturn	efx_rc_t
1882efx_rx_scale_support_get(
1883	__in		efx_nic_t *enp,
1884	__out		efx_rx_scale_support_t *supportp);
1885
1886extern	__checkReturn	efx_rc_t
1887efx_rx_scale_mode_set(
1888	__in	efx_nic_t *enp,
1889	__in	efx_rx_hash_alg_t alg,
1890	__in	efx_rx_hash_type_t type,
1891	__in	boolean_t insert);
1892
1893extern	__checkReturn	efx_rc_t
1894efx_rx_scale_tbl_set(
1895	__in		efx_nic_t *enp,
1896	__in_ecount(n)	unsigned int *table,
1897	__in		size_t n);
1898
1899extern	__checkReturn	efx_rc_t
1900efx_rx_scale_key_set(
1901	__in		efx_nic_t *enp,
1902	__in_ecount(n)	uint8_t *key,
1903	__in		size_t n);
1904
1905extern	__checkReturn	uint32_t
1906efx_pseudo_hdr_hash_get(
1907	__in		efx_rxq_t *erp,
1908	__in		efx_rx_hash_alg_t func,
1909	__in		uint8_t *buffer);
1910
1911#endif	/* EFSYS_OPT_RX_SCALE */
1912
1913extern	__checkReturn	efx_rc_t
1914efx_pseudo_hdr_pkt_length_get(
1915	__in		efx_rxq_t *erp,
1916	__in		uint8_t *buffer,
1917	__out		uint16_t *pkt_lengthp);
1918
1919#define	EFX_RXQ_MAXNDESCS		4096
1920#define	EFX_RXQ_MINNDESCS		512
1921
1922#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1923#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1924#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1925#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1926
1927typedef enum efx_rxq_type_e {
1928	EFX_RXQ_TYPE_DEFAULT,
1929	EFX_RXQ_TYPE_SCATTER,
1930	EFX_RXQ_NTYPES
1931} efx_rxq_type_t;
1932
1933extern	__checkReturn	efx_rc_t
1934efx_rx_qcreate(
1935	__in		efx_nic_t *enp,
1936	__in		unsigned int index,
1937	__in		unsigned int label,
1938	__in		efx_rxq_type_t type,
1939	__in		efsys_mem_t *esmp,
1940	__in		size_t n,
1941	__in		uint32_t id,
1942	__in		efx_evq_t *eep,
1943	__deref_out	efx_rxq_t **erpp);
1944
1945typedef struct efx_buffer_s {
1946	efsys_dma_addr_t	eb_addr;
1947	size_t			eb_size;
1948	boolean_t		eb_eop;
1949} efx_buffer_t;
1950
1951typedef struct efx_desc_s {
1952	efx_qword_t ed_eq;
1953} efx_desc_t;
1954
1955extern			void
1956efx_rx_qpost(
1957	__in		efx_rxq_t *erp,
1958	__in_ecount(n)	efsys_dma_addr_t *addrp,
1959	__in		size_t size,
1960	__in		unsigned int n,
1961	__in		unsigned int completed,
1962	__in		unsigned int added);
1963
1964extern		void
1965efx_rx_qpush(
1966	__in	efx_rxq_t *erp,
1967	__in	unsigned int added,
1968	__inout	unsigned int *pushedp);
1969
1970extern	__checkReturn	efx_rc_t
1971efx_rx_qflush(
1972	__in	efx_rxq_t *erp);
1973
1974extern		void
1975efx_rx_qenable(
1976	__in	efx_rxq_t *erp);
1977
1978extern		void
1979efx_rx_qdestroy(
1980	__in	efx_rxq_t *erp);
1981
1982/* TX */
1983
1984typedef struct efx_txq_s	efx_txq_t;
1985
1986#if EFSYS_OPT_QSTATS
1987
1988/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1989typedef enum efx_tx_qstat_e {
1990	TX_POST,
1991	TX_POST_PIO,
1992	TX_NQSTATS
1993} efx_tx_qstat_t;
1994
1995/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1996
1997#endif	/* EFSYS_OPT_QSTATS */
1998
1999extern	__checkReturn	efx_rc_t
2000efx_tx_init(
2001	__in		efx_nic_t *enp);
2002
2003extern		void
2004efx_tx_fini(
2005	__in	efx_nic_t *enp);
2006
2007#define	EFX_TXQ_MINNDESCS		512
2008
2009#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
2010#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2011#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2012#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2013
2014#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2015
2016#define	EFX_TXQ_CKSUM_IPV4		0x0001
2017#define	EFX_TXQ_CKSUM_TCPUDP		0x0002
2018#define	EFX_TXQ_FATSOV2			0x0004
2019#define	EFX_TXQ_CKSUM_INNER_IPV4	0x0008
2020#define	EFX_TXQ_CKSUM_INNER_TCPUDP	0x0010
2021
2022extern	__checkReturn	efx_rc_t
2023efx_tx_qcreate(
2024	__in		efx_nic_t *enp,
2025	__in		unsigned int index,
2026	__in		unsigned int label,
2027	__in		efsys_mem_t *esmp,
2028	__in		size_t n,
2029	__in		uint32_t id,
2030	__in		uint16_t flags,
2031	__in		efx_evq_t *eep,
2032	__deref_out	efx_txq_t **etpp,
2033	__out		unsigned int *addedp);
2034
2035extern	__checkReturn	efx_rc_t
2036efx_tx_qpost(
2037	__in		efx_txq_t *etp,
2038	__in_ecount(n)	efx_buffer_t *eb,
2039	__in		unsigned int n,
2040	__in		unsigned int completed,
2041	__inout		unsigned int *addedp);
2042
2043extern	__checkReturn	efx_rc_t
2044efx_tx_qpace(
2045	__in		efx_txq_t *etp,
2046	__in		unsigned int ns);
2047
2048extern			void
2049efx_tx_qpush(
2050	__in		efx_txq_t *etp,
2051	__in		unsigned int added,
2052	__in		unsigned int pushed);
2053
2054extern	__checkReturn	efx_rc_t
2055efx_tx_qflush(
2056	__in		efx_txq_t *etp);
2057
2058extern			void
2059efx_tx_qenable(
2060	__in		efx_txq_t *etp);
2061
2062extern	__checkReturn	efx_rc_t
2063efx_tx_qpio_enable(
2064	__in		efx_txq_t *etp);
2065
2066extern			void
2067efx_tx_qpio_disable(
2068	__in		efx_txq_t *etp);
2069
2070extern	__checkReturn	efx_rc_t
2071efx_tx_qpio_write(
2072	__in			efx_txq_t *etp,
2073	__in_ecount(buf_length)	uint8_t *buffer,
2074	__in			size_t buf_length,
2075	__in			size_t pio_buf_offset);
2076
2077extern	__checkReturn	efx_rc_t
2078efx_tx_qpio_post(
2079	__in			efx_txq_t *etp,
2080	__in			size_t pkt_length,
2081	__in			unsigned int completed,
2082	__inout			unsigned int *addedp);
2083
2084extern	__checkReturn	efx_rc_t
2085efx_tx_qdesc_post(
2086	__in		efx_txq_t *etp,
2087	__in_ecount(n)	efx_desc_t *ed,
2088	__in		unsigned int n,
2089	__in		unsigned int completed,
2090	__inout		unsigned int *addedp);
2091
2092extern	void
2093efx_tx_qdesc_dma_create(
2094	__in	efx_txq_t *etp,
2095	__in	efsys_dma_addr_t addr,
2096	__in	size_t size,
2097	__in	boolean_t eop,
2098	__out	efx_desc_t *edp);
2099
2100extern	void
2101efx_tx_qdesc_tso_create(
2102	__in	efx_txq_t *etp,
2103	__in	uint16_t ipv4_id,
2104	__in	uint32_t tcp_seq,
2105	__in	uint8_t  tcp_flags,
2106	__out	efx_desc_t *edp);
2107
2108/* Number of FATSOv2 option descriptors */
2109#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2110
2111/* Maximum number of DMA segments per TSO packet (not superframe) */
2112#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2113
2114extern	void
2115efx_tx_qdesc_tso2_create(
2116	__in			efx_txq_t *etp,
2117	__in			uint16_t ipv4_id,
2118	__in			uint32_t tcp_seq,
2119	__in			uint16_t tcp_mss,
2120	__out_ecount(count)	efx_desc_t *edp,
2121	__in			int count);
2122
2123extern	void
2124efx_tx_qdesc_vlantci_create(
2125	__in	efx_txq_t *etp,
2126	__in	uint16_t tci,
2127	__out	efx_desc_t *edp);
2128
2129extern	void
2130efx_tx_qdesc_checksum_create(
2131	__in	efx_txq_t *etp,
2132	__in	uint16_t flags,
2133	__out	efx_desc_t *edp);
2134
2135#if EFSYS_OPT_QSTATS
2136
2137#if EFSYS_OPT_NAMES
2138
2139extern		const char *
2140efx_tx_qstat_name(
2141	__in	efx_nic_t *etp,
2142	__in	unsigned int id);
2143
2144#endif	/* EFSYS_OPT_NAMES */
2145
2146extern					void
2147efx_tx_qstats_update(
2148	__in				efx_txq_t *etp,
2149	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2150
2151#endif	/* EFSYS_OPT_QSTATS */
2152
2153extern		void
2154efx_tx_qdestroy(
2155	__in	efx_txq_t *etp);
2156
2157
2158/* FILTER */
2159
2160#if EFSYS_OPT_FILTER
2161
2162#define	EFX_ETHER_TYPE_IPV4 0x0800
2163#define	EFX_ETHER_TYPE_IPV6 0x86DD
2164
2165#define	EFX_IPPROTO_TCP 6
2166#define	EFX_IPPROTO_UDP 17
2167#define	EFX_IPPROTO_GRE	47
2168
2169/* Use RSS to spread across multiple queues */
2170#define	EFX_FILTER_FLAG_RX_RSS		0x01
2171/* Enable RX scatter */
2172#define	EFX_FILTER_FLAG_RX_SCATTER	0x02
2173/*
2174 * Override an automatic filter (priority EFX_FILTER_PRI_AUTO).
2175 * May only be set by the filter implementation for each type.
2176 * A removal request will restore the automatic filter in its place.
2177 */
2178#define	EFX_FILTER_FLAG_RX_OVER_AUTO	0x04
2179/* Filter is for RX */
2180#define	EFX_FILTER_FLAG_RX		0x08
2181/* Filter is for TX */
2182#define	EFX_FILTER_FLAG_TX		0x10
2183
2184typedef uint8_t efx_filter_flags_t;
2185
2186/*
2187 * Flags which specify the fields to match on. The values are the same as in the
2188 * MC_CMD_FILTER_OP/MC_CMD_FILTER_OP_EXT commands.
2189 */
2190
2191/* Match by remote IP host address */
2192#define	EFX_FILTER_MATCH_REM_HOST		0x00000001
2193/* Match by local IP host address */
2194#define	EFX_FILTER_MATCH_LOC_HOST		0x00000002
2195/* Match by remote MAC address */
2196#define	EFX_FILTER_MATCH_REM_MAC		0x00000004
2197/* Match by remote TCP/UDP port */
2198#define	EFX_FILTER_MATCH_REM_PORT		0x00000008
2199/* Match by remote TCP/UDP port */
2200#define	EFX_FILTER_MATCH_LOC_MAC		0x00000010
2201/* Match by local TCP/UDP port */
2202#define	EFX_FILTER_MATCH_LOC_PORT		0x00000020
2203/* Match by Ether-type */
2204#define	EFX_FILTER_MATCH_ETHER_TYPE		0x00000040
2205/* Match by inner VLAN ID */
2206#define	EFX_FILTER_MATCH_INNER_VID		0x00000080
2207/* Match by outer VLAN ID */
2208#define	EFX_FILTER_MATCH_OUTER_VID		0x00000100
2209/* Match by IP transport protocol */
2210#define	EFX_FILTER_MATCH_IP_PROTO		0x00000200
2211/* For encapsulated packets, match all multicast inner frames */
2212#define	EFX_FILTER_MATCH_IFRM_UNKNOWN_MCAST_DST	0x01000000
2213/* For encapsulated packets, match all unicast inner frames */
2214#define	EFX_FILTER_MATCH_IFRM_UNKNOWN_UCAST_DST	0x02000000
2215/* Match otherwise-unmatched multicast and broadcast packets */
2216#define	EFX_FILTER_MATCH_UNKNOWN_MCAST_DST	0x40000000
2217/* Match otherwise-unmatched unicast packets */
2218#define	EFX_FILTER_MATCH_UNKNOWN_UCAST_DST	0x80000000
2219
2220typedef uint32_t efx_filter_match_flags_t;
2221
2222typedef enum efx_filter_priority_s {
2223	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2224	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2225					 * address list or hardware
2226					 * requirements. This may only be used
2227					 * by the filter implementation for
2228					 * each NIC type. */
2229	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2230	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2231					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2232					 */
2233} efx_filter_priority_t;
2234
2235/*
2236 * FIXME: All these fields are assumed to be in little-endian byte order.
2237 * It may be better for some to be big-endian. See bug42804.
2238 */
2239
2240typedef struct efx_filter_spec_s {
2241	efx_filter_match_flags_t	efs_match_flags;
2242	uint8_t				efs_priority;
2243	efx_filter_flags_t		efs_flags;
2244	uint16_t			efs_dmaq_id;
2245	uint32_t			efs_rss_context;
2246	uint16_t			efs_outer_vid;
2247	uint16_t			efs_inner_vid;
2248	uint8_t				efs_loc_mac[EFX_MAC_ADDR_LEN];
2249	uint8_t				efs_rem_mac[EFX_MAC_ADDR_LEN];
2250	uint16_t			efs_ether_type;
2251	uint8_t				efs_ip_proto;
2252	efx_tunnel_protocol_t		efs_encap_type;
2253	uint16_t			efs_loc_port;
2254	uint16_t			efs_rem_port;
2255	efx_oword_t			efs_rem_host;
2256	efx_oword_t			efs_loc_host;
2257} efx_filter_spec_t;
2258
2259
2260/* Default values for use in filter specifications */
2261#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2262#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2263
2264extern	__checkReturn	efx_rc_t
2265efx_filter_init(
2266	__in		efx_nic_t *enp);
2267
2268extern			void
2269efx_filter_fini(
2270	__in		efx_nic_t *enp);
2271
2272extern	__checkReturn	efx_rc_t
2273efx_filter_insert(
2274	__in		efx_nic_t *enp,
2275	__inout		efx_filter_spec_t *spec);
2276
2277extern	__checkReturn	efx_rc_t
2278efx_filter_remove(
2279	__in		efx_nic_t *enp,
2280	__inout		efx_filter_spec_t *spec);
2281
2282extern	__checkReturn	efx_rc_t
2283efx_filter_restore(
2284	__in		efx_nic_t *enp);
2285
2286extern	__checkReturn	efx_rc_t
2287efx_filter_supported_filters(
2288	__in				efx_nic_t *enp,
2289	__out_ecount(buffer_length)	uint32_t *buffer,
2290	__in				size_t buffer_length,
2291	__out				size_t *list_lengthp);
2292
2293extern			void
2294efx_filter_spec_init_rx(
2295	__out		efx_filter_spec_t *spec,
2296	__in		efx_filter_priority_t priority,
2297	__in		efx_filter_flags_t flags,
2298	__in		efx_rxq_t *erp);
2299
2300extern			void
2301efx_filter_spec_init_tx(
2302	__out		efx_filter_spec_t *spec,
2303	__in		efx_txq_t *etp);
2304
2305extern	__checkReturn	efx_rc_t
2306efx_filter_spec_set_ipv4_local(
2307	__inout		efx_filter_spec_t *spec,
2308	__in		uint8_t proto,
2309	__in		uint32_t host,
2310	__in		uint16_t port);
2311
2312extern	__checkReturn	efx_rc_t
2313efx_filter_spec_set_ipv4_full(
2314	__inout		efx_filter_spec_t *spec,
2315	__in		uint8_t proto,
2316	__in		uint32_t lhost,
2317	__in		uint16_t lport,
2318	__in		uint32_t rhost,
2319	__in		uint16_t rport);
2320
2321extern	__checkReturn	efx_rc_t
2322efx_filter_spec_set_eth_local(
2323	__inout		efx_filter_spec_t *spec,
2324	__in		uint16_t vid,
2325	__in		const uint8_t *addr);
2326
2327extern			void
2328efx_filter_spec_set_ether_type(
2329	__inout		efx_filter_spec_t *spec,
2330	__in		uint16_t ether_type);
2331
2332extern	__checkReturn	efx_rc_t
2333efx_filter_spec_set_uc_def(
2334	__inout		efx_filter_spec_t *spec);
2335
2336extern	__checkReturn	efx_rc_t
2337efx_filter_spec_set_mc_def(
2338	__inout		efx_filter_spec_t *spec);
2339
2340typedef enum efx_filter_inner_frame_match_e {
2341	EFX_FILTER_INNER_FRAME_MATCH_OTHER = 0,
2342	EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_MCAST_DST,
2343	EFX_FILTER_INNER_FRAME_MATCH_UNKNOWN_UCAST_DST
2344} efx_filter_inner_frame_match_t;
2345
2346extern	__checkReturn	efx_rc_t
2347efx_filter_spec_set_encap_type(
2348	__inout		efx_filter_spec_t *spec,
2349	__in		efx_tunnel_protocol_t encap_type,
2350	__in		efx_filter_inner_frame_match_t inner_frame_match);
2351
2352
2353#endif	/* EFSYS_OPT_FILTER */
2354
2355/* HASH */
2356
2357extern	__checkReturn		uint32_t
2358efx_hash_dwords(
2359	__in_ecount(count)	uint32_t const *input,
2360	__in			size_t count,
2361	__in			uint32_t init);
2362
2363extern	__checkReturn		uint32_t
2364efx_hash_bytes(
2365	__in_ecount(length)	uint8_t const *input,
2366	__in			size_t length,
2367	__in			uint32_t init);
2368
2369#if EFSYS_OPT_LICENSING
2370
2371/* LICENSING */
2372
2373typedef struct efx_key_stats_s {
2374	uint32_t	eks_valid;
2375	uint32_t	eks_invalid;
2376	uint32_t	eks_blacklisted;
2377	uint32_t	eks_unverifiable;
2378	uint32_t	eks_wrong_node;
2379	uint32_t	eks_licensed_apps_lo;
2380	uint32_t	eks_licensed_apps_hi;
2381	uint32_t	eks_licensed_features_lo;
2382	uint32_t	eks_licensed_features_hi;
2383} efx_key_stats_t;
2384
2385extern	__checkReturn		efx_rc_t
2386efx_lic_init(
2387	__in			efx_nic_t *enp);
2388
2389extern				void
2390efx_lic_fini(
2391	__in			efx_nic_t *enp);
2392
2393extern	__checkReturn	boolean_t
2394efx_lic_check_support(
2395	__in			efx_nic_t *enp);
2396
2397extern	__checkReturn	efx_rc_t
2398efx_lic_update_licenses(
2399	__in		efx_nic_t *enp);
2400
2401extern	__checkReturn	efx_rc_t
2402efx_lic_get_key_stats(
2403	__in		efx_nic_t *enp,
2404	__out		efx_key_stats_t *ksp);
2405
2406extern	__checkReturn	efx_rc_t
2407efx_lic_app_state(
2408	__in		efx_nic_t *enp,
2409	__in		uint64_t app_id,
2410	__out		boolean_t *licensedp);
2411
2412extern	__checkReturn	efx_rc_t
2413efx_lic_get_id(
2414	__in		efx_nic_t *enp,
2415	__in		size_t buffer_size,
2416	__out		uint32_t *typep,
2417	__out		size_t *lengthp,
2418	__out_opt	uint8_t *bufferp);
2419
2420
2421extern	__checkReturn		efx_rc_t
2422efx_lic_find_start(
2423	__in			efx_nic_t *enp,
2424	__in_bcount(buffer_size)
2425				caddr_t bufferp,
2426	__in			size_t buffer_size,
2427	__out			uint32_t *startp
2428	);
2429
2430extern	__checkReturn		efx_rc_t
2431efx_lic_find_end(
2432	__in			efx_nic_t *enp,
2433	__in_bcount(buffer_size)
2434				caddr_t bufferp,
2435	__in			size_t buffer_size,
2436	__in			uint32_t offset,
2437	__out			uint32_t *endp
2438	);
2439
2440extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2441efx_lic_find_key(
2442	__in			efx_nic_t *enp,
2443	__in_bcount(buffer_size)
2444				caddr_t bufferp,
2445	__in			size_t buffer_size,
2446	__in			uint32_t offset,
2447	__out			uint32_t *startp,
2448	__out			uint32_t *lengthp
2449	);
2450
2451extern	__checkReturn	__success(return != B_FALSE)	boolean_t
2452efx_lic_validate_key(
2453	__in			efx_nic_t *enp,
2454	__in_bcount(length)	caddr_t keyp,
2455	__in			uint32_t length
2456	);
2457
2458extern	__checkReturn		efx_rc_t
2459efx_lic_read_key(
2460	__in			efx_nic_t *enp,
2461	__in_bcount(buffer_size)
2462				caddr_t bufferp,
2463	__in			size_t buffer_size,
2464	__in			uint32_t offset,
2465	__in			uint32_t length,
2466	__out_bcount_part(key_max_size, *lengthp)
2467				caddr_t keyp,
2468	__in			size_t key_max_size,
2469	__out			uint32_t *lengthp
2470	);
2471
2472extern	__checkReturn		efx_rc_t
2473efx_lic_write_key(
2474	__in			efx_nic_t *enp,
2475	__in_bcount(buffer_size)
2476				caddr_t bufferp,
2477	__in			size_t buffer_size,
2478	__in			uint32_t offset,
2479	__in_bcount(length)	caddr_t keyp,
2480	__in			uint32_t length,
2481	__out			uint32_t *lengthp
2482	);
2483
2484	__checkReturn		efx_rc_t
2485efx_lic_delete_key(
2486	__in			efx_nic_t *enp,
2487	__in_bcount(buffer_size)
2488				caddr_t bufferp,
2489	__in			size_t buffer_size,
2490	__in			uint32_t offset,
2491	__in			uint32_t length,
2492	__in			uint32_t end,
2493	__out			uint32_t *deltap
2494	);
2495
2496extern	__checkReturn		efx_rc_t
2497efx_lic_create_partition(
2498	__in			efx_nic_t *enp,
2499	__in_bcount(buffer_size)
2500				caddr_t bufferp,
2501	__in			size_t buffer_size
2502	);
2503
2504extern	__checkReturn		efx_rc_t
2505efx_lic_finish_partition(
2506	__in			efx_nic_t *enp,
2507	__in_bcount(buffer_size)
2508				caddr_t bufferp,
2509	__in			size_t buffer_size
2510	);
2511
2512#endif	/* EFSYS_OPT_LICENSING */
2513
2514
2515
2516#ifdef	__cplusplus
2517}
2518#endif
2519
2520#endif	/* _SYS_EFX_H */
2521