1/******************************************************************************* 2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3* 4*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5*that the following conditions are met: 6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7*following disclaimer. 8*2. Redistributions in binary form must reproduce the above copyright notice, 9*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10*with the distribution. 11* 12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20* 21* $FreeBSD$ 22* 23********************************************************************************/ 24/*******************************************************************************/ 25/*! \file sampidefs.h 26 * \brief The file defines the constants used by SAS/SATA LL layer 27 * 28 */ 29 30/*******************************************************************************/ 31 32#ifndef __SAMPIDEFS_H__ 33 34#define __SAMPIDEFS_H__ 35 36/* for Request Opcode of IOMB */ 37#define OPC_INB_ECHO 0x001 /* */ 38 39#define OPC_INB_PHYSTART 0x004 /* */ 40#define OPC_INB_PHYSTOP 0x005 /* */ 41#define OPC_INB_SSPINIIOSTART 0x006 /* */ 42#define OPC_INB_SSPINITMSTART 0x007 /* */ 43#define OPC_INB_SSPINIEXTIOSTART 0x008 /* V reserved */ 44#define OPC_INB_DEV_HANDLE_ACCEPT 0x009 /* */ 45#define OPC_INB_SSPTGTIOSTART 0x00a /* */ 46#define OPC_INB_SSPTGTRSPSTART 0x00b /* */ 47#define OPC_INB_SSP_ABORT 0x00f /* */ 48#define OPC_INB_DEREG_DEV_HANDLE 0x010 /* 16 */ 49#define OPC_INB_GET_DEV_HANDLE 0x011 /* 17 */ 50#define OPC_INB_SMP_REQUEST 0x012 /* 18 */ 51 52#define OPC_INB_SMP_ABORT 0x014 /* 20 */ 53 54#define OPC_INB_SPC_REG_DEV 0x016 /* 22 V reserved */ 55#define OPC_INB_SATA_HOST_OPSTART 0x017 /* 23 */ 56#define OPC_INB_SATA_ABORT 0x018 /* 24 */ 57#define OPC_INB_LOCAL_PHY_CONTROL 0x019 /* 25 */ 58#define OPC_INB_SPC_GET_DEV_INFO 0x01a /* 26 V reserved */ 59 60#define OPC_INB_FW_FLASH_UPDATE 0x020 /* 32 */ 61 62#define OPC_INB_GPIO 0x022 /* 34 */ 63#define OPC_INB_SAS_DIAG_MODE_START_END 0x023 /* 35 */ 64#define OPC_INB_SAS_DIAG_EXECUTE 0x024 /* 36 */ 65#define OPC_INB_SPC_SAS_HW_EVENT_ACK 0x025 /* 37 V reserved */ 66#define OPC_INB_GET_TIME_STAMP 0x026 /* 38 */ 67#define OPC_INB_PORT_CONTROL 0x027 /* 39 */ 68#define OPC_INB_GET_NVMD_DATA 0x028 /* 40 */ 69#define OPC_INB_SET_NVMD_DATA 0x029 /* 41 */ 70#define OPC_INB_SET_DEVICE_STATE 0x02a /* 42 */ 71#define OPC_INB_GET_DEVICE_STATE 0x02b /* 43 */ 72#define OPC_INB_SET_DEV_INFO 0x02c /* 44 */ 73#define OPC_INB_SAS_RE_INITIALIZE 0x02d /* 45 V reserved */ 74#define OPC_INB_SGPIO 0x02e /* 46 */ 75#define OPC_INB_PCIE_DIAG_EXECUTE 0x02f /* 47 */ 76 77#define OPC_INB_SET_CONTROLLER_CONFIG 0x030 /* 48 */ 78#define OPC_INB_GET_CONTROLLER_CONFIG 0x031 /* 49 */ 79 80#define OPC_INB_REG_DEV 0x032 /* 50 SPCV */ 81#define OPC_INB_SAS_HW_EVENT_ACK 0x033 /* 51 SPCV */ 82#define OPC_INB_GET_DEV_INFO 0x034 /* 52 SPCV */ 83#define OPC_INB_GET_PHY_PROFILE 0x035 /* 53 SPCV */ 84#define OPC_INB_FLASH_OP_EXT 0x036 /* 54 SPCV */ 85#define OPC_INB_SET_PHY_PROFILE 0x037 /* 55 SPCV */ 86#define OPC_INB_GET_DFE_DATA 0x038 /* 56 SPCV */ 87#define OPC_INB_GET_VHIST_CAP 0x039 /* 57 SPCV12g */ 88 89 90#define OPC_INB_KEK_MANAGEMENT 0x100 /* 256 SPCV */ 91#define OPC_INB_DEK_MANAGEMENT 0x101 /* 257 SPCV */ 92#define OPC_INB_SSP_DIF_ENC_OPSTART 0x102 /* 258 SPCV */ 93#define OPC_INB_SATA_DIF_ENC_OPSTART 0x103 /* 259 SPCV */ 94#define OPC_INB_OPR_MGMT 0x104 /* 260 SPCV */ 95#define OPC_INB_ENC_TEST_EXECUTE 0x105 /* 261 SPCV */ 96#define OPC_INB_SET_OPERATOR 0x106 /* 262 SPCV */ 97#define OPC_INB_GET_OPERATOR 0x107 /* 263 SPCV */ 98#define OPC_INB_DIF_ENC_OFFLOAD_CMD 0x110 /* 272 SPCV */ 99 100#define OPC_INB_FW_PROFILE 0x888 /* 2184 SPCV */ 101 102/* for Response Opcode of IOMB */ 103#define OPC_OUB_ECHO 0x001 /* 1 */ 104 105#define OPC_OUB_SPC_HW_EVENT 0x004 /* 4 V reserved Now OPC_OUB_HW_EVENT */ 106#define OPC_OUB_SSP_COMP 0x005 /* 5 */ 107#define OPC_OUB_SMP_COMP 0x006 /* 6 */ 108#define OPC_OUB_LOCAL_PHY_CNTRL 0x007 /* 7 */ 109 110#define OPC_OUB_SPC_DEV_REGIST 0x00a /* 10 V reserved Now OPC_OUB_DEV_REGIST */ 111#define OPC_OUB_DEREG_DEV 0x00b /* 11 */ 112#define OPC_OUB_GET_DEV_HANDLE 0x00c /* 12 */ 113#define OPC_OUB_SATA_COMP 0x00d /* 13 */ 114#define OPC_OUB_SATA_EVENT 0x00e /* 14 */ 115#define OPC_OUB_SSP_EVENT 0x00f /* 15 */ 116 117#define OPC_OUB_SPC_DEV_HANDLE_ARRIV 0x010 /* 16 V reserved Now OPC_OUB_DEV_HANDLE_ARRIV */ 118 119#define OPC_OUB_SSP_RECV_EVENT 0x012 /* 18 */ 120#define OPC_OUB_SPC_DEV_INFO 0x013 /* 19 V reserved Now OPC_OUB_DEV_INFO*/ 121#define OPC_OUB_FW_FLASH_UPDATE 0x014 /* 20 */ 122 123#define OPC_OUB_GPIO_RESPONSE 0x016 /* 22 */ 124#define OPC_OUB_GPIO_EVENT 0x017 /* 23 */ 125#define OPC_OUB_GENERAL_EVENT 0x018 /* 24 */ 126 127#define OPC_OUB_SSP_ABORT_RSP 0x01a /* 26 */ 128#define OPC_OUB_SATA_ABORT_RSP 0x01b /* 27 */ 129#define OPC_OUB_SAS_DIAG_MODE_START_END 0x01c /* 28 */ 130#define OPC_OUB_SAS_DIAG_EXECUTE 0x01d /* 29 */ 131#define OPC_OUB_GET_TIME_STAMP 0x01e /* 30 */ 132#define OPC_OUB_SPC_SAS_HW_EVENT_ACK 0x01f /* 31 V reserved Now OPC_OUB_SAS_HW_EVENT_ACK*/ 133#define OPC_OUB_PORT_CONTROL 0x020 /* 32 */ 134#define OPC_OUB_SKIP_ENTRY 0x021 /* 33 */ 135#define OPC_OUB_SMP_ABORT_RSP 0x022 /* 34 */ 136#define OPC_OUB_GET_NVMD_DATA 0x023 /* 35 */ 137#define OPC_OUB_SET_NVMD_DATA 0x024 /* 36 */ 138#define OPC_OUB_DEVICE_HANDLE_REMOVAL 0x025 /* 37 */ 139#define OPC_OUB_SET_DEVICE_STATE 0x026 /* 38 */ 140#define OPC_OUB_GET_DEVICE_STATE 0x027 /* 39 */ 141#define OPC_OUB_SET_DEV_INFO 0x028 /* 40 */ 142#define OPC_OUB_SAS_RE_INITIALIZE 0x029 /* 41 V reserved not replaced */ 143 144#define OPC_OUB_HW_EVENT 0x700 /* 1792 SPCV Was OPC_OUB_SPC_HW_EVENT*/ 145#define OPC_OUB_DEV_HANDLE_ARRIV 0x720 /* 1824 SPCV Was OPC_OUB_SPC_DEV_HANDLE_ARRIV*/ 146 147#define OPC_OUB_PHY_START_RESPONSE 0x804 /* 2052 SPCV */ 148#define OPC_OUB_PHY_STOP_RESPONSE 0x805 /* 2053 SPCV */ 149#define OPC_OUB_SGPIO_RESPONSE 0x82E /* 2094 SPCV */ 150#define OPC_OUB_PCIE_DIAG_EXECUTE 0x82F /* 2095 SPCV */ 151 152#define OPC_OUB_SET_CONTROLLER_CONFIG 0x830 /* 2096 SPCV */ 153#define OPC_OUB_GET_CONTROLLER_CONFIG 0x831 /* 2097 SPCV */ 154#define OPC_OUB_DEV_REGIST 0x832 /* 2098 SPCV */ 155#define OPC_OUB_SAS_HW_EVENT_ACK 0x833 /* 2099 SPCV */ 156#define OPC_OUB_DEV_INFO 0x834 /* 2100 SPCV */ 157#define OPC_OUB_GET_PHY_PROFILE_RSP 0x835 /* 2101 SPCV */ 158#define OPC_OUB_FLASH_OP_EXT_RSP 0x836 /* 2102 SPCV */ 159#define OPC_OUB_SET_PHY_PROFILE_RSP 0x837 /* 2103 SPCV */ 160#define OPC_OUB_GET_DFE_DATA_RSP 0x838 /* 2104 SPCV */ 161#define OPC_OUB_GET_VIST_CAP_RSP 0x839 /* Can be 2104 for SPCV12g */ 162 163#define OPC_OUB_FW_PROFILE 0x888 /* 2184 */ 164 165#define OPC_OUB_KEK_MANAGEMENT 0x900 /* 2304 SPCV */ 166#define OPC_OUB_DEK_MANAGEMENT 0x901 /* 2305 SPCV */ 167#define OPC_OUB_COMBINED_SSP_COMP 0x902 /* 2306 SPCV */ 168#define OPC_OUB_COMBINED_SATA_COMP 0x903 /* 2307 SPCV */ 169#define OPC_OUB_OPR_MGMT 0x904 /* 2308 SPCV */ 170#define OPC_OUB_ENC_TEST_EXECUTE 0x905 /* 2309 SPCV */ 171#define OPC_OUB_SET_OPERATOR 0x906 /* 2310 SPCV */ 172#define OPC_OUB_GET_OPERATOR 0x907 /* 2311 SPCV */ 173#define OPC_OUB_DIF_ENC_OFFLOAD_RSP 0x910 /* 2320 SPCV */ 174 175/* Definitions for encryption key management */ 176#define KEK_MGMT_SUBOP_INVALIDATE 0x1 177#define KEK_MGMT_SUBOP_UPDATE 0x2 178#define KEK_MGMT_SUBOP_KEYCARDINVALIDATE 0x3 179#define KEK_MGMT_SUBOP_KEYCARDUPDATE 0x4 180 181#define DEK_MGMT_SUBOP_INVALIDATE 0x1 182#define DEK_MGMT_SUBOP_UPDATE 0x2 183 184/*************************************************** 185 * typedef for IOMB structure 186 ***************************************************/ 187/** \brief the data structure of Echo Command 188 * 189 * use to describe MPI Echo Command (64 bytes) 190 * 191 */ 192typedef struct agsaEchoCmd_s { 193 bit32 tag; 194 bit32 payload[14]; 195} agsaEchoCmd_t; 196 197/** \brief the data structure of PHY Start Command 198 * 199 * use to describe MPI PHY Start Command (64 bytes) 200 * 201 */ 202typedef struct agsaPhyStartCmd_s { 203 bit32 tag; 204 bit32 SscdAseSHLmMlrPhyId; 205 agsaSASIdentify_t sasIdentify; 206 bit32 analogSetupIdx; 207 bit32 SAWT_DAWT; 208 bit32 reserved[5]; 209} agsaPhyStartCmd_t; 210 211#define SPINHOLD_DISABLE (0x00 << 14) 212#define SPINHOLD_ENABLE (0x01 << 14) 213#define LINKMODE_SAS (0x01 << 12) 214#define LINKMODE_DSATA (0x02 << 12) 215#define LINKMODE_AUTO (0x03 << 12) 216#define LINKRATE_15 (0x01 << 8) 217#define LINKRATE_30 (0x02 << 8) 218#define LINKRATE_60 (0x04 << 8) 219#define LINKRATE_12 (0x08 << 8) 220 221/** \brief the data structure of PHY Stop Command 222 * 223 * use to describe MPI PHY Start Command (64 bytes) 224 * 225 */ 226typedef struct agsaPhyStopCmd_s { 227 bit32 tag; 228 bit32 phyId; 229 bit32 reserved[13]; 230} agsaPhyStopCmd_t; 231 232/** \brief the data structure of SSP INI IO Start Command 233 * 234 * use to describe MPI SSP INI IO Start Command (64 bytes) 235 * 236 */ 237typedef struct agsaSSPIniIOStartCmd_s { 238 bit32 tag; 239 bit32 deviceId; 240 bit32 dataLen; 241 bit32 dirMTlr; 242 agsaSSPCmdInfoUnit_t SSPInfoUnit; 243 bit32 AddrLow0; 244 bit32 AddrHi0; 245 bit32 Len0; 246 bit32 E0; 247} agsaSSPIniIOStartCmd_t; 248 249/** \brief the data structure of SSP INI TM Start Command 250 * 251 * use to describe MPI SSP INI TM Start Command (64 bytes) 252 * 253 */ 254typedef struct agsaSSPIniTMStartCmd_s { 255 bit32 tag; 256 bit32 deviceId; 257 bit32 relatedTag; 258 bit32 TMfunction; 259 bit8 lun[8]; 260 bit32 dsAdsMReport; 261 bit32 reserved[8]; 262} agsaSSPIniTMStartCmd_t; 263 264/** \brief the data structure of SSP INI Extended IO Start Command 265 * 266 * use to describe MPI SSP INI Extended CDB Start Command (96 bytes to support 32 CDB) 267 * 268 */ 269typedef struct agsaSSPIniExtIOStartCmd_s { 270 bit32 tag; 271 bit32 deviceId; 272 bit32 dataLen; 273 bit32 SSPIuLendirMTlr; 274 bit8 SSPIu[1]; 275 /* variable lengh */ 276 /* bit32 AddrLow0; */ 277 /* bit32 AddrHi0; */ 278 /* bit32 Len0; */ 279 /* bit32 E0; */ 280} agsaSSPIniExtIOStartCmd_t; 281 282typedef struct agsaSSPIniEncryptIOStartCmd_s 283{ 284 bit32 tag; /* 1 */ 285 bit32 deviceId; /* 2 */ 286 bit32 dataLen; /* 3 */ 287 bit32 dirMTlr; /* 4 */ 288 bit32 sspiu_0_3_indcdbalL; /* 5 */ 289 bit32 sspiu_4_7_indcdbalH; /* 6 */ 290 bit32 sspiu_8_11; /* 7 */ 291 bit32 sspiu_12_15; /* 8 */ 292 bit32 sspiu_16_19; /* 9 */ 293 bit32 sspiu_19_23; /* 10 */ 294 bit32 sspiu_24_27; /* 11 */ 295 bit32 epl_descL; /* 12 */ 296 bit32 dpl_descL; /* 13 */ 297 bit32 edpl_descH; /* 14 */ 298 bit32 DIF_flags; /* 15 */ 299 bit32 udt; /* 16 0x10 */ 300 bit32 udtReplacementLo; /* 17 */ 301 bit32 udtReplacementHi; /* 18 */ 302 bit32 DIF_seed; /* 19 */ 303 bit32 encryptFlagsLo; /* 20 0x14 */ 304 bit32 encryptFlagsHi; /* 21 */ 305 bit32 keyTag_W0; /* 22 */ 306 bit32 keyTag_W1; /* 23 */ 307 bit32 tweakVal_W0; /* 24 0x18 */ 308 bit32 tweakVal_W1; /* 25 */ 309 bit32 tweakVal_W2; /* 26 */ 310 bit32 tweakVal_W3; /* 27 */ 311 bit32 AddrLow0; /* 28 0x1C */ 312 bit32 AddrHi0; /* 29 */ 313 bit32 Len0; /* 30 */ 314 bit32 E0; /* 31 */ 315} agsaSSPIniEncryptIOStartCmd_t; 316 317/** \brief the data structure of SSP Abort Command 318 * 319 * use to describe MPI SSP Abort Command (64 bytes) 320 * 321 */ 322typedef struct agsaSSPAbortCmd_s { 323 bit32 tag; 324 bit32 deviceId; 325 bit32 HTagAbort; 326 bit32 abortAll; 327 bit32 reserved[11]; 328} agsaSSPAbortCmd_t; 329 330/** \brief the data structure of Register Device Command 331 * 332 * use to describe MPI DEVICE REGISTER Command (64 bytes) 333 * 334 */ 335typedef struct agsaRegDevCmd_s { 336 bit32 tag; 337 bit32 phyIdportId; 338 bit32 dTypeLRateAwtHa; 339 bit32 ITNexusTimeOut; 340 bit32 sasAddrHi; 341 bit32 sasAddrLo; 342 bit32 DeviceId; 343 bit32 reserved[8]; 344} agsaRegDevCmd_t; 345 346/** \brief the data structure of Deregister Device Handle Command 347 * 348 * use to describe MPI DEREGISTER DEVIDE HANDLE Command (64 bytes) 349 * 350 */ 351typedef struct agsaDeregDevHandleCmd_s { 352 bit32 tag; 353 bit32 deviceId; 354 bit32 portId; 355 bit32 reserved[12]; 356} agsaDeregDevHandleCmd_t; 357 358/** \brief the data structure of Get Device Handle Command 359 * 360 * use to describe MPI GET DEVIDE HANDLE Command (64 bytes) 361 * 362 */ 363typedef struct agsaGetDevHandleCmd_s { 364 bit32 tag; 365 bit32 DevADevTMaxDIDportId; 366 bit32 skipCount; 367 bit32 reserved[12]; 368} agsaGetDevHandleCmd_t; 369 370/** \brief the data structure of SMP Request Command 371 * 372 * use to describe MPI SMP REQUEST Command (64 bytes) 373 * 374 */ 375 376typedef struct agsaSMPCmd_s { 377 bit32 tag; 378 bit32 deviceId; 379 bit32 IR_IP_OV_res_phyId_DPdLen_res; 380 /* Bits [0] - IR */ 381 /* Bits [1] - IP */ 382 /* Bits [15:2] - Reserved */ 383 /* Bits [23:16] - Len */ 384 /* Bits [31:24] - Reserved */ 385 bit32 SMPCmd[12]; 386} agsaSMPCmd_t; 387 388 389typedef struct agsaSMPCmd_V_s { 390 bit32 tag; /* 1 */ 391 bit32 deviceId; /* 2 */ 392 bit32 IR_IP_OV_res_phyId_DPdLen_res;/* 3 */ 393 /* Bits [0] - IR */ 394 /* Bits [1] - IP */ 395 /* Bits [15:2] - Reserved */ 396 /* Bits [23:16] - Len */ 397 /* Bits [31:24] - Reserved */ 398 bit32 SMPHDR; /* 4 */ 399 bit32 SMP3_0; /* 5 */ 400 bit32 SMP7_4; /* 6 */ 401 bit32 SMP11_8; /* 7 */ 402 bit32 IndirL_SMPRF15_12; /* 8 */ 403 bit32 IndirH_or_SMPRF19_16; /* 9 */ 404 bit32 IndirLen_or_SMPRF23_20; /* 10 */ 405 bit32 R_or_SMPRF27_24; /* 11 */ 406 bit32 ISRAL_or_SMPRF31_28; /* 12 */ 407 bit32 ISRAH_or_SMPRF35_32; /* 13 */ 408 bit32 ISRL_or_SMPRF39_36; /* 14 */ 409 bit32 R_or_SMPRF43_40; /* 15 */ 410} agsaSMPCmd_V_t; 411 412/** \brief the data structure of SMP Abort Command 413 * 414 * use to describe MPI SMP Abort Command (64 bytes) 415 * 416 */ 417typedef struct agsaSMPAbortCmd_s { 418 bit32 tag; 419 bit32 deviceId; 420 bit32 HTagAbort; 421 bit32 Scp; 422 bit32 reserved[11]; 423} agsaSMPAbortCmd_t; 424 425/** \brief the data structure of SATA Start Command 426 * 427 * use to describe MPI SATA Start Command (64 bytes) 428 * 429 */ 430typedef struct agsaSATAStartCmd_s { 431 bit32 tag; /* 1 */ 432 bit32 deviceId; /* 2 */ 433 bit32 dataLen; /* 3 */ 434 bit32 optNCQTagataProt; /* 4 */ 435 agsaFisRegHostToDevice_t sataFis; /* 5 6 7 8 9 */ 436 bit32 reserved1; /* 10 */ 437 bit32 reserved2; /* 11 */ 438 bit32 AddrLow0; /* 12 */ 439 bit32 AddrHi0; /* 13 */ 440 bit32 Len0; /* 14 */ 441 bit32 E0; /* 15 */ 442 bit32 ATAPICDB[4]; /* 16-19 */ 443} agsaSATAStartCmd_t; 444 445typedef struct agsaSATAEncryptStartCmd_s 446{ 447 bit32 tag; /* 1 */ 448 bit32 IniDeviceId; /* 2 */ 449 bit32 dataLen; /* 3 */ 450 bit32 optNCQTagataProt; /* 4 */ 451 agsaFisRegHostToDevice_t sataFis; /* 5 6 7 8 9 */ 452 bit32 reserved1; /* 10 */ 453 bit32 Res_EPL_DESCL; /* 11 */ 454 bit32 resSKIPBYTES; /* 12 */ 455 bit32 Res_DPL_DESCL_NDPLR; /* 13 DIF per LA Address lo if DPLE is 1 */ 456 bit32 Res_EDPL_DESCH; /* 14 DIF per LA Address hi if DPLE is 1 */ 457 bit32 DIF_flags; /* 15 */ 458 bit32 udt; /* 16 */ 459 bit32 udtReplacementLo; /* 17 */ 460 bit32 udtReplacementHi; /* 18 */ 461 bit32 DIF_seed; /* 19 */ 462 bit32 encryptFlagsLo; /* 20 */ 463 bit32 encryptFlagsHi; /* 21 */ 464 bit32 keyTagLo; /* 22 */ 465 bit32 keyTagHi; /* 23 */ 466 bit32 tweakVal_W0; /* 24 */ 467 bit32 tweakVal_W1; /* 25 */ 468 bit32 tweakVal_W2; /* 26 */ 469 bit32 tweakVal_W3; /* 27 */ 470 bit32 AddrLow0; /* 28 */ 471 bit32 AddrHi0; /* 29 */ 472 bit32 Len0; /* 30 */ 473 bit32 E0; /* 31 */ 474} agsaSATAEncryptStartCmd_t; 475 476/** \brief the data structure of SATA Abort Command 477 * 478 * use to describe MPI SATA Abort Command (64 bytes) 479 * 480 */ 481typedef struct agsaSATAAbortCmd_s { 482 bit32 tag; 483 bit32 deviceId; 484 bit32 HTagAbort; 485 bit32 abortAll; 486 bit32 reserved[11]; 487} agsaSATAAbortCmd_t; 488 489/** \brief the data structure of Local PHY Control Command 490 * 491 * use to describe MPI LOCAL PHY CONTROL Command (64 bytes) 492 * 493 */ 494typedef struct agsaLocalPhyCntrlCmd_s { 495 bit32 tag; 496 bit32 phyOpPhyId; 497 bit32 reserved1[14]; 498} agsaLocalPhyCntrlCmd_t; 499 500/** \brief the data structure of Get Device Info Command 501 * 502 * use to describe MPI GET DEVIDE INFO Command (64 bytes) 503 * 504 */ 505typedef struct agsaGetDevInfoCmd_s { 506 bit32 tag; 507 bit32 DeviceId; 508 bit32 reserved[13]; 509} agsaGetDevInfoCmd_t; 510 511/** \brief the data structure of HW Reset Command 512 * 513 * use to describe MPI HW Reset Command (64 bytes) 514 * 515 */ 516typedef struct agsaHWResetCmd_s { 517 bit32 option; 518 bit32 reserved[14]; 519} agsaHWResetCmd_t; 520 521/** \brief the data structure of Firmware download 522 * 523 * use to describe MPI FW DOWNLOAD Command (64 bytes) 524 */ 525typedef struct agsaFwFlashUpdate_s { 526 bit32 tag; 527 bit32 curImageOffset; 528 bit32 curImageLen; 529 bit32 totalImageLen; 530 bit32 reserved0[7]; 531 bit32 SGLAL; 532 bit32 SGLAH; 533 bit32 Len; 534 bit32 extReserved; 535} agsaFwFlashUpdate_t; 536 537 538/** \brief the data structure EXT Flash Op 539 * 540 * use to describe Extented Flash Operation Command (128 bytes) 541 */ 542typedef struct agsaFwFlashOpExt_s { 543 bit32 tag; 544 bit32 Command; 545 bit32 PartOffset; 546 bit32 DataLength; 547 bit32 Reserved0[7]; 548 bit32 SGLAL; 549 bit32 SGLAH; 550 bit32 Len; 551 bit32 E_sgl; 552 bit32 Reserved[15]; 553} agsaFwFlashOpExt_t; 554 555/** \brief the data structure EXT Flash Op 556 * 557 * use to describe Extented Flash Operation Command (64 bytes) 558 */ 559typedef struct agsaFwFlashOpExtRsp_s { 560 bit32 tag; 561 bit32 Command; 562 bit32 Status; 563 bit32 Epart_Size; 564 bit32 EpartSectSize; 565 bit32 Reserved[10]; 566} agsaFwFlashOpExtRsp_t; 567 568 569#define FWFLASH_IOMB_RESERVED_LEN 0x07 570 571#ifdef SPC_ENABLE_PROFILE 572typedef struct agsaFwProfileIOMB_s { 573 bit32 tag; 574 bit32 tcid_processor_cmd; 575 bit32 codeStartAdd; 576 bit32 codeEndAdd; 577 bit32 reserved0[7]; 578 bit32 SGLAL; 579 bit32 SGLAH; 580 bit32 Len; 581 bit32 extReserved; 582} agsaFwProfileIOMB_t; 583#define FWPROFILE_IOMB_RESERVED_LEN 0x07 584#endif 585/** \brief the data structure of GPIO Commannd 586 * 587 * use to describe MPI GPIO Command (64 bytes) 588 */ 589typedef struct agsaGPIOCmd_s { 590 bit32 tag; 591 bit32 eOBIDGeGsGrGw; 592 bit32 GpioWrMsk; 593 bit32 GpioWrVal; 594 bit32 GpioIe; 595 bit32 OT11_0; 596 bit32 OT19_12; /* reserved for SPCv controller */ 597 bit32 GPIEVChange; 598 bit32 GPIEVRise; 599 bit32 GPIEVFall; 600 bit32 reserved[5]; 601} agsaGPIOCmd_t; 602 603 604#define GPIO_GW_BIT 0x1 605#define GPIO_GR_BIT 0x2 606#define GPIO_GS_BIT 0x4 607#define GPIO_GE_BIT 0x8 608 609/** \brief the data structure of SAS Diagnostic Start/End Command 610 * 611 * use to describe MPI SAS Diagnostic Start/End Command (64 bytes) 612 */ 613typedef struct agsaSASDiagStartEndCmd_s { 614 bit32 tag; 615 bit32 OperationPhyId; 616 bit32 reserved[13]; 617} agsaSASDiagStartEndCmd_t; 618 619/** \brief the data structure of SAS Diagnostic Execute Command 620 * 621 * use to describe MPI SAS Diagnostic Execute Command for SPCv (128 bytes) 622 */ 623typedef struct agsaSASDiagExecuteCmd_s { 624 bit32 tag; /* 1 */ 625 bit32 CmdTypeDescPhyId;/* 2 */ 626 bit32 Pat1Pat2; /* 3 */ 627 bit32 Threshold; /* 4 */ 628 bit32 CodePatErrMsk; /* 5 */ 629 bit32 Pmon; /* 6 */ 630 bit32 PERF1CTL; /* 7 */ 631 bit32 THRSHLD1; /* 8 */ 632 bit32 reserved[23]; /* 9 31 */ 633} agsaSASDiagExecuteCmd_t; 634 635 636/** \brief the data structure of SAS Diagnostic Execute Command 637 * 638 * use to describe MPI SAS Diagnostic Execute Command for SPC (64 bytes) 639 */ 640typedef struct agsa_SPC_SASDiagExecuteCmd_s { 641 bit32 tag; /* 1 */ 642 bit32 CmdTypeDescPhyId;/* 2 */ 643 bit32 Pat1Pat2; /* 3 */ 644 bit32 Threshold; /* 4 */ 645 bit32 CodePatErrMsk; /* 5 */ 646 bit32 Pmon; /* 6 */ 647 bit32 PERF1CTL; /* 7 */ 648 bit32 reserved[8]; /* 8 15 */ 649} agsa_SPC_SASDiagExecuteCmd_t; 650#define SAS_DIAG_PARAM_BYTES 24 651 652 653/** \brief the data structure of SSP TGT IO Start Command 654 * 655 * use to describe MPI SSP TGT IO Start Command (64 bytes) 656 * 657 */ 658typedef struct agsaSSPTgtIOStartCmd_s { 659 bit32 tag; /* 1 */ 660 bit32 deviceId; /* 2 */ 661 bit32 dataLen; /* 3 */ 662 bit32 dataOffset; /* 4 */ 663 bit32 INITagAgrDir; /* 5 */ 664 bit32 reserved; /* 6 */ 665 bit32 DIF_flags; /* 7 */ 666 bit32 udt; /* 8 */ 667 bit32 udtReplacementLo; /* 9 */ 668 bit32 udtReplacementHi; /* 10 */ 669 bit32 DIF_seed; /* 11 */ 670 bit32 AddrLow0; /* 12 */ 671 bit32 AddrHi0; /* 13 */ 672 bit32 Len0; /* 14 */ 673 bit32 E0; /* 15 */ 674} agsaSSPTgtIOStartCmd_t; 675 676/** \brief the data structure of SSP TGT Response Start Command 677 * 678 * use to describe MPI SSP TGT Response Start Command (64 bytes) 679 * 680 */ 681typedef struct agsaSSPTgtRspStartCmd_s { 682 bit32 tag; 683 bit32 deviceId; 684 bit32 RspLen; 685 bit32 INITag_IP_AN; 686 bit32 reserved[7]; 687 bit32 AddrLow0; 688 bit32 AddrHi0; 689 bit32 Len0; 690 bit32 E0; 691} agsaSSPTgtRspStartCmd_t; 692 693/** \brief the data structure of Device Handle Accept Command 694 * 695 * use to describe MPI Device Handle Accept Command (64 bytes) 696 * 697 */ 698typedef struct agsaDevHandleAcceptCmd_s { 699 bit32 tag; 700 bit32 Ctag; 701 bit32 deviceId; 702 bit32 DevA_MCN_R_R_HA_ITNT; 703 bit32 reserved[11]; 704} agsaDevHandleAcceptCmd_t; 705 706/** \brief the data structure of SAS HW Event Ack Command 707 * 708 * use to describe MPI SAS HW Event Ack Command (64 bytes) 709 * 710 */ 711typedef struct agsaSASHwEventAckCmd_s { 712 bit32 tag; 713 bit32 sEaPhyIdPortId; 714 bit32 Param0; 715 bit32 Param1; 716 bit32 reserved[11]; 717} agsaSASHwEventAckCmd_t; 718 719/** \brief the data structure of Get Time Stamp Command 720 * 721 * use to describe MPI Get Time Stamp Command (64 bytes) 722 * 723 */ 724typedef struct agsaGetTimeStampCmd_s { 725 bit32 tag; 726 bit32 reserved[14]; 727} agsaGetTimeStampCmd_t; 728 729/** \brief the data structure of Port Control Command 730 * 731 * use to describe MPI Port Control Command (64 bytes) 732 * 733 */ 734typedef struct agsaPortControlCmd_s { 735 bit32 tag; 736 bit32 portOPPortId; 737 bit32 Param0; 738 bit32 Param1; 739 bit32 reserved[11]; 740} agsaPortControlCmd_t; 741 742/** \brief the data structure of Set NVM Data Command 743 * 744 * use to describe MPI Set NVM Data Command (64 bytes) 745 * 746 */ 747typedef struct agNVMIndirect_s { 748 bit32 signature; 749 bit32 reserved[7]; 750 bit32 ISglAL; 751 bit32 ISglAH; 752 bit32 ILen; 753 bit32 reserved1; 754} agNVMIndirect_t; 755 756typedef union agsaSetNVMData_s { 757 bit32 NVMData[12]; 758 agNVMIndirect_t indirectData; 759} agsaSetNVMData_t; 760 761typedef struct agsaSetNVMDataCmd_s { 762 bit32 tag; 763 bit32 LEN_IR_VPDD; 764 bit32 VPDOffset; 765 agsaSetNVMData_t Data; 766} agsaSetNVMDataCmd_t; 767 768/** \brief the data structure of Get NVM Data Command 769 * 770 * use to describe MPI Get NVM Data Command (64 bytes) 771 * 772 */ 773typedef struct agsaGetNVMDataCmd_s { 774 bit32 tag; 775 bit32 LEN_IR_VPDD; 776 bit32 VPDOffset; 777 bit32 reserved[8]; 778 bit32 respAddrLo; 779 bit32 respAddrHi; 780 bit32 respLen; 781 bit32 reserved1; 782} agsaGetNVMDataCmd_t; 783 784#define TWI_DEVICE 0x0 785#define C_SEEPROM 0x1 786#define VPD_FLASH 0x4 787#define AAP1_RDUMP 0x5 788#define IOP_RDUMP 0x6 789#define EXPAN_ROM 0x7 790 791#define DIRECT_MODE 0x0 792#define INDIRECT_MODE 0x1 793 794#define IRMode 0x80000000 795#define IPMode 0x80000000 796#define NVMD_TYPE 0x0000000F 797#define NVMD_STAT 0x0000FFFF 798#define NVMD_LEN 0xFF000000 799 800#define TWI_DEVICE 0x0 801#define SEEPROM 0x1 802 803/** \brief the data structure of Set Device State Command 804 * 805 * use to describe MPI Set Device State Command (64 bytes) 806 * 807 */ 808typedef struct agsaSetDeviceStateCmd_s { 809 bit32 tag; 810 bit32 deviceId; 811 bit32 NDS; 812 bit32 reserved[12]; 813} agsaSetDeviceStateCmd_t; 814 815#define DS_OPERATIONAL 0x01 816#define DS_IN_RECOVERY 0x03 817#define DS_IN_ERROR 0x04 818#define DS_NON_OPERATIONAL 0x07 819 820/** \brief the data structure of Get Device State Command 821 * 822 * use to describe MPI Get Device State Command (64 bytes) 823 * 824 */ 825typedef struct agsaGetDeviceStateCmd_s { 826 bit32 tag; 827 bit32 deviceId; 828 bit32 reserved[13]; 829} agsaGetDeviceStateCmd_t; 830 831/** \brief the data structure of Set Device Info Command 832 * 833 * use to describe MPI OPC_INB_SET_DEV_INFO (0x02c) Command (64 bytes) 834 * 835 */ 836typedef struct agsaSetDevInfoCmd_s { 837 bit32 tag; 838 bit32 deviceId; 839 bit32 SA_SR_SI; 840 bit32 DEVA_MCN_R_ITNT; 841 bit32 reserved[11]; 842} agsaSetDevInfoCmd_t; 843 844#define SET_DEV_INFO_V_DW3_MASK 0x0000003F 845#define SET_DEV_INFO_V_DW4_MASK 0xFF07FFFF 846#define SET_DEV_INFO_SPC_DW3_MASK 0x7 847#define SET_DEV_INFO_SPC_DW4_MASK 0x003FFFF 848 849#define SET_DEV_INFO_V_DW3_SM_SHIFT 3 850#define SET_DEV_INFO_V_DW3_SA_SHIFT 2 851#define SET_DEV_INFO_V_DW3_SR_SHIFT 1 852#define SET_DEV_INFO_V_DW3_SI_SHIFT 0 853 854#define SET_DEV_INFO_V_DW4_MCN_SHIFT 24 855#define SET_DEV_INFO_V_DW4_AWT_SHIFT 17 856#define SET_DEV_INFO_V_DW4_RETRY_SHIFT 16 857#define SET_DEV_INFO_V_DW4_ITNEXUS_SHIFT 0 858 859/** \brief the data structure of SAS Re_Initialize Command 860 * 861 * use to describe MPI SAS RE_INITIALIZE Command (64 bytes) 862 * 863 */ 864typedef struct agsaSasReInitializeCmd_s { 865 bit32 tag; 866 bit32 setFlags; 867 bit32 MaxPorts; 868 bit32 openRejReCmdData; 869 bit32 sataHOLTMO; 870 bit32 reserved[10]; 871} agsaSasReInitializeCmd_t; 872 873 874/** \brief the data structure of SGPIO Command 875 * 876 * use to describe MPI serial GPIO Command (64 bytes) 877 * 878 */ 879typedef struct agsaSGpioCmd_s { 880 bit32 tag; 881 bit32 regIndexRegTypeFunctionFrameType; 882 bit32 regCount; 883 bit32 writeData[OSSA_SGPIO_MAX_WRITE_DATA_COUNT]; 884} agsaSGpioCmd_t; 885 886/** \brief the data structure of PCIE Diagnostic Command 887 * 888 * use to describe MPI PCIE Diagnostic Command for SPCv (128 bytes) 889 * 890 */ 891typedef struct agsaPCIeDiagExecuteCmd_s { 892 bit32 tag; /* 1 */ 893 bit32 CmdTypeDesc; /* 2 */ 894 bit32 UUM_EDA; /* 3 */ 895 bit32 UDTR1_UDT0; /* 4 */ 896 bit32 UDT5_UDT2; /* 5 */ 897 bit32 UDTR5_UDTR2; /* 6 */ 898 bit32 Res_IOS; /* 7 */ 899 bit32 rdAddrLower; /* 8 */ 900 bit32 rdAddrUpper; /* 9 */ 901 bit32 wrAddrLower; /* 10 */ 902 bit32 wrAddrUpper; /* 11 */ 903 bit32 len; /* 12 */ 904 bit32 pattern; /* 13 */ 905 bit32 reserved2[2]; /* 14 15 */ 906 bit32 reserved3[16]; /* 15 31 */ 907} agsaPCIeDiagExecuteCmd_t; 908 909 910/** \brief the data structure of PCI Diagnostic Command for SPC 911 * 912 * use to describe MPI PCI Diagnostic Command for SPC (64 bytes) 913 * 914 */ 915typedef struct agsa_SPC_PCIDiagExecuteCmd_s { 916 bit32 tag; 917 bit32 CmdTypeDesc; 918 bit32 reserved1[5]; 919 bit32 rdAddrLower; 920 bit32 rdAddrUpper; 921 bit32 wrAddrLower; 922 bit32 wrAddrUpper; 923 bit32 len; 924 bit32 pattern; 925 bit32 reserved2[2]; 926} agsa_SPC_PCIDiagExecuteCmd_t; 927 928/** \brief the data structure of GET DFE Data Command 929 * 930 * use to describe GET DFE Data Command for SPCv (128 bytes) 931 * 932 */ 933typedef struct agsaGetDDEFDataCmd_s { 934 bit32 tag; /* 1 */ 935 bit32 reserved_In_Ln;/* 2 */ 936 bit32 MCNT; /* 3 */ 937 bit32 reserved1[3]; /* 4 - 6 */ 938 bit32 Buf_AddrL; /* 7 */ 939 bit32 Buf_AddrH; /* 8 */ 940 bit32 Buf_Len; /* 9 */ 941 bit32 E_reserved; /* 10 */ 942 bit32 reserved2[21]; /* 11 - 31 */ 943} agsaGetDDEFDataCmd_t; 944 945 946/*********************************************** 947 * outbound IOMBs 948 ***********************************************/ 949/** \brief the data structure of Echo Response 950 * 951 * use to describe MPI Echo Response (64 bytes) 952 * 953 */ 954typedef struct agsaEchoRsp_s { 955 bit32 tag; 956 bit32 payload[14]; 957} agsaEchoRsp_t; 958 959/** \brief the data structure of HW Event from Outbound 960 * 961 * use to describe MPI HW Event (64 bytes) 962 * 963 */ 964typedef struct agsaHWEvent_SPC_OUB_s { 965 bit32 LRStatusEventPhyIdPortId; 966 bit32 EVParam; 967 bit32 NpipPortState; 968 agsaSASIdentify_t sasIdentify; 969 agsaFisRegDeviceToHost_t sataFis; 970} agsaHWEvent_SPC_OUB_t; 971 972#define PHY_ID_BITS 0x000000F0 973#define LINK_RATE_MASK 0xF0000000 974#define STATUS_BITS 0x0F000000 975#define HW_EVENT_BITS 0x00FFFF00 976 977typedef struct agsaHWEvent_Phy_OUB_s { 978 bit32 tag; 979 bit32 Status; 980 bit32 ReservedPhyId; 981} agsaHWEvent_Phy_OUB_t; 982 983/** \brief the data structure of HW Event from Outbound 984 * 985 * use to describe MPI HW Event (64 bytes) 986 * 987 */ 988typedef struct agsaHWEvent_V_OUB_s { 989 bit32 LRStatEventPortId; 990 bit32 EVParam; 991 bit32 RsvPhyIdNpipRsvPortState; 992 agsaSASIdentify_t sasIdentify; 993 agsaFisRegDeviceToHost_t sataFis; 994} agsaHWEvent_V_OUB_t; 995 996#define PHY_ID_V_BITS 0x00FF0000 997#define NIPP_V_BITS 0x0000FF00 998 999 1000 1001/** \brief the data structure of SSP Completion Response 1002 * 1003 * use to describe MPI SSP Completion Response (1024 bytes) 1004 * 1005 */ 1006typedef struct agsaSSPCompletionRsp_s { 1007 bit32 tag; 1008 bit32 status; 1009 bit32 param; 1010 bit32 SSPTag; 1011 agsaSSPResponseInfoUnit_t SSPrsp; 1012 bit32 respData; 1013 bit32 senseData[5]; 1014 bit32 respData1[239]; 1015} agsaSSPCompletionRsp_t; 1016 1017 1018/** \brief the data structure of SSP Completion DIF Response 1019 * 1020 * use to describe MPI SSP Completion DIF Response (1024 bytes) 1021 * 1022 */ 1023typedef struct agsaSSPCompletionDifRsp_s { 1024 bit32 tag; 1025 bit32 status; 1026 bit32 param; 1027 bit32 SSPTag; 1028 bit32 Device_Id; 1029 bit32 UpperLBA; 1030 bit32 LowerLBA; 1031 bit32 sasAddressHi; 1032 bit32 sasAddressLo; 1033 bit32 ExpectedCRCUDT01; 1034 bit32 ExpectedUDT2345; 1035 bit32 ActualCRCUDT01; 1036 bit32 ActualUDT2345; 1037 bit32 DIFErrDevID; 1038 bit32 ErrBoffsetEDataLen; 1039 bit32 EDATA_FRM; 1040 1041} agsaSSPCompletionDifRsp_t; 1042 1043 1044/* SSPTag bit fields Bits [31:16] */ 1045#define SSP_RESCV_BIT 0x00010000 /* Bits [16] */ 1046#define SSP_RESCV_PAD 0x00060000 /* Bits [18:17] */ 1047#define SSP_RESCV_PAD_SHIFT 17 1048#define SSP_AGR_S_BIT (1 << 19) /* Bits [19] */ 1049 1050/** \brief the data structure of SMP Completion Response 1051 * 1052 * use to describe MPI SMP Completion Response (1024 bytes) 1053 * 1054 */ 1055typedef struct agsaSMPCompletionRsp_s { 1056 bit32 tag; 1057 bit32 status; 1058 bit32 param; 1059 bit32 SMPrsp[252]; 1060} agsaSMPCompletionRsp_t; 1061 1062/** \brief the data structure of Deregister Device Response 1063 * 1064 * use to describe MPI Deregister Device Response (64 bytes) 1065 * 1066 */ 1067typedef struct agsaDeregDevHandleRsp_s { 1068 bit32 tag; 1069 bit32 status; 1070 bit32 deviceId; 1071 bit32 reserved[12]; 1072} agsaDeregDevHandleRsp_t; 1073 1074/** \brief the data structure of Get Device Handle Response 1075 * 1076 * use to describe MPI Get Device Handle Response (64 bytes) 1077 * 1078 */ 1079typedef struct agsaGetDevHandleRsp_s { 1080 bit32 tag; 1081 bit32 DeviceIdcPortId; 1082 bit32 deviceId[13]; 1083} agsaGetDevHandleRsp_t; 1084 1085#define DEVICE_IDC_BITS 0x00FFFF00 1086#define DEVICE_ID_BITS 0x00000FFF 1087 1088/** \brief the data structure of Local Phy Control Response 1089 * 1090 * use to describe MPI Local Phy Control Response (64 bytes) 1091 * 1092 */ 1093typedef struct agsaLocalPhyCntrlRsp_s { 1094 bit32 tag; 1095 bit32 phyOpId; 1096 bit32 status; 1097 bit32 reserved[12]; 1098} agsaLocalPhyCntrlRsp_t; 1099 1100#define LOCAL_PHY_OP_BITS 0x0000FF00 1101#define LOCAL_PHY_PHYID 0x000000FF 1102 1103/** \brief the data structure of DEVICE_REGISTRATION Response 1104 * 1105 * use to describe device registration response (64 bytes) 1106 * 1107 */ 1108typedef struct agsaDeviceRegistrationRsp_s { 1109 bit32 tag; 1110 bit32 status; 1111 bit32 deviceId; 1112 bit32 reserved[12]; 1113} agsaDeviceRegistrationRsp_t; 1114 1115 1116#define FAILURE_OUT_OF_RESOURCE 0x01 /* The device registration failed because the SPC 8x6G is running out of device handle resources. The parameter DEVICE_ID is not used. */ 1117#define FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /* The device registration failed because the SPC 8x6G detected an existing device handle with a similar SAS address. The parameter DEVICE_ID contains the existing DEVICE _ID assigned to the SAS device. */ 1118#define FAILURE_INVALID_PHY_ID 0x03 /* Only for directly-attached SATA registration. The device registration failed because the SPC 8x6G detected an invalid (out-of-range) PHY ID. */ 1119#define FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /* Only for directly-attached SATA registration. The device registration failed because the SPC 8x6G detected an already -registered PHY ID for a directly attached SATA drive. */ 1120#define FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /* PORT_ID specified in the REGISTER_DEVICE Command is out-of range (0-7). */ 1121#define FAILURE_PORT_NOT_VALID_STATE 0x06 /* The PORT_ID specified in the REGISTER_DEVICE Command is not in PORT_VALID state. */ 1122#define FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /* The device type, specified in the �S field in the REGISTER_DEVICE Command is not valid. */ 1123 1124#define MPI_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 /* The device registration failed because the SPCv controller is running out of device handle resources. The parameter DEVICE_ID is not used. */ 1125#define MPI_ERR_DEVICE_ALREADY_REGISTERED 0x1021 /* The device registration failed because the SPCv controller detected an existing device handle with the same SAS address. The parameter DEVICE_ID contains the existing DEVICE _ID assigned to the SAS device. */ 1126#define MPI_ERR_DEVICE_TYPE_NOT_VALID 0x1022 /* The device type, specified in the �S field in the REGISTER_DEVICE_HANDLE Command (page 274) is not valid. */ 1127#define MPI_ERR_PORT_INVALID_PORT_ID 0x1041 /* specified in the REGISTER_DEVICE_HANDLE Command (page 274) is invalid. i.e Out of supported range */ 1128#define MPI_ERR_PORT_STATE_NOT_VALID 0x1042 /* The PORT_ID specified in the REGISTER_DEVICE_HANDLE Command (page 274) is not in PORT_VALID state. */ 1129#define MPI_ERR_PORT_STATE_NOT_IN_USE 0x1043 1130#define MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 1131#define MPI_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045 1132#define MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /*MPI_ERR_DEVICE_ACCEPT_PENDING*/ 1133 1134 1135#define MPI_ERR_PHY_ID_INVALID 0x1061 /* Only for directly-attached SATA registration. The device registration failed because the SPCv controller detected an invalid (out-of-range) PHY ID. */ 1136#define MPI_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 /* Only for directly-attached SATA registration. The device registration failed because the SPCv controller detected an alreadyregistered PHY ID for a directly-attached SATA drive. */ 1137 1138 1139 1140 1141/** \brief the data structure of SATA Completion Response 1142 * 1143 * use to describe MPI SATA Completion Response (64 bytes) 1144 * 1145 */ 1146typedef struct agsaSATACompletionRsp_s { 1147 bit32 tag; 1148 bit32 status; 1149 bit32 param; 1150 bit32 FSATArsp; 1151 bit32 respData[11]; 1152} agsaSATACompletionRsp_t; 1153 1154/** \brief the data structure of SATA Event Response 1155 * 1156 * use to describe MPI SATA Event Response (64 bytes) 1157 * 1158 */ 1159typedef struct agsaSATAEventRsp_s { 1160 bit32 tag; 1161 bit32 event; 1162 bit32 portId; 1163 bit32 deviceId; 1164 bit32 reserved[11]; 1165} agsaSATAEventRsp_t; 1166 1167/** \brief the data structure of SSP Event Response 1168 * 1169 * use to describe MPI SSP Event Response (64 bytes) 1170 * 1171 */ 1172typedef struct agsaSSPEventRsp_s { 1173 bit32 tag; 1174 bit32 event; 1175 bit32 portId; 1176 bit32 deviceId; 1177 bit32 SSPTag; 1178 bit32 EVT_PARAM0_or_LBAH; 1179 bit32 EVT_PARAM1_or_LBAL; 1180 bit32 SAS_ADDRH; 1181 bit32 SAS_ADDRL; 1182 bit32 UDT1_E_UDT0_E_CRC_E; 1183 bit32 UDT5_E_UDT4_E_UDT3_E_UDT2_E; 1184 bit32 UDT1_A_UDT0_A_CRC_A; 1185 bit32 UDT5_A_UDT4_A_UDT3_A_UDT2_A; 1186 bit32 HW_DEVID_Reserved_DIF_ERR; 1187 bit32 EDATA_LEN_ERR_BOFF; 1188 bit32 EDATA_FRM; 1189} agsaSSPEventRsp_t; 1190 1191#define SSPTAG_BITS 0x0000FFFF 1192 1193/** \brief the data structure of Get Device Info Response 1194 * 1195 * use to describe MPI Get Device Info Response (64 bytes) 1196 * 1197 */ 1198typedef struct agsaGetDevInfoRspSpc_s { 1199 bit32 tag; 1200 bit32 status; 1201 bit32 deviceId; 1202 bit32 dTypeSrateSMPTOArPortID; 1203 bit32 FirstBurstSizeITNexusTimeOut; 1204 bit8 sasAddrHi[4]; 1205 bit8 sasAddrLow[4]; 1206 bit32 reserved[8]; 1207} agsaGetDevInfoRsp_t; 1208 1209#define SMPTO_BITS 0xFFFF 1210#define NEXUSTO_BITS 0xFFFF 1211#define FIRST_BURST 0xFFFF 1212#define FLAG_BITS 0x3 1213#define LINK_RATE_BITS 0xFF 1214#define DEV_TYPE_BITS 0x30000000 1215 1216/** \brief the data structure of Get Device Info Response V 1217 * 1218 * use to describe MPI Get Device Info Response (64 bytes) 1219 * 1220 */ 1221typedef struct agsaGetDevInfoRspV_s { 1222 bit32 tag; 1223 bit32 status; 1224 bit32 deviceId; 1225 bit32 ARSrateSMPTimeOutPortID; 1226 bit32 IRMcnITNexusTimeOut; 1227 bit8 sasAddrHi[4]; 1228 bit8 sasAddrLow[4]; 1229 bit32 reserved[8]; 1230} agsaGetDevInfoRspV_t; 1231 1232#define SMPTO_VBITS 0xFFFF 1233#define NEXUSTO_VBITS 0xFFFF 1234#define FIRST_BURST_MCN 0xF 1235#define FLAG_VBITS 0x3 1236#define LINK_RATE_VBITS 0xFF 1237#define DEV_TYPE_VBITS 0x10000000 1238 1239 1240/** \brief the data structure of Get Phy Profile Command IOMB V 1241 * 1242 */ 1243typedef struct agsaGetPhyProfileCmd_V_s { 1244 bit32 tag; 1245 bit32 Reserved_Ppc_SOP_PHYID; 1246 bit32 reserved[29]; 1247} agsaGetPhyProfileCmd_V_t; 1248 1249 1250/** \brief the data structure of Get Phy Profile Response IOMB V 1251 * 1252 */ 1253typedef struct agsaGetPhyProfileRspV_s { 1254 bit32 tag; 1255 bit32 status; 1256 bit32 Reserved_Ppc_SOP_PHYID; 1257 bit32 PageSpecificArea[12]; 1258} agsaGetPhyProfileRspV_t; 1259 1260/** \brief the data structure of Set Phy Profile Command IOMB V 1261 * 1262 */ 1263typedef struct agsaSetPhyProfileCmd_V_s { 1264 bit32 tag; 1265 bit32 Reserved_Ppc_SOP_PHYID; 1266 bit32 PageSpecificArea[29]; 1267} agsaSetPhyProfileCmd_V_t; 1268 1269/** \brief the data structure of GetVis Command IOMB V 1270 * OPC_OUB_GET_VIST_CAP_RSP 1271 */ 1272typedef struct agsaGetVHistCap_V_s { 1273 bit32 tag; 1274 bit32 Channel; 1275 bit32 NumBitLo; 1276 bit32 NumBitHi; 1277 bit32 reserved0; 1278 bit32 reserved1; 1279 bit32 PcieAddrLo; 1280 bit32 PcieAddrHi; 1281 bit32 ByteCount; 1282 bit32 reserved2[22]; 1283} agsaGetVHistCap_V_t; 1284 1285/** \brief the data structure of Set Phy Profile Response IOMB V 1286 * 1287 */ 1288typedef struct agsaSetPhyProfileRspV_s { 1289 bit32 tag; 1290 bit32 status; 1291 bit32 Reserved_Ppc_PHYID; 1292 bit32 PageSpecificArea[12]; 1293} agsaSetPhyProfileRspV_t; 1294 1295typedef struct agsaGetPhyInfoV_s { 1296 bit32 tag; 1297 bit32 Reserved_SOP_PHYID; 1298 bit32 reserved[28]; 1299} agsaGetPhyInfoV_t; 1300 1301 1302#define SPC_GET_SAS_PHY_ERR_COUNTERS 1 1303#define SPC_GET_SAS_PHY_ERR_COUNTERS_CLR 2 1304#define SPC_GET_SAS_PHY_BW_COUNTERS 3 1305 1306 1307/** \brief the data structure of FW_FLASH_UPDATE Response 1308 * 1309 * use to describe MPI FW_FLASH_UPDATE Response (64 bytes) 1310 * 1311 */ 1312typedef struct agsaFwFlashUpdateRsp_s { 1313 bit32 tag; 1314 bit32 status; 1315 bit32 reserved[13]; 1316} agsaFwFlashUpdateRsp_t; 1317 1318#ifdef SPC_ENABLE_PROFILE 1319typedef struct agsaFwProfileRsp_s { 1320 bit32 tag; 1321 bit32 status; 1322 bit32 len; 1323 bit32 reserved[12]; 1324} agsaFwProfileRsp_t; 1325#endif 1326/** \brief the data structure of GPIO Response 1327 * 1328 * use to describe MPI GPIO Response (64 bytes) 1329 */ 1330typedef struct agsaGPIORsp_s { 1331 bit32 tag; 1332 bit32 reserved[2]; 1333 bit32 GpioRdVal; 1334 bit32 GpioIe; 1335 bit32 OT11_0; 1336 bit32 OT19_12; 1337 bit32 GPIEVChange; 1338 bit32 GPIEVRise; 1339 bit32 GPIEVFall; 1340 bit32 reserved1[5]; 1341} agsaGPIORsp_t; 1342 1343/** \brief the data structure of GPIO Event 1344 * 1345 * use to describe MPI GPIO Event Response (64 bytes) 1346 */ 1347typedef struct agsaGPIOEvent_s { 1348 bit32 GpioEvent; 1349 bit32 reserved[14]; 1350} agsaGPIOEvent_t; 1351 1352/** \brief the data structure of GENERAL_EVENT Response 1353 * 1354 * use to describe MPI GENERNAL_EVENT Notification (64 bytes) 1355 * 1356 */ 1357typedef struct agsaGenernalEventRsp_s { 1358 bit32 status; 1359 bit32 inboundIOMB[14]; 1360} agsaGenernalEventRsp_t; 1361 1362/** \brief the data structure of SSP_ABORT Response 1363 * 1364 * use to describe MPI SSP_ABORT (64 bytes) 1365 * 1366 */ 1367typedef struct agsaSSPAbortRsp_s { 1368 bit32 tag; 1369 bit32 status; 1370 bit32 scp; 1371 bit32 reserved[12]; 1372} agsaSSPAbortRsp_t; 1373 1374/** \brief the data structure of SATA_ABORT Response 1375 * 1376 * use to describe MPI SATA_ABORT (64 bytes) 1377 * 1378 */ 1379typedef struct agsaSATAAbortRsp_s { 1380 bit32 tag; 1381 bit32 status; 1382 bit32 scp; 1383 bit32 reserved[12]; 1384} agsaSATAAbortRsp_t; 1385 1386/** \brief the data structure of SAS Diagnostic Start/End Response 1387 * 1388 * use to describe MPI SAS Diagnostic Start/End Response (64 bytes) 1389 * 1390 */ 1391typedef struct agsaSASDiagStartEndRsp_s { 1392 bit32 tag; 1393 bit32 Status; 1394 bit32 reserved[13]; 1395} agsaSASDiagStartEndRsp_t; 1396 1397/** \brief the data structure of SAS Diagnostic Execute Response 1398 * 1399 * use to describe MPI SAS Diagnostic Execute Response (64 bytes) 1400 * 1401 */ 1402typedef struct agsaSASDiagExecuteRsp_s { 1403 bit32 tag; 1404 bit32 CmdTypeDescPhyId; 1405 bit32 Status; 1406 bit32 ReportData; 1407 bit32 reserved[11]; 1408} agsaSASDiagExecuteRsp_t; 1409 1410/** \brief the data structure of General Event Notification Response 1411 * 1412 * use to describe MPI General Event Notification Response (64 bytes) 1413 * 1414 */ 1415typedef struct agsaGeneralEventRsp_s { 1416 bit32 status; 1417 bit32 inbIOMBpayload[14]; 1418} agsaGeneralEventRsp_t; 1419 1420#define GENERAL_EVENT_PAYLOAD 14 1421#define OPCODE_BITS 0x00000fff 1422 1423/* 1424Table 171 GENERAL_EVENT Notification Status Field Codes 1425Value Name Description 1426*/ 1427#define GEN_EVENT_IOMB_V_BIT_NOT_SET 0x01 /* INBOUND_ Inbound IOMB is received with the V bit in the IOMB header not set. */ 1428#define GEN_EVENT_INBOUND_IOMB_OPC_NOT_SUPPORTED 0x02 /* Inbound IOMB is received with an unsupported OPC. */ 1429#define GEN_EVENT_IOMB_INVALID_OBID 0x03 /* INBOUND Inbound IOMB is received with an invalid OBID. */ 1430#define GEN_EVENT_DS_IN_NON_OPERATIONAL 0x39 /* DEVICE_HANDLE_ACCEPT command failed due to the device being in DS_NON_OPERATIONAL state. */ 1431#define GEN_EVENT_DS_IN_RECOVERY 0x3A /* DEVICE_HANDLE_ACCEPT command failed due to device being in DS_IN_RECOVERY state. */ 1432#define GEN_EVENT_DS_INVALID 0x49 /* DEVICE_HANDLE_ACCEPT command failed due to device being in DS_INVALID state. */ 1433 1434#define GEN_EVENT_IO_XFER_READ_COMPL_ERR 0x50 /* Indicates the PCIe Read Request to fetch one or more inbound IOMBs received 1435 a failed completion response. The first and second Dwords of the 1436 INBOUND IOMB field ( Dwords 2 and 3) contains information to identifying 1437 the location in the inbound queue where the error occurred. 1438 Dword 2 bits[15:0] contains the inbound queue number. 1439 Dword 2 bits[31:16] specifies how many consecutive IOMBs were affected 1440 by the failed DMA. 1441 Dword 3 specifies the Consumer Index [CI] of the inbound queue where 1442 the DMA operation failed.*/ 1443 1444/** \brief the data structure of SSP Request Received Notification 1445 * 1446 * use to describe MPI SSP Request Received Notification ( 1024 bytes) 1447 * 1448 */ 1449typedef struct agsaSSPReqReceivedNotify_s { 1450 bit32 deviceId; 1451 bit32 iniTagSSPIul; 1452 bit32 frameTypeHssa; 1453 bit32 TlrHdsa; 1454 bit32 SSPIu[251]; 1455} agsaSSPReqReceivedNotify_t; 1456 1457#define SSPIUL_BITS 0x0000FFFF 1458#define INITTAG_BITS 0x0000FFFF 1459#define FRAME_TYPE 0x000000FF 1460#define TLR_BITS 0x00000300 1461 1462/** \brief the data structure of Device Handle Arrived Notification 1463 * 1464 * use to describe MPI Device Handle Arrived Notification ( 64 bytes) 1465 * 1466 */ 1467typedef struct agsaDeviceHandleArrivedNotify_s { 1468 bit32 CTag; 1469 bit32 HostAssignedIdFwdDeviceId; 1470 bit32 ProtConrPortId; 1471 bit8 sasAddrHi[4]; 1472 bit8 sasAddrLow[4]; 1473 bit32 reserved[10]; 1474 1475} agsaDeviceHandleArrivedNotify_t; 1476 1477 1478#define Conrate_V_MASK 0x0000F000 1479#define Conrate_V_SHIFT 12 1480#define Conrate_SPC_MASK 0x0000F000 1481#define Conrate_SPC_SHIFT 4 1482 1483#define Protocol_SPC_MASK 0x00000700 1484#define Protocol_SPC_SHIFT 8 1485#define Protocol_SPC_MASK 0x00000700 1486#define Protocol_SPC_SHIFT 8 1487 1488#define PortId_V_MASK 0xFF 1489#define PortId_SPC_MASK 0x0F 1490 1491#define PROTOCOL_BITS 0x00000700 1492#define PROTOCOL_SHIFT 8 1493 1494#define SHIFT_REG_64K_MASK 0xffff0000 1495#define SHIFT_REG_BIT_SHIFT 8 1496#define SPC_GSM_SM_OFFSET 0x400000 1497#define SPCV_GSM_SM_OFFSET 0x0 1498 1499/** \brief the data structure of Get Time Stamp Response 1500 * 1501 * use to describe MPI Get TIme Stamp Response ( 64 bytes) 1502 * 1503 */ 1504typedef struct agsaGetTimeStampRsp_s { 1505 bit32 tag; 1506 bit32 timeStampLower; 1507 bit32 timeStampUpper; 1508 bit32 reserved[12]; 1509} agsaGetTimeStampRsp_t; 1510 1511/** \brief the data structure of SAS HW Event Ack Response 1512 * 1513 * use to describe SAS HW Event Ack Response ( 64 bytes) 1514 * 1515 */ 1516typedef struct agsaSASHwEventAckRsp_s { 1517 bit32 tag; 1518 bit32 status; 1519 bit32 reserved[13]; 1520} agsaSASHwEventAckRsp_t; 1521 1522/** \brief the data structure of Port Control Response 1523 * 1524 * use to describe Port Control Response ( 64 bytes) 1525 * 1526 */ 1527typedef struct agsaPortControlRsp_s { 1528 bit32 tag; 1529 bit32 portOPPortId; 1530 bit32 status; 1531 bit32 rsvdPortState; 1532 bit32 reserved[11]; 1533} agsaPortControlRsp_t; 1534 1535/** \brief the data structure of SMP Abort Response 1536 * 1537 * use to describe SMP Abort Response ( 64 bytes) 1538 * 1539 */ 1540typedef struct agsaSMPAbortRsp_s { 1541 bit32 tag; 1542 bit32 status; 1543 bit32 scp; 1544 bit32 reserved[12]; 1545} agsaSMPAbortRsp_t; 1546 1547/** \brief the data structure of Get NVMD Data Response 1548 * 1549 * use to describe MPI Get NVMD Data Response (64 bytes) 1550 * 1551 */ 1552typedef struct agsaGetNVMDataRsp_s { 1553 bit32 tag; 1554 bit32 iRTdaBnDpsAsNvm; 1555 bit32 DlenStatus; 1556 bit32 NVMData[12]; 1557} agsaGetNVMDataRsp_t; 1558 1559/** \brief the data structure of Set NVMD Data Response 1560 * 1561 * use to describe MPI Set NVMD Data Response (64 bytes) 1562 * 1563 */ 1564typedef struct agsaSetNVMDataRsp_s { 1565 bit32 tag; 1566 bit32 iPTdaBnDpsAsNvm; 1567 bit32 status; 1568 bit32 reserved[12]; 1569} agsaSetNVMDataRsp_t; 1570 1571/** \brief the data structure of Device Handle Removal 1572 * 1573 * use to describe MPI Device Handle Removel Notification (64 bytes) 1574 * 1575 */ 1576typedef struct agsaDeviceHandleRemoval_s { 1577 bit32 portId; 1578 bit32 deviceId; 1579 bit32 reserved[13]; 1580} agsaDeviceHandleRemoval_t; 1581 1582/** \brief the data structure of Set Device State Response 1583 * 1584 * use to describe MPI Set Device State Response (64 bytes) 1585 * 1586 */ 1587typedef struct agsaSetDeviceStateRsp_s { 1588 bit32 tag; 1589 bit32 status; 1590 bit32 deviceId; 1591 bit32 pds_nds; 1592 bit32 reserved[11]; 1593} agsaSetDeviceStateRsp_t; 1594 1595#define NDS_BITS 0x0F 1596#define PDS_BITS 0xF0 1597 1598/** \brief the data structure of Get Device State Response 1599 * 1600 * use to describe MPI Get Device State Response (64 bytes) 1601 * 1602 */ 1603typedef struct agsaGetDeviceStateRsp_s { 1604 bit32 tag; 1605 bit32 status; 1606 bit32 deviceId; 1607 bit32 ds; 1608 bit32 reserved[11]; 1609} agsaGetDeviceStateRsp_t; 1610 1611/** \brief the data structure of Set Device Info Response 1612 * 1613 * use to describe MPI Set Device Info Response (64 bytes) 1614 * 1615 */ 1616typedef struct agsaSetDeviceInfoRsp_s { 1617 bit32 tag; 1618 bit32 status; 1619 bit32 deviceId; 1620 bit32 SA_SR_SI; 1621 bit32 A_R_ITNT; 1622 bit32 reserved[10]; 1623} agsaSetDeviceInfoRsp_t; 1624 1625/** \brief the data structure of SAS Re_Initialize Response 1626 * 1627 * use to describe MPI SAS RE_INITIALIZE Response (64 bytes) 1628 * 1629 */ 1630typedef struct agsaSasReInitializeRsp_s { 1631 bit32 tag; 1632 bit32 status; 1633 bit32 setFlags; 1634 bit32 MaxPorts; 1635 bit32 openRejReCmdData; 1636 bit32 sataHOLTMO; 1637 bit32 reserved[9]; 1638} agsaSasReInitializeRsp_t; 1639 1640/** \brief the data structure of SGPIO Response 1641 * 1642 * use to describe MPI serial GPIO Response IOMB (64 bytes) 1643 * 1644 */ 1645typedef struct agsaSGpioRsp_s { 1646 bit32 tag; 1647 bit32 resultFunctionFrameType; 1648 bit32 readData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; 1649} agsaSGpioRsp_t; 1650 1651 1652/** \brief the data structure of PCIe diag response 1653 * 1654 * use to describe PCIe diag response IOMB (64 bytes) 1655 * 1656 */ 1657 1658typedef struct agsaPCIeDiagExecuteRsp_s { 1659 bit32 tag; /* 1 */ 1660 bit32 CmdTypeDesc; /* 2 */ 1661 bit32 Status; /* 3 */ 1662 bit32 reservedDW4; /* 4 */ 1663 bit32 reservedDW5; /* 5 */ 1664 bit32 ERR_BLKH; /* 6 */ 1665 bit32 ERR_BLKL; /* 7 */ 1666 bit32 DWord8; /* 8 */ 1667 bit32 DWord9; /* 9 */ 1668 bit32 DWord10; /* 10 */ 1669 bit32 DWord11; /* 11 */ 1670 bit32 DIF_ERR; /* 12 */ 1671 bit32 reservedDW13; /* 13 */ 1672 bit32 reservedDW14; /* 14 */ 1673 bit32 reservedDW15; /* 15 */ 1674} agsaPCIeDiagExecuteRsp_t; 1675 1676/** \brief the data structure of PCI diag response 1677 * 1678 * use to describe PCI diag response IOMB for SPC (64 bytes) 1679 * 1680 */ 1681 1682typedef struct agsa_SPC_PCIeDiagExecuteRsp_s { 1683 bit32 tag; /* 1 */ 1684 bit32 CmdTypeDesc; /* 2 */ 1685 bit32 Status; /* 3 */ 1686 bit32 reserved[12]; /* 4 15 */ 1687} agsa_SPC_PCIeDiagExecuteRsp_t; 1688 1689/** \brief the data structure of GET DFE Data Response 1690 * 1691 * use to describe GET DFE Data Response for SPCv (64 bytes) 1692 * 1693 */ 1694typedef struct agsaGetDDEFDataRsp_s { 1695 bit32 tag; /* 1 */ 1696 bit32 status; /* 2 */ 1697 bit32 reserved_In_Ln;/* 3 */ 1698 bit32 MCNT; /* 4 */ 1699 bit32 NBT; /* 5 */ 1700 bit32 reserved[10]; /* 6 - 15 */ 1701} agsaGetDDEFDataRsp_t; 1702 1703/** \brief the data structure of GET Vis Data Response 1704 * 1705 * use to describe GET Vis Data Response for SPCv (64 bytes) 1706 * 1707 */ 1708typedef struct agsaGetVHistCapRsp_s { 1709 bit32 tag; /* 1 */ 1710 bit32 status; /* 2 */ 1711 bit32 channel; /* 3 */ 1712 bit32 BistLo; /* 4 */ 1713 bit32 BistHi; /* 5 */ 1714 bit32 BytesXfered; /* 6 */ 1715 bit32 PciLo; /* 7 */ 1716 bit32 PciHi; /* 8 */ 1717 bit32 PciBytecount; /* 9 */ 1718 bit32 reserved[5]; /* 10 - 15 */ 1719} agsaGetVHistCapRsp_t; 1720 1721typedef struct agsaSetControllerConfigCmd_s { 1722 bit32 tag; 1723 bit32 pageCode; 1724 bit32 configPage[13]; /* Page code specific fields */ 1725} agsaSetControllerConfigCmd_t; 1726 1727 1728typedef struct agsaSetControllerConfigRsp_s { 1729 bit32 tag; 1730 bit32 status; 1731 bit32 errorQualifierPage; 1732 bit32 reserved[12]; 1733} agsaSetControllerConfigRsp_t; 1734 1735typedef struct agsaGetControllerConfigCmd_s { 1736 bit32 tag; 1737 bit32 pageCode; 1738 bit32 INT_VEC_MSK0; 1739 bit32 INT_VEC_MSK1; 1740 bit32 reserved[11]; 1741} agsaGetControllerConfigCmd_t; 1742 1743typedef struct agsaGetControllerConfigRsp_s { 1744 bit32 tag; 1745 bit32 status; 1746 bit32 errorQualifier; 1747 bit32 configPage[12]; /* Page code specific fields */ 1748} agsaGetControllerConfigRsp_t; 1749 1750typedef struct agsaDekManagementCmd_s { 1751 bit32 tag; 1752 bit32 KEKIDX_Reserved_TBLS_DSOP; 1753 bit32 dekIndex; 1754 bit32 tableAddrLo; 1755 bit32 tableAddrHi; 1756 bit32 tableEntries; 1757 bit32 Reserved_DBF_TBL_SIZE; 1758} agsaDekManagementCmd_t; 1759 1760typedef struct agsaDekManagementRsp_s { 1761 bit32 tag; 1762 bit32 status; 1763 bit32 flags; 1764 bit32 dekIndex; 1765 bit32 errorQualifier; 1766 bit32 reserved[12]; 1767} agsaDekManagementRsp_t; 1768 1769typedef struct agsaKekManagementCmd_s { 1770 bit32 tag; 1771 bit32 NEWKIDX_CURKIDX_KBF_Reserved_SKNV_KSOP; 1772 bit32 reserved; 1773 bit32 kekBlob[12]; 1774} agsaKekManagementCmd_t; 1775 1776typedef struct agsaKekManagementRsp_s { 1777 bit32 tag; 1778 bit32 status; 1779 bit32 flags; 1780 bit32 errorQualifier; 1781 bit32 reserved[12]; 1782} agsaKekManagementRsp_t; 1783 1784 1785typedef struct agsaCoalSspComplCxt_s { 1786 bit32 tag; 1787 bit16 SSPTag; 1788 bit16 reserved; 1789} agsaCoalSspComplCxt_t; 1790 1791/** \brief the data structure of SSP Completion Response 1792 * 1793 * use to describe MPI SSP Completion Response (1024 bytes) 1794 * 1795 */ 1796typedef struct agsaSSPCoalescedCompletionRsp_s { 1797 bit32 coalescedCount; 1798 agsaCoalSspComplCxt_t sspComplCxt[1]; /* Open ended array */ 1799} agsaSSPCoalescedCompletionRsp_t; 1800 1801 1802/** \brief the data structure of SATA Completion Response 1803 * 1804 * use to describe MPI SATA Completion Response (1024 bytes) 1805 * 1806 */ 1807typedef struct agsaCoalStpComplCxt_s { 1808 bit32 tag; 1809 bit16 reserved; 1810} agsaCoalStpComplCxt_t; 1811 1812typedef struct agsaSATACoalescedCompletionRsp_s { 1813 bit32 coalescedCount; 1814 agsaCoalStpComplCxt_t stpComplCxt[1]; /* Open ended array */ 1815} agsaSATACoalescedCompletionRsp_t; 1816 1817 1818/** \brief the data structure of Operator Mangement Command 1819 * 1820 * use to describe OPR_MGMT Command (128 bytes) 1821 * 1822 */ 1823typedef struct agsaOperatorMangmentCmd_s{ 1824 bit32 tag; /* 1 */ 1825 bit32 OPRIDX_AUTIDX_R_KBF_PKT_OMO;/* 2 */ 1826 bit8 IDString_Role[32]; /* 3 10 */ 1827#ifndef HAILEAH_HOST_6G_COMPITIBILITY_FLAG 1828 agsaEncryptKekBlob_t Kblob; /* 11 22 */ 1829#endif 1830 bit32 reserved[8]; /* 23 31 */ 1831} agsaOperatorMangmentCmd_t; 1832 1833 1834/* 1835 * 1836 * use to describe OPR_MGMT Response (64 bytes) 1837 * 1838 */ 1839typedef struct agsaOperatorMangmentRsp_s { 1840 bit32 tag; /* 1 */ 1841 bit32 status; /* 2 */ 1842 bit32 OPRIDX_AUTIDX_R_OMO; /* 3 */ 1843 bit32 errorQualifier; /* 4 */ 1844 bit32 reserved[10]; /* 5 15 */ 1845} agsaOperatorMangmenRsp_t; 1846 1847/** \brief the data structure of Set Operator Command 1848 * 1849 * use to describe Set Operator Command (64 bytes) 1850 * 1851 */ 1852typedef struct agsaSetOperatorCmd_s{ 1853 bit32 tag; /* 1 */ 1854 bit32 OPRIDX_PIN_ACS; /* 2 */ 1855 bit32 cert[10]; /* 3 12 */ 1856 bit32 reserved[3]; /* 13 15 */ 1857} agsaSetOperatorCmd_t; 1858 1859/* 1860 * 1861 * use to describe Set Operator Response (64 bytes) 1862 * 1863 */ 1864typedef struct agsaSetOperatorRsp_s { 1865 bit32 tag; /* 1 */ 1866 bit32 status; /* 2 */ 1867 bit32 ERR_QLFR_OPRIDX_PIN_ACS;/* 3 */ 1868 bit32 reserved[12]; /* 4 15 */ 1869} agsaSetOperatorRsp_t; 1870 1871/** \brief the data structure of Get Operator Command 1872 * 1873 * use to describe Get Operator Command (64 bytes) 1874 * 1875 */ 1876typedef struct agsaGetOperatorCmd_s{ 1877 bit32 tag; /* 1 */ 1878 bit32 option; /* 2 */ 1879 bit32 OprBufAddrLo; /* 3 */ 1880 bit32 OprBufAddrHi; /* 4*/ 1881 bit32 reserved[11]; /*5 15*/ 1882} agsaGetOperatorCmd_t; 1883 1884/* 1885 * 1886 * use to describe Get Operator Response (64 bytes) 1887 * 1888 */ 1889typedef struct agsaGetOperatorRsp_s { 1890 bit32 tag; /* 1 */ 1891 bit32 status; /* 2 */ 1892 bit32 Num_Option; /* 3 */ 1893 bit32 IDString[8]; /* 4 11*/ 1894 bit32 reserved[4]; /* 12 15*/ 1895} agsaGetOperatorRsp_t; 1896 1897/* 1898 * 1899 * use to start Encryption BIST (128 bytes) 1900 * 0x105 1901 */ 1902typedef struct agsaEncryptBist_s { 1903 bit32 tag; /* 1 */ 1904 bit32 r_subop; /* 2 */ 1905 bit32 testDiscption[28]; /* 3 31 */ 1906} agsaEncryptBist_t; 1907 1908/* 1909 * 1910 * use to describe Encryption BIST Response (64 bytes) 1911 * 0x905 1912 */ 1913 1914typedef struct agsaEncryptBistRsp_s { 1915 bit32 tag; /* 1 */ 1916 bit32 status; /* 2 */ 1917 bit32 subop; /* 3 */ 1918 bit32 testResults[11]; /* 4 15 */ 1919} agsaEncryptBistRsp_t; 1920 1921/** \brief the data structure of DifEncOffload Command 1922 * 1923 * use to describe Set DifEncOffload Command (128 bytes) 1924 * 1925 */ 1926typedef struct agsaDifEncOffloadCmd_s{ 1927 bit32 tag; /* 1 */ 1928 bit32 option; /* 2 */ 1929 bit32 reserved[2]; /* 3-4 */ 1930 bit32 Src_Data_Len; /* 5 */ 1931 bit32 Dst_Data_Len; /* 6 */ 1932 bit32 flags; /* 7 */ 1933 bit32 UDTR01UDT01; /* 8 */ 1934 bit32 UDT2345; /* 9 */ 1935 bit32 UDTR2345; /* 10 */ 1936 bit32 DPLR0SecCnt_IOSeed; /* 11 */ 1937 bit32 DPL_Addr_Lo; /* 12 */ 1938 bit32 DPL_Addr_Hi; /* 13 */ 1939 bit32 KeyIndex_CMode_KTS_ENT_R; /* 14 */ 1940 bit32 EPLR0SecCnt_KS_ENSS; /* 15 */ 1941 bit32 keyTag_W0; /* 16 */ 1942 bit32 keyTag_W1; /* 17 */ 1943 bit32 tweakVal_W0; /* 18 */ 1944 bit32 tweakVal_W1; /* 19 */ 1945 bit32 tweakVal_W2; /* 20 */ 1946 bit32 tweakVal_W3; /* 21 */ 1947 bit32 EPL_Addr_Lo; /* 22 */ 1948 bit32 EPL_Addr_Hi; /* 23 */ 1949 agsaSgl_t SrcSgl; /* 24-27 */ 1950 agsaSgl_t DstSgl; /* 28-31 */ 1951} agsaDifEncOffloadCmd_t; 1952 1953/* 1954 * 1955 * use to describe DIF/Encryption Offload Response (32 bytes) 1956 * 0x910 1957 */ 1958typedef struct agsaDifEncOffloadRspV_s { 1959 bit32 tag; 1960 bit32 status; 1961 bit32 ExpectedCRCUDT01; 1962 bit32 ExpectedUDT2345; 1963 bit32 ActualCRCUDT01; 1964 bit32 ActualUDT2345; 1965 bit32 DIFErr; 1966 bit32 ErrBoffset; 1967} agsaDifEncOffloadRspV_t; 1968 1969#endif /*__SAMPIDEFS_H__ */ 1970