1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 * 30 */ 31 32#ifndef _PCIVAR_H_ 33#define _PCIVAR_H_ 34 35#include <sys/queue.h> 36#include <sys/eventhandler.h> 37 38/* some PCI bus constants */ 39#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 40#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 41#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 42 43typedef uint64_t pci_addr_t; 44 45/* Config registers for PCI-PCI and PCI-Cardbus bridges. */ 46struct pcicfg_bridge { 47 uint8_t br_seclat; 48 uint8_t br_subbus; 49 uint8_t br_secbus; 50 uint8_t br_pribus; 51 uint16_t br_control; 52}; 53 54/* Interesting values for PCI power management */ 55struct pcicfg_pp { 56 uint16_t pp_cap; /* PCI power management capabilities */ 57 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 58 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 59 uint8_t pp_data; /* conf. space addr. of PM data reg */ 60}; 61 62struct pci_map { 63 pci_addr_t pm_value; /* Raw BAR value */ 64 pci_addr_t pm_size; 65 uint16_t pm_reg; 66 STAILQ_ENTRY(pci_map) pm_link; 67}; 68 69struct vpd_readonly { 70 char keyword[2]; 71 char *value; 72 int len; 73}; 74 75struct vpd_write { 76 char keyword[2]; 77 char *value; 78 int start; 79 int len; 80}; 81 82struct pcicfg_vpd { 83 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 84 char vpd_cached; 85 char *vpd_ident; /* string identifier */ 86 int vpd_rocnt; 87 struct vpd_readonly *vpd_ros; 88 int vpd_wcnt; 89 struct vpd_write *vpd_w; 90}; 91 92/* Interesting values for PCI MSI */ 93struct pcicfg_msi { 94 uint16_t msi_ctrl; /* Message Control */ 95 uint8_t msi_location; /* Offset of MSI capability registers. */ 96 uint8_t msi_msgnum; /* Number of messages */ 97 int msi_alloc; /* Number of allocated messages. */ 98 uint64_t msi_addr; /* Contents of address register. */ 99 uint16_t msi_data; /* Contents of data register. */ 100 u_int msi_handlers; 101}; 102 103/* Interesting values for PCI MSI-X */ 104struct msix_vector { 105 uint64_t mv_address; /* Contents of address register. */ 106 uint32_t mv_data; /* Contents of data register. */ 107 int mv_irq; 108}; 109 110struct msix_table_entry { 111 u_int mte_vector; /* 1-based index into msix_vectors array. */ 112 u_int mte_handlers; 113}; 114 115struct pcicfg_msix { 116 uint16_t msix_ctrl; /* Message Control */ 117 uint16_t msix_msgnum; /* Number of messages */ 118 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 119 uint8_t msix_table_bar; /* BAR containing vector table. */ 120 uint8_t msix_pba_bar; /* BAR containing PBA. */ 121 uint32_t msix_table_offset; 122 uint32_t msix_pba_offset; 123 int msix_alloc; /* Number of allocated vectors. */ 124 int msix_table_len; /* Length of virtual table. */ 125 struct msix_table_entry *msix_table; /* Virtual table. */ 126 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 127 struct resource *msix_table_res; /* Resource containing vector table. */ 128 struct resource *msix_pba_res; /* Resource containing PBA. */ 129}; 130 131/* Interesting values for HyperTransport */ 132struct pcicfg_ht { 133 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 134 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 135 uint16_t ht_msictrl; /* MSI mapping control */ 136 uint64_t ht_msiaddr; /* MSI mapping base address */ 137}; 138 139/* Interesting values for PCI-express */ 140struct pcicfg_pcie { 141 uint8_t pcie_location; /* Offset of PCI-e capability registers. */ 142 uint8_t pcie_type; /* Device type. */ 143 uint16_t pcie_flags; /* Device capabilities register. */ 144 uint16_t pcie_device_ctl; /* Device control register. */ 145 uint16_t pcie_link_ctl; /* Link control register. */ 146 uint16_t pcie_slot_ctl; /* Slot control register. */ 147 uint16_t pcie_root_ctl; /* Root control register. */ 148 uint16_t pcie_device_ctl2; /* Second device control register. */ 149 uint16_t pcie_link_ctl2; /* Second link control register. */ 150 uint16_t pcie_slot_ctl2; /* Second slot control register. */ 151}; 152 153struct pcicfg_pcix { 154 uint16_t pcix_command; 155 uint8_t pcix_location; /* Offset of PCI-X capability registers. */ 156}; 157 158struct pcicfg_vf { 159 int index; 160}; 161 162struct pci_ea_entry { 163 int eae_bei; 164 uint32_t eae_flags; 165 uint64_t eae_base; 166 uint64_t eae_max_offset; 167 uint32_t eae_cfg_offset; 168 STAILQ_ENTRY(pci_ea_entry) eae_link; 169}; 170 171struct pcicfg_ea { 172 int ea_location; /* Structure offset in Configuration Header */ 173 STAILQ_HEAD(, pci_ea_entry) ea_entries; /* EA entries */ 174}; 175 176#define PCICFG_VF 0x0001 /* Device is an SR-IOV Virtual Function */ 177 178/* config header information common to all header types */ 179typedef struct pcicfg { 180 device_t dev; /* device which owns this */ 181 182 STAILQ_HEAD(, pci_map) maps; /* BARs */ 183 184 uint16_t subvendor; /* card vendor ID */ 185 uint16_t subdevice; /* card device ID, assigned by card vendor */ 186 uint16_t vendor; /* chip vendor ID */ 187 uint16_t device; /* chip device ID, assigned by chip vendor */ 188 189 uint16_t cmdreg; /* disable/enable chip and PCI options */ 190 uint16_t statreg; /* supported PCI features and error state */ 191 192 uint8_t baseclass; /* chip PCI class */ 193 uint8_t subclass; /* chip PCI subclass */ 194 uint8_t progif; /* chip PCI programming interface */ 195 uint8_t revid; /* chip revision ID */ 196 197 uint8_t hdrtype; /* chip config header type */ 198 uint8_t cachelnsz; /* cache line size in 4byte units */ 199 uint8_t intpin; /* PCI interrupt pin */ 200 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 201 202 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 203 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 204 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 205 206 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 207 uint8_t nummaps; /* actual number of PCI maps used */ 208 209 uint32_t domain; /* PCI domain */ 210 uint8_t bus; /* config space bus address */ 211 uint8_t slot; /* config space slot address */ 212 uint8_t func; /* config space function number */ 213 214 uint32_t flags; /* flags defined above */ 215 216 struct pcicfg_bridge bridge; /* Bridges */ 217 struct pcicfg_pp pp; /* Power management */ 218 struct pcicfg_vpd vpd; /* Vital product data */ 219 struct pcicfg_msi msi; /* PCI MSI */ 220 struct pcicfg_msix msix; /* PCI MSI-X */ 221 struct pcicfg_ht ht; /* HyperTransport */ 222 struct pcicfg_pcie pcie; /* PCI Express */ 223 struct pcicfg_pcix pcix; /* PCI-X */ 224 struct pcicfg_iov *iov; /* SR-IOV */ 225 struct pcicfg_vf vf; /* SR-IOV Virtual Function */ 226 struct pcicfg_ea ea; /* Enhanced Allocation */ 227} pcicfgregs; 228 229/* additional type 1 device config header information (PCI to PCI bridge) */ 230 231typedef struct { 232 pci_addr_t pmembase; /* base address of prefetchable memory */ 233 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 234 uint32_t membase; /* base address of memory window */ 235 uint32_t memlimit; /* topmost address of memory window */ 236 uint32_t iobase; /* base address of port window */ 237 uint32_t iolimit; /* topmost address of port window */ 238 uint16_t secstat; /* secondary bus status register */ 239 uint16_t bridgectl; /* bridge control register */ 240 uint8_t seclat; /* CardBus latency timer */ 241} pcih1cfgregs; 242 243/* additional type 2 device config header information (CardBus bridge) */ 244 245typedef struct { 246 uint32_t membase0; /* base address of memory window */ 247 uint32_t memlimit0; /* topmost address of memory window */ 248 uint32_t membase1; /* base address of memory window */ 249 uint32_t memlimit1; /* topmost address of memory window */ 250 uint32_t iobase0; /* base address of port window */ 251 uint32_t iolimit0; /* topmost address of port window */ 252 uint32_t iobase1; /* base address of port window */ 253 uint32_t iolimit1; /* topmost address of port window */ 254 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 255 uint16_t secstat; /* secondary bus status register */ 256 uint16_t bridgectl; /* bridge control register */ 257 uint8_t seclat; /* CardBus latency timer */ 258} pcih2cfgregs; 259 260extern uint32_t pci_numdevs; 261extern int pci_enable_aspm; 262 263struct pci_device_table { 264#if BYTE_ORDER == LITTLE_ENDIAN 265 uint16_t 266 match_flag_vendor:1, 267 match_flag_device:1, 268 match_flag_subvendor:1, 269 match_flag_subdevice:1, 270 match_flag_class:1, 271 match_flag_subclass:1, 272 match_flag_revid:1, 273 match_flag_unused:9; 274#else 275 uint16_t 276 match_flag_unused:9, 277 match_flag_revid:1, 278 match_flag_subclass:1, 279 match_flag_class:1, 280 match_flag_subdevice:1, 281 match_flag_subvendor:1, 282 match_flag_device:1, 283 match_flag_vendor:1; 284#endif 285 uint16_t vendor; 286 uint16_t device; 287 uint16_t subvendor; 288 uint16_t subdevice; 289 uint16_t class_id; 290 uint16_t subclass; 291 uint16_t revid; 292 uint16_t unused; 293 uintptr_t driver_data; 294 char *descr; 295}; 296 297#define PCI_DEV(v, d) \ 298 .match_flag_vendor = 1, .vendor = (v), \ 299 .match_flag_device = 1, .device = (d) 300#define PCI_SUBDEV(sv, sd) \ 301 .match_flag_subvendor = 1, .subvendor = (sv), \ 302 .match_flag_subdevice = 1, .subdevice = (sd) 303#define PCI_CLASS(x) \ 304 .match_flag_class = 1, .class_id = (x) 305#define PCI_SUBCLASS(x) \ 306 .match_flag_subclass = 1, .subclass = (x) 307#define PCI_REVID(x) \ 308 .match_flag_revid = 1, .revid = (x) 309#define PCI_DESCR(x) \ 310 .descr = (x) 311#define PCI_PNP_STR \ 312 "M16:mask;U16:vendor;U16:device;U16:subvendor;U16:subdevice;" \ 313 "U16:class;U16:subclass;U16:revid;" 314#define PCI_PNP_INFO(table) \ 315 MODULE_PNP_INFO(PCI_PNP_STR, pci, table, table, \ 316 sizeof(table) / sizeof(table[0])) 317 318const struct pci_device_table *pci_match_device(device_t child, 319 const struct pci_device_table *id, size_t nelt); 320#define PCI_MATCH(child, table) \ 321 pci_match_device(child, (table), nitems(table)); 322 323/* Only if the prerequisites are present */ 324#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 325struct pci_devinfo { 326 STAILQ_ENTRY(pci_devinfo) pci_links; 327 struct resource_list resources; 328 pcicfgregs cfg; 329 struct pci_conf conf; 330}; 331#endif 332 333#ifdef _SYS_BUS_H_ 334 335#include "pci_if.h" 336 337enum pci_device_ivars { 338 PCI_IVAR_SUBVENDOR, 339 PCI_IVAR_SUBDEVICE, 340 PCI_IVAR_VENDOR, 341 PCI_IVAR_DEVICE, 342 PCI_IVAR_DEVID, 343 PCI_IVAR_CLASS, 344 PCI_IVAR_SUBCLASS, 345 PCI_IVAR_PROGIF, 346 PCI_IVAR_REVID, 347 PCI_IVAR_INTPIN, 348 PCI_IVAR_IRQ, 349 PCI_IVAR_DOMAIN, 350 PCI_IVAR_BUS, 351 PCI_IVAR_SLOT, 352 PCI_IVAR_FUNCTION, 353 PCI_IVAR_ETHADDR, 354 PCI_IVAR_CMDREG, 355 PCI_IVAR_CACHELNSZ, 356 PCI_IVAR_MINGNT, 357 PCI_IVAR_MAXLAT, 358 PCI_IVAR_LATTIMER 359}; 360 361/* 362 * Simplified accessors for pci devices 363 */ 364#define PCI_ACCESSOR(var, ivar, type) \ 365 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 366 367PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 368PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 369PCI_ACCESSOR(vendor, VENDOR, uint16_t) 370PCI_ACCESSOR(device, DEVICE, uint16_t) 371PCI_ACCESSOR(devid, DEVID, uint32_t) 372PCI_ACCESSOR(class, CLASS, uint8_t) 373PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 374PCI_ACCESSOR(progif, PROGIF, uint8_t) 375PCI_ACCESSOR(revid, REVID, uint8_t) 376PCI_ACCESSOR(intpin, INTPIN, uint8_t) 377PCI_ACCESSOR(irq, IRQ, uint8_t) 378PCI_ACCESSOR(domain, DOMAIN, uint32_t) 379PCI_ACCESSOR(bus, BUS, uint8_t) 380PCI_ACCESSOR(slot, SLOT, uint8_t) 381PCI_ACCESSOR(function, FUNCTION, uint8_t) 382PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 383PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 384PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 385PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 386PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 387PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 388 389#undef PCI_ACCESSOR 390 391/* 392 * Operations on configuration space. 393 */ 394static __inline uint32_t 395pci_read_config(device_t dev, int reg, int width) 396{ 397 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 398} 399 400static __inline void 401pci_write_config(device_t dev, int reg, uint32_t val, int width) 402{ 403 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 404} 405 406/* 407 * Ivars for pci bridges. 408 */ 409 410/*typedef enum pci_device_ivars pcib_device_ivars;*/ 411enum pcib_device_ivars { 412 PCIB_IVAR_DOMAIN, 413 PCIB_IVAR_BUS 414}; 415 416#define PCIB_ACCESSOR(var, ivar, type) \ 417 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 418 419PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 420PCIB_ACCESSOR(bus, BUS, uint32_t) 421 422#undef PCIB_ACCESSOR 423 424/* 425 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 426 * on i386 or other platforms should be mapped out in the MD pcireadconf 427 * code and not here, since the only MI invalid IRQ is 255. 428 */ 429#define PCI_INVALID_IRQ 255 430#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 431 432/* 433 * Convenience functions. 434 * 435 * These should be used in preference to manually manipulating 436 * configuration space. 437 */ 438static __inline int 439pci_enable_busmaster(device_t dev) 440{ 441 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 442} 443 444static __inline int 445pci_disable_busmaster(device_t dev) 446{ 447 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 448} 449 450static __inline int 451pci_enable_io(device_t dev, int space) 452{ 453 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 454} 455 456static __inline int 457pci_disable_io(device_t dev, int space) 458{ 459 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 460} 461 462static __inline int 463pci_get_vpd_ident(device_t dev, const char **identptr) 464{ 465 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 466} 467 468static __inline int 469pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr) 470{ 471 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr)); 472} 473 474/* 475 * Check if the address range falls within the VGA defined address range(s) 476 */ 477static __inline int 478pci_is_vga_ioport_range(rman_res_t start, rman_res_t end) 479{ 480 481 return (((start >= 0x3b0 && end <= 0x3bb) || 482 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 483} 484 485static __inline int 486pci_is_vga_memory_range(rman_res_t start, rman_res_t end) 487{ 488 489 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 490} 491 492/* 493 * PCI power states are as defined by ACPI: 494 * 495 * D0 State in which device is on and running. It is receiving full 496 * power from the system and delivering full functionality to the user. 497 * D1 Class-specific low-power state in which device context may or may not 498 * be lost. Buses in D1 cannot do anything to the bus that would force 499 * devices on that bus to lose context. 500 * D2 Class-specific low-power state in which device context may or may 501 * not be lost. Attains greater power savings than D1. Buses in D2 502 * can cause devices on that bus to lose some context. Devices in D2 503 * must be prepared for the bus to be in D2 or higher. 504 * D3 State in which the device is off and not running. Device context is 505 * lost. Power can be removed from the device. 506 */ 507#define PCI_POWERSTATE_D0 0 508#define PCI_POWERSTATE_D1 1 509#define PCI_POWERSTATE_D2 2 510#define PCI_POWERSTATE_D3 3 511#define PCI_POWERSTATE_UNKNOWN -1 512 513static __inline int 514pci_set_powerstate(device_t dev, int state) 515{ 516 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 517} 518 519static __inline int 520pci_get_powerstate(device_t dev) 521{ 522 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 523} 524 525static __inline int 526pci_find_cap(device_t dev, int capability, int *capreg) 527{ 528 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg)); 529} 530 531static __inline int 532pci_find_next_cap(device_t dev, int capability, int start, int *capreg) 533{ 534 return (PCI_FIND_NEXT_CAP(device_get_parent(dev), dev, capability, start, 535 capreg)); 536} 537 538static __inline int 539pci_find_extcap(device_t dev, int capability, int *capreg) 540{ 541 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 542} 543 544static __inline int 545pci_find_next_extcap(device_t dev, int capability, int start, int *capreg) 546{ 547 return (PCI_FIND_NEXT_EXTCAP(device_get_parent(dev), dev, capability, 548 start, capreg)); 549} 550 551static __inline int 552pci_find_htcap(device_t dev, int capability, int *capreg) 553{ 554 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg)); 555} 556 557static __inline int 558pci_find_next_htcap(device_t dev, int capability, int start, int *capreg) 559{ 560 return (PCI_FIND_NEXT_HTCAP(device_get_parent(dev), dev, capability, 561 start, capreg)); 562} 563 564static __inline int 565pci_alloc_msi(device_t dev, int *count) 566{ 567 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 568} 569 570static __inline int 571pci_alloc_msix(device_t dev, int *count) 572{ 573 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 574} 575 576static __inline void 577pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 578{ 579 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data); 580} 581 582static __inline void 583pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 584{ 585 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data); 586} 587 588static __inline void 589pci_disable_msi(device_t dev) 590{ 591 PCI_DISABLE_MSI(device_get_parent(dev), dev); 592} 593 594static __inline int 595pci_remap_msix(device_t dev, int count, const u_int *vectors) 596{ 597 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 598} 599 600static __inline int 601pci_release_msi(device_t dev) 602{ 603 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 604} 605 606static __inline int 607pci_msi_count(device_t dev) 608{ 609 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 610} 611 612static __inline int 613pci_msix_count(device_t dev) 614{ 615 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 616} 617 618static __inline int 619pci_msix_pba_bar(device_t dev) 620{ 621 return (PCI_MSIX_PBA_BAR(device_get_parent(dev), dev)); 622} 623 624static __inline int 625pci_msix_table_bar(device_t dev) 626{ 627 return (PCI_MSIX_TABLE_BAR(device_get_parent(dev), dev)); 628} 629 630static __inline int 631pci_get_id(device_t dev, enum pci_id_type type, uintptr_t *id) 632{ 633 return (PCI_GET_ID(device_get_parent(dev), dev, type, id)); 634} 635 636/* 637 * This is the deprecated interface, there is no way to tell the difference 638 * between a failure and a valid value that happens to be the same as the 639 * failure value. 640 */ 641static __inline uint16_t 642pci_get_rid(device_t dev) 643{ 644 uintptr_t rid; 645 646 if (pci_get_id(dev, PCI_ID_RID, &rid) != 0) 647 return (0); 648 649 return (rid); 650} 651 652static __inline void 653pci_child_added(device_t dev) 654{ 655 656 return (PCI_CHILD_ADDED(device_get_parent(dev), dev)); 657} 658 659device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 660device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 661device_t pci_find_device(uint16_t, uint16_t); 662device_t pci_find_class(uint8_t class, uint8_t subclass); 663 664/* Can be used by drivers to manage the MSI-X table. */ 665int pci_pending_msix(device_t dev, u_int index); 666 667int pci_msi_device_blacklisted(device_t dev); 668int pci_msix_device_blacklisted(device_t dev); 669 670void pci_ht_map_msi(device_t dev, uint64_t addr); 671 672device_t pci_find_pcie_root_port(device_t dev); 673int pci_get_relaxed_ordering_enabled(device_t dev); 674int pci_get_max_payload(device_t dev); 675int pci_get_max_read_req(device_t dev); 676void pci_restore_state(device_t dev); 677void pci_save_state(device_t dev); 678int pci_set_max_read_req(device_t dev, int size); 679int pci_power_reset(device_t dev); 680uint32_t pcie_read_config(device_t dev, int reg, int width); 681void pcie_write_config(device_t dev, int reg, uint32_t value, int width); 682uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask, 683 uint32_t value, int width); 684void pcie_apei_error(device_t dev, int sev, uint8_t *aer); 685bool pcie_flr(device_t dev, u_int max_delay, bool force); 686int pcie_get_max_completion_timeout(device_t dev); 687bool pcie_wait_for_pending_transactions(device_t dev, u_int max_delay); 688int pcie_link_reset(device_t port, int pcie_location); 689 690void pci_print_faulted_dev(void); 691 692#endif /* _SYS_BUS_H_ */ 693 694/* 695 * cdev switch for control device, initialised in generic PCI code 696 */ 697extern struct cdevsw pcicdev; 698 699/* 700 * List of all PCI devices, generation count for the list. 701 */ 702STAILQ_HEAD(devlist, pci_devinfo); 703 704extern struct devlist pci_devq; 705extern uint32_t pci_generation; 706 707struct pci_map *pci_find_bar(device_t dev, int reg); 708int pci_bar_enabled(device_t dev, struct pci_map *pm); 709struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 710 711#define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 712#define VGA_PCI_BIOS_SHADOW_SIZE 131072 713 714int vga_pci_is_boot_display(device_t dev); 715void * vga_pci_map_bios(device_t dev, size_t *size); 716void vga_pci_unmap_bios(device_t dev, void *bios); 717int vga_pci_repost(device_t dev); 718 719/** 720 * Global eventhandlers invoked when PCI devices are added or removed 721 * from the system. 722 */ 723typedef void (*pci_event_fn)(void *arg, device_t dev); 724EVENTHANDLER_DECLARE(pci_add_device, pci_event_fn); 725EVENTHANDLER_DECLARE(pci_delete_device, pci_event_fn); 726 727#endif /* _PCIVAR_H_ */ 728