1/*- 2 * Copyright (c) 2016-2018, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28#ifndef __MLX5_PORT_H__ 29#define __MLX5_PORT_H__ 30 31#include <dev/mlx5/driver.h> 32 33enum mlx5_beacon_duration { 34 MLX5_BEACON_DURATION_OFF = 0x0, 35 MLX5_BEACON_DURATION_INF = 0xffff, 36}; 37 38enum mlx5_module_id { 39 MLX5_MODULE_ID_SFP = 0x3, 40 MLX5_MODULE_ID_QSFP = 0xC, 41 MLX5_MODULE_ID_QSFP_PLUS = 0xD, 42 MLX5_MODULE_ID_QSFP28 = 0x11, 43}; 44 45enum mlx5_an_status { 46 MLX5_AN_UNAVAILABLE = 0, 47 MLX5_AN_COMPLETE = 1, 48 MLX5_AN_FAILED = 2, 49 MLX5_AN_LINK_UP = 3, 50 MLX5_AN_LINK_DOWN = 4, 51}; 52 53/* EEPROM I2C Addresses */ 54#define MLX5_I2C_ADDR_LOW 0x50 55#define MLX5_I2C_ADDR_HIGH 0x51 56#define MLX5_EEPROM_PAGE_LENGTH 256 57#define MLX5_EEPROM_MAX_BYTES 32 58#define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff 59#define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00 60#define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000 61#define MLX5_EEPROM_LOW_PAGE 0x0 62#define MLX5_EEPROM_HIGH_PAGE 0x3 63#define MLX5_EEPROM_HIGH_PAGE_OFFSET 128 64#define MLX5_EEPROM_INFO_BYTES 0x3 65 66/* EEPROM Standards for plug in modules */ 67#ifndef MLX5_ETH_MODULE_SFF_8472 68#define MLX5_ETH_MODULE_SFF_8472 0x1 69#define MLX5_ETH_MODULE_SFF_8472_LEN 128 70#endif 71 72#ifndef MLX5_ETH_MODULE_SFF_8636 73#define MLX5_ETH_MODULE_SFF_8636 0x2 74#define MLX5_ETH_MODULE_SFF_8636_LEN 256 75#endif 76 77#ifndef MLX5_ETH_MODULE_SFF_8436 78#define MLX5_ETH_MODULE_SFF_8436 0x3 79#define MLX5_ETH_MODULE_SFF_8436_LEN 256 80#endif 81 82enum mlx5e_link_speed { 83 MLX5E_1000BASE_CX_SGMII = 0, 84 MLX5E_1000BASE_KX = 1, 85 MLX5E_10GBASE_CX4 = 2, 86 MLX5E_10GBASE_KX4 = 3, 87 MLX5E_10GBASE_KR = 4, 88 MLX5E_20GBASE_KR2 = 5, 89 MLX5E_40GBASE_CR4 = 6, 90 MLX5E_40GBASE_KR4 = 7, 91 MLX5E_56GBASE_R4 = 8, 92 MLX5E_10GBASE_CR = 12, 93 MLX5E_10GBASE_SR = 13, 94 MLX5E_10GBASE_ER_LR = 14, 95 MLX5E_40GBASE_SR4 = 15, 96 MLX5E_40GBASE_LR4_ER4 = 16, 97 MLX5E_50GBASE_SR2 = 18, 98 MLX5E_50GBASE_KR4 = 19, 99 MLX5E_100GBASE_CR4 = 20, 100 MLX5E_100GBASE_SR4 = 21, 101 MLX5E_100GBASE_KR4 = 22, 102 MLX5E_100GBASE_LR4 = 23, 103 MLX5E_100BASE_TX = 24, 104 MLX5E_1000BASE_T = 25, 105 MLX5E_10GBASE_T = 26, 106 MLX5E_25GBASE_CR = 27, 107 MLX5E_25GBASE_KR = 28, 108 MLX5E_25GBASE_SR = 29, 109 MLX5E_50GBASE_CR2 = 30, 110 MLX5E_50GBASE_KR2 = 31, 111 MLX5E_LINK_SPEEDS_NUMBER, 112}; 113 114enum mlx5e_ext_link_speed { 115 MLX5E_SGMII_100M = 0, 116 MLX5E_1000BASE_X_SGMII = 1, 117 MLX5E_5GBASE_R = 3, 118 MLX5E_10GBASE_XFI_XAUI_1 = 4, 119 MLX5E_40GBASE_XLAUI_4_XLPPI_4 = 5, 120 MLX5E_25GAUI_1_25GBASE_CR_KR = 6, 121 MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2 = 7, 122 MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8, 123 MLX5E_CAUI_4_100GBASE_CR4_KR4 = 9, 124 MLX5E_100GAUI_2_100GBASE_CR2_KR2 = 10, 125 MLX5E_200GAUI_4_200GBASE_CR4_KR4 = 12, 126 MLX5E_400GAUI_8 = 15, 127 MLX5E_EXT_LINK_SPEEDS_NUMBER, 128}; 129 130enum mlx5e_link_mode { 131 MLX5E_ACC, 132 MLX5E_AOC, 133 MLX5E_AUI, 134 MLX5E_AUI_AC, 135 MLX5E_AUI2, 136 MLX5E_AUI2_AC, 137 MLX5E_AUI4, 138 MLX5E_AUI4_AC, 139 MLX5E_CAUI2, 140 MLX5E_CAUI2_AC, 141 MLX5E_CAUI4, 142 MLX5E_CAUI4_AC, 143 MLX5E_CP, 144 MLX5E_CP2, 145 MLX5E_CR, 146 MLX5E_CR_S, 147 MLX5E_CR1, 148 MLX5E_CR2, 149 MLX5E_CR4, 150 MLX5E_CR_PAM4, 151 MLX5E_CR4_PAM4, 152 MLX5E_CX4, 153 MLX5E_CX, 154 MLX5E_CX_SGMII, 155 MLX5E_DR, 156 MLX5E_DR4, 157 MLX5E_ER, 158 MLX5E_ER4, 159 MLX5E_FR, 160 MLX5E_FR4, 161 MLX5E_KR, 162 MLX5E_KR1, 163 MLX5E_KR_PAM4, 164 MLX5E_KR_S, 165 MLX5E_KR2, 166 MLX5E_KR2_PAM4, 167 MLX5E_KR4, 168 MLX5E_KR4_PAM4, 169 MLX5E_KX, 170 MLX5E_KX4, 171 MLX5E_LR, 172 MLX5E_LR2, 173 MLX5E_LR4, 174 MLX5E_LX, 175 MLX5E_R, 176 MLX5E_SGMII, 177 MLX5E_SR, 178 MLX5E_SR2, 179 MLX5E_SR4, 180 MLX5E_SX, 181 MLX5E_T, 182 MLX5E_TX, 183 MLX5E_LINK_MODES_NUMBER, 184}; 185 186enum mlx5e_connector_type { 187 MLX5E_PORT_UNKNOWN = 0, 188 MLX5E_PORT_NONE = 1, 189 MLX5E_PORT_TP = 2, 190 MLX5E_PORT_AUI = 3, 191 MLX5E_PORT_BNC = 4, 192 MLX5E_PORT_MII = 5, 193 MLX5E_PORT_FIBRE = 6, 194 MLX5E_PORT_DA = 7, 195 MLX5E_PORT_OTHER = 8, 196 MLX5E_CONNECTOR_TYPE_NUMBER, 197}; 198 199enum mlx5_qpts_trust_state { 200 MLX5_QPTS_TRUST_PCP = 1, 201 MLX5_QPTS_TRUST_DSCP = 2, 202 MLX5_QPTS_TRUST_BOTH = 3, 203}; 204struct mlx5e_port_eth_proto { 205 u32 cap; 206 u32 admin; 207 u32 oper; 208}; 209 210#ifndef SPEED_40000 211#define SPEED_40000 40000 212#endif 213 214#define MLX5E_PROT_MASK(link_mode) (1 << (link_mode)) 215 216#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 217#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 218 219#define MLX5_GET_ETH_PROTO(reg, out, ext, field) \ 220 ((ext) ? MLX5_GET(reg, out, ext_##field) : \ 221 MLX5_GET(reg, out, field)) 222 223int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); 224int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, 225 int ptys_size, int proto_mask, u8 local_port); 226int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, 227 u32 *proto_cap, int proto_mask); 228int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask, 229 u8 *an_disable_cap, u8 *an_disable_status); 230int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable, 231 u32 eth_proto_admin, int proto_mask); 232int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, 233 u32 *proto_admin, int proto_mask); 234int mlx5_query_port_eth_proto_oper(struct mlx5_core_dev *dev, 235 u32 *proto_oper, u8 local_port); 236int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, 237 int proto_mask, bool ext); 238int mlx5_set_port_status(struct mlx5_core_dev *dev, 239 enum mlx5_port_status status); 240int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); 241int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, 242 enum mlx5_port_status *status); 243int mlx5_set_port_pause_and_pfc(struct mlx5_core_dev *dev, u32 port, 244 u8 rx_pause, u8 tx_pause, 245 u8 pfc_en_rx, u8 pfc_en_tx); 246int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port, 247 u32 *rx_pause, u32 *tx_pause); 248int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx); 249 250int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); 251int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); 252int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); 253 254unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num); 255int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num); 256int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num, 257 int device_addr, int size, int module_num, u32 *data, 258 int *size_read); 259 260int mlx5_max_tc(struct mlx5_core_dev *mdev); 261int mlx5_query_port_tc_rate_limit(struct mlx5_core_dev *mdev, 262 u8 *max_bw_value, 263 u8 *max_bw_units); 264int mlx5_modify_port_tc_rate_limit(struct mlx5_core_dev *mdev, 265 const u8 *max_bw_value, 266 const u8 *max_bw_units); 267int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev, 268 u8 prio, u8 *tc); 269int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, int prio_index, 270 const u8 prio_tc); 271int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, const u8 *tc_group); 272int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev, 273 u8 tc, u8 *tc_group); 274int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, const u8 *tc_bw); 275int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *bw_pct); 276 277int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state); 278int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state); 279 280#define MLX5_MAX_SUPPORTED_DSCP 64 281int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, const u8 *dscp2prio); 282int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio); 283 284int mlx5_query_pddr_range_info(struct mlx5_core_dev *mdev, u8 local_port, u8 *is_er_type); 285 286u32 mlx5e_port_ptys2speed(struct mlx5_core_dev *mdev, u32 eth_proto_oper); 287int mlx5e_port_linkspeed(struct mlx5_core_dev *mdev, u32 *speed); 288int mlx5_port_query_eth_proto(struct mlx5_core_dev *dev, u8 port, bool ext, 289 struct mlx5e_port_eth_proto *eproto); 290 291int mlx5e_port_query_pbmc(struct mlx5_core_dev *mdev, void *out); 292int mlx5e_port_set_pbmc(struct mlx5_core_dev *mdev, void *in); 293int mlx5e_port_query_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer); 294int mlx5e_port_set_priority2buffer(struct mlx5_core_dev *mdev, u8 *buffer); 295 296#endif /* __MLX5_PORT_H__ */ 297