1/*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD$ 26 */ 27 28#include <linux/module.h> 29#include <linux/errno.h> 30#include <linux/pci.h> 31#include <linux/dma-mapping.h> 32#include <linux/slab.h> 33#if defined(CONFIG_X86) 34#include <asm/pat.h> 35#endif 36#include <linux/sched.h> 37#include <linux/delay.h> 38#include <linux/fs.h> 39#undef inode 40#include <rdma/ib_user_verbs.h> 41#include <rdma/ib_addr.h> 42#include <rdma/ib_cache.h> 43#include <dev/mlx5/port.h> 44#include <dev/mlx5/vport.h> 45#include <linux/list.h> 46#include <rdma/ib_smi.h> 47#include <rdma/ib_umem.h> 48#include <linux/in.h> 49#include <linux/etherdevice.h> 50#include <dev/mlx5/fs.h> 51#include "mlx5_ib.h" 52 53#define DRIVER_NAME "mlx5ib" 54#ifndef DRIVER_VERSION 55#define DRIVER_VERSION "3.6.0" 56#endif 57#define DRIVER_RELDATE "December 2020" 58 59MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver"); 60MODULE_LICENSE("Dual BSD/GPL"); 61MODULE_DEPEND(mlx5ib, linuxkpi, 1, 1, 1); 62MODULE_DEPEND(mlx5ib, mlx5, 1, 1, 1); 63MODULE_DEPEND(mlx5ib, ibcore, 1, 1, 1); 64MODULE_VERSION(mlx5ib, 1); 65 66static const char mlx5_version[] = 67 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver " 68 DRIVER_VERSION " (" DRIVER_RELDATE ")\n"; 69 70enum { 71 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3, 72}; 73 74static enum rdma_link_layer 75mlx5_port_type_cap_to_rdma_ll(int port_type_cap) 76{ 77 switch (port_type_cap) { 78 case MLX5_CAP_PORT_TYPE_IB: 79 return IB_LINK_LAYER_INFINIBAND; 80 case MLX5_CAP_PORT_TYPE_ETH: 81 return IB_LINK_LAYER_ETHERNET; 82 default: 83 return IB_LINK_LAYER_UNSPECIFIED; 84 } 85} 86 87static enum rdma_link_layer 88mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num) 89{ 90 struct mlx5_ib_dev *dev = to_mdev(device); 91 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type); 92 93 return mlx5_port_type_cap_to_rdma_ll(port_type_cap); 94} 95 96static bool mlx5_netdev_match(struct net_device *ndev, 97 struct mlx5_core_dev *mdev, 98 const char *dname) 99{ 100 return ndev->if_type == IFT_ETHER && 101 ndev->if_dname != NULL && 102 strcmp(ndev->if_dname, dname) == 0 && 103 ndev->if_softc != NULL && 104 *(struct mlx5_core_dev **)ndev->if_softc == mdev; 105} 106 107static int mlx5_netdev_event(struct notifier_block *this, 108 unsigned long event, void *ptr) 109{ 110 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 111 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev, 112 roce.nb); 113 114 switch (event) { 115 case NETDEV_REGISTER: 116 case NETDEV_UNREGISTER: 117 write_lock(&ibdev->roce.netdev_lock); 118 /* check if network interface belongs to mlx5en */ 119 if (mlx5_netdev_match(ndev, ibdev->mdev, "mce")) 120 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ? 121 NULL : ndev; 122 write_unlock(&ibdev->roce.netdev_lock); 123 break; 124 125 case NETDEV_UP: 126 case NETDEV_DOWN: { 127 struct net_device *upper = NULL; 128 129 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev)) 130 && ibdev->ib_active) { 131 struct ib_event ibev = {0}; 132 133 ibev.device = &ibdev->ib_dev; 134 ibev.event = (event == NETDEV_UP) ? 135 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 136 ibev.element.port_num = 1; 137 ib_dispatch_event(&ibev); 138 } 139 break; 140 } 141 142 default: 143 break; 144 } 145 146 return NOTIFY_DONE; 147} 148 149static struct net_device *mlx5_ib_get_netdev(struct ib_device *device, 150 u8 port_num) 151{ 152 struct mlx5_ib_dev *ibdev = to_mdev(device); 153 struct net_device *ndev; 154 155 /* Ensure ndev does not disappear before we invoke dev_hold() 156 */ 157 read_lock(&ibdev->roce.netdev_lock); 158 ndev = ibdev->roce.netdev; 159 if (ndev) 160 dev_hold(ndev); 161 read_unlock(&ibdev->roce.netdev_lock); 162 163 return ndev; 164} 165 166static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed, 167 u8 *active_width) 168{ 169 switch (eth_proto_oper) { 170 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII): 171 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX): 172 case MLX5E_PROT_MASK(MLX5E_100BASE_TX): 173 case MLX5E_PROT_MASK(MLX5E_1000BASE_T): 174 *active_width = IB_WIDTH_1X; 175 *active_speed = IB_SPEED_SDR; 176 break; 177 case MLX5E_PROT_MASK(MLX5E_10GBASE_T): 178 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4): 179 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4): 180 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR): 181 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR): 182 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR): 183 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER_LR): 184 *active_width = IB_WIDTH_1X; 185 *active_speed = IB_SPEED_QDR; 186 break; 187 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR): 188 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR): 189 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR): 190 *active_width = IB_WIDTH_1X; 191 *active_speed = IB_SPEED_EDR; 192 break; 193 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4): 194 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4): 195 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4): 196 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4_ER4): 197 *active_width = IB_WIDTH_4X; 198 *active_speed = IB_SPEED_QDR; 199 break; 200 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2): 201 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2): 202 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR4): 203 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2): 204 *active_width = IB_WIDTH_1X; 205 *active_speed = IB_SPEED_HDR; 206 break; 207 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4): 208 *active_width = IB_WIDTH_4X; 209 *active_speed = IB_SPEED_FDR; 210 break; 211 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4): 212 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4): 213 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4): 214 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4): 215 *active_width = IB_WIDTH_4X; 216 *active_speed = IB_SPEED_EDR; 217 break; 218 default: 219 *active_width = IB_WIDTH_4X; 220 *active_speed = IB_SPEED_QDR; 221 return -EINVAL; 222 } 223 224 return 0; 225} 226 227static int translate_eth_ext_proto_oper(u32 eth_proto_oper, u8 *active_speed, 228 u8 *active_width) 229{ 230 switch (eth_proto_oper) { 231 case MLX5E_PROT_MASK(MLX5E_SGMII_100M): 232 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII): 233 *active_width = IB_WIDTH_1X; 234 *active_speed = IB_SPEED_SDR; 235 break; 236 case MLX5E_PROT_MASK(MLX5E_5GBASE_R): 237 *active_width = IB_WIDTH_1X; 238 *active_speed = IB_SPEED_DDR; 239 break; 240 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1): 241 *active_width = IB_WIDTH_1X; 242 *active_speed = IB_SPEED_QDR; 243 break; 244 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4): 245 *active_width = IB_WIDTH_4X; 246 *active_speed = IB_SPEED_QDR; 247 break; 248 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR): 249 *active_width = IB_WIDTH_1X; 250 *active_speed = IB_SPEED_EDR; 251 break; 252 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2): 253 *active_width = IB_WIDTH_2X; 254 *active_speed = IB_SPEED_EDR; 255 break; 256 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR): 257 *active_width = IB_WIDTH_1X; 258 *active_speed = IB_SPEED_HDR; 259 break; 260 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4): 261 *active_width = IB_WIDTH_4X; 262 *active_speed = IB_SPEED_EDR; 263 break; 264 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2): 265 *active_width = IB_WIDTH_2X; 266 *active_speed = IB_SPEED_HDR; 267 break; 268 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4): 269 *active_width = IB_WIDTH_4X; 270 *active_speed = IB_SPEED_HDR; 271 break; 272 default: 273 *active_width = IB_WIDTH_4X; 274 *active_speed = IB_SPEED_QDR; 275 return -EINVAL; 276 } 277 278 return 0; 279} 280 281static int mlx5_query_port_roce(struct ib_device *device, u8 port_num, 282 struct ib_port_attr *props) 283{ 284 struct mlx5_ib_dev *dev = to_mdev(device); 285 u32 out[MLX5_ST_SZ_DW(ptys_reg)] = {}; 286 struct net_device *ndev; 287 enum ib_mtu ndev_ib_mtu; 288 u16 qkey_viol_cntr; 289 u32 eth_prot_oper; 290 bool ext; 291 int err; 292 293 memset(props, 0, sizeof(*props)); 294 295 /* Possible bad flows are checked before filling out props so in case 296 * of an error it will still be zeroed out. 297 */ 298 err = mlx5_query_port_ptys(dev->mdev, out, sizeof(out), MLX5_PTYS_EN, 299 port_num); 300 if (err) 301 return err; 302 303 ext = MLX5_CAP_PCAM_FEATURE(dev->mdev, ptys_extended_ethernet); 304 eth_prot_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext, eth_proto_oper); 305 306 if (ext) 307 translate_eth_ext_proto_oper(eth_prot_oper, &props->active_speed, 308 &props->active_width); 309 else 310 translate_eth_proto_oper(eth_prot_oper, &props->active_speed, 311 &props->active_width); 312 313 props->port_cap_flags |= IB_PORT_CM_SUP; 314 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS; 315 316 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev, 317 roce_address_table_size); 318 props->max_mtu = IB_MTU_4096; 319 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg); 320 props->pkey_tbl_len = 1; 321 props->state = IB_PORT_DOWN; 322 props->phys_state = 3; 323 324 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr); 325 props->qkey_viol_cntr = qkey_viol_cntr; 326 327 ndev = mlx5_ib_get_netdev(device, port_num); 328 if (!ndev) 329 return 0; 330 331 if (netif_running(ndev) && netif_carrier_ok(ndev)) { 332 props->state = IB_PORT_ACTIVE; 333 props->phys_state = 5; 334 } 335 336 ndev_ib_mtu = iboe_get_mtu(ndev->if_mtu); 337 338 dev_put(ndev); 339 340 props->active_mtu = min(props->max_mtu, ndev_ib_mtu); 341 return 0; 342} 343 344static void ib_gid_to_mlx5_roce_addr(const union ib_gid *gid, 345 const struct ib_gid_attr *attr, 346 void *mlx5_addr) 347{ 348#define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v) 349 char *mlx5_addr_l3_addr = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 350 source_l3_address); 351 void *mlx5_addr_mac = MLX5_ADDR_OF(roce_addr_layout, mlx5_addr, 352 source_mac_47_32); 353 u16 vlan_id; 354 355 if (!gid) 356 return; 357 ether_addr_copy(mlx5_addr_mac, IF_LLADDR(attr->ndev)); 358 359 vlan_id = rdma_vlan_dev_vlan_id(attr->ndev); 360 if (vlan_id != 0xffff) { 361 MLX5_SET_RA(mlx5_addr, vlan_valid, 1); 362 MLX5_SET_RA(mlx5_addr, vlan_id, vlan_id); 363 } 364 365 switch (attr->gid_type) { 366 case IB_GID_TYPE_IB: 367 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_1); 368 break; 369 case IB_GID_TYPE_ROCE_UDP_ENCAP: 370 MLX5_SET_RA(mlx5_addr, roce_version, MLX5_ROCE_VERSION_2); 371 break; 372 373 default: 374 WARN_ON(true); 375 } 376 377 if (attr->gid_type != IB_GID_TYPE_IB) { 378 if (ipv6_addr_v4mapped((void *)gid)) 379 MLX5_SET_RA(mlx5_addr, roce_l3_type, 380 MLX5_ROCE_L3_TYPE_IPV4); 381 else 382 MLX5_SET_RA(mlx5_addr, roce_l3_type, 383 MLX5_ROCE_L3_TYPE_IPV6); 384 } 385 386 if ((attr->gid_type == IB_GID_TYPE_IB) || 387 !ipv6_addr_v4mapped((void *)gid)) 388 memcpy(mlx5_addr_l3_addr, gid, sizeof(*gid)); 389 else 390 memcpy(&mlx5_addr_l3_addr[12], &gid->raw[12], 4); 391} 392 393static int set_roce_addr(struct ib_device *device, u8 port_num, 394 unsigned int index, 395 const union ib_gid *gid, 396 const struct ib_gid_attr *attr) 397{ 398 struct mlx5_ib_dev *dev = to_mdev(device); 399 u32 in[MLX5_ST_SZ_DW(set_roce_address_in)] = {0}; 400 u32 out[MLX5_ST_SZ_DW(set_roce_address_out)] = {0}; 401 void *in_addr = MLX5_ADDR_OF(set_roce_address_in, in, roce_address); 402 enum rdma_link_layer ll = mlx5_ib_port_link_layer(device, port_num); 403 404 if (ll != IB_LINK_LAYER_ETHERNET) 405 return -EINVAL; 406 407 ib_gid_to_mlx5_roce_addr(gid, attr, in_addr); 408 409 MLX5_SET(set_roce_address_in, in, roce_address_index, index); 410 MLX5_SET(set_roce_address_in, in, opcode, MLX5_CMD_OP_SET_ROCE_ADDRESS); 411 return mlx5_cmd_exec(dev->mdev, in, sizeof(in), out, sizeof(out)); 412} 413 414static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num, 415 unsigned int index, const union ib_gid *gid, 416 const struct ib_gid_attr *attr, 417 __always_unused void **context) 418{ 419 return set_roce_addr(device, port_num, index, gid, attr); 420} 421 422static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num, 423 unsigned int index, __always_unused void **context) 424{ 425 return set_roce_addr(device, port_num, index, NULL, NULL); 426} 427 428__be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num, 429 int index) 430{ 431 struct ib_gid_attr attr; 432 union ib_gid gid; 433 434 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr)) 435 return 0; 436 437 if (!attr.ndev) 438 return 0; 439 440 dev_put(attr.ndev); 441 442 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP) 443 return 0; 444 445 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port)); 446} 447 448int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num, 449 int index, enum ib_gid_type *gid_type) 450{ 451 struct ib_gid_attr attr; 452 union ib_gid gid; 453 int ret; 454 455 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr); 456 if (ret) 457 return ret; 458 459 if (!attr.ndev) 460 return -ENODEV; 461 462 dev_put(attr.ndev); 463 464 *gid_type = attr.gid_type; 465 466 return 0; 467} 468 469static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev) 470{ 471 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB) 472 return !MLX5_CAP_GEN(dev->mdev, ib_virt); 473 return 0; 474} 475 476enum { 477 MLX5_VPORT_ACCESS_METHOD_MAD, 478 MLX5_VPORT_ACCESS_METHOD_HCA, 479 MLX5_VPORT_ACCESS_METHOD_NIC, 480}; 481 482static int mlx5_get_vport_access_method(struct ib_device *ibdev) 483{ 484 if (mlx5_use_mad_ifc(to_mdev(ibdev))) 485 return MLX5_VPORT_ACCESS_METHOD_MAD; 486 487 if (mlx5_ib_port_link_layer(ibdev, 1) == 488 IB_LINK_LAYER_ETHERNET) 489 return MLX5_VPORT_ACCESS_METHOD_NIC; 490 491 return MLX5_VPORT_ACCESS_METHOD_HCA; 492} 493 494static void get_atomic_caps(struct mlx5_ib_dev *dev, 495 struct ib_device_attr *props) 496{ 497 u8 tmp; 498 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations); 499 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp); 500 u8 atomic_req_8B_endianness_mode = 501 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianess_mode); 502 503 /* Check if HW supports 8 bytes standard atomic operations and capable 504 * of host endianness respond 505 */ 506 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD; 507 if (((atomic_operations & tmp) == tmp) && 508 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) && 509 (atomic_req_8B_endianness_mode)) { 510 props->atomic_cap = IB_ATOMIC_HCA; 511 } else { 512 props->atomic_cap = IB_ATOMIC_NONE; 513 } 514} 515 516static int mlx5_query_system_image_guid(struct ib_device *ibdev, 517 __be64 *sys_image_guid) 518{ 519 struct mlx5_ib_dev *dev = to_mdev(ibdev); 520 struct mlx5_core_dev *mdev = dev->mdev; 521 u64 tmp; 522 int err; 523 524 switch (mlx5_get_vport_access_method(ibdev)) { 525 case MLX5_VPORT_ACCESS_METHOD_MAD: 526 return mlx5_query_mad_ifc_system_image_guid(ibdev, 527 sys_image_guid); 528 529 case MLX5_VPORT_ACCESS_METHOD_HCA: 530 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp); 531 break; 532 533 case MLX5_VPORT_ACCESS_METHOD_NIC: 534 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp); 535 break; 536 537 default: 538 return -EINVAL; 539 } 540 541 if (!err) 542 *sys_image_guid = cpu_to_be64(tmp); 543 544 return err; 545 546} 547 548static int mlx5_query_max_pkeys(struct ib_device *ibdev, 549 u16 *max_pkeys) 550{ 551 struct mlx5_ib_dev *dev = to_mdev(ibdev); 552 struct mlx5_core_dev *mdev = dev->mdev; 553 554 switch (mlx5_get_vport_access_method(ibdev)) { 555 case MLX5_VPORT_ACCESS_METHOD_MAD: 556 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys); 557 558 case MLX5_VPORT_ACCESS_METHOD_HCA: 559 case MLX5_VPORT_ACCESS_METHOD_NIC: 560 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, 561 pkey_table_size)); 562 return 0; 563 564 default: 565 return -EINVAL; 566 } 567} 568 569static int mlx5_query_vendor_id(struct ib_device *ibdev, 570 u32 *vendor_id) 571{ 572 struct mlx5_ib_dev *dev = to_mdev(ibdev); 573 574 switch (mlx5_get_vport_access_method(ibdev)) { 575 case MLX5_VPORT_ACCESS_METHOD_MAD: 576 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id); 577 578 case MLX5_VPORT_ACCESS_METHOD_HCA: 579 case MLX5_VPORT_ACCESS_METHOD_NIC: 580 return mlx5_core_query_vendor_id(dev->mdev, vendor_id); 581 582 default: 583 return -EINVAL; 584 } 585} 586 587static int mlx5_query_node_guid(struct mlx5_ib_dev *dev, 588 __be64 *node_guid) 589{ 590 u64 tmp; 591 int err; 592 593 switch (mlx5_get_vport_access_method(&dev->ib_dev)) { 594 case MLX5_VPORT_ACCESS_METHOD_MAD: 595 return mlx5_query_mad_ifc_node_guid(dev, node_guid); 596 597 case MLX5_VPORT_ACCESS_METHOD_HCA: 598 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp); 599 break; 600 601 case MLX5_VPORT_ACCESS_METHOD_NIC: 602 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp); 603 break; 604 605 default: 606 return -EINVAL; 607 } 608 609 if (!err) 610 *node_guid = cpu_to_be64(tmp); 611 612 return err; 613} 614 615struct mlx5_reg_node_desc { 616 u8 desc[IB_DEVICE_NODE_DESC_MAX]; 617}; 618 619static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc) 620{ 621 struct mlx5_reg_node_desc in; 622 623 if (mlx5_use_mad_ifc(dev)) 624 return mlx5_query_mad_ifc_node_desc(dev, node_desc); 625 626 memset(&in, 0, sizeof(in)); 627 628 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc, 629 sizeof(struct mlx5_reg_node_desc), 630 MLX5_REG_NODE_DESC, 0, 0); 631} 632 633static int mlx5_ib_query_device(struct ib_device *ibdev, 634 struct ib_device_attr *props, 635 struct ib_udata *uhw) 636{ 637 struct mlx5_ib_dev *dev = to_mdev(ibdev); 638 struct mlx5_core_dev *mdev = dev->mdev; 639 int err = -ENOMEM; 640 int max_sq_desc; 641 int max_rq_sg; 642 int max_sq_sg; 643 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz); 644 struct mlx5_ib_query_device_resp resp = {}; 645 size_t resp_len; 646 u64 max_tso; 647 648 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length); 649 if (uhw->outlen && uhw->outlen < resp_len) 650 return -EINVAL; 651 else 652 resp.response_length = resp_len; 653 654 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen)) 655 return -EINVAL; 656 657 memset(props, 0, sizeof(*props)); 658 err = mlx5_query_system_image_guid(ibdev, 659 &props->sys_image_guid); 660 if (err) 661 return err; 662 663 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys); 664 if (err) 665 return err; 666 667 err = mlx5_query_vendor_id(ibdev, &props->vendor_id); 668 if (err) 669 return err; 670 671 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) | 672 ((u32)fw_rev_min(dev->mdev) << 16) | 673 fw_rev_sub(dev->mdev); 674 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT | 675 IB_DEVICE_PORT_ACTIVE_EVENT | 676 IB_DEVICE_SYS_IMAGE_GUID | 677 IB_DEVICE_RC_RNR_NAK_GEN; 678 679 if (MLX5_CAP_GEN(mdev, pkv)) 680 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR; 681 if (MLX5_CAP_GEN(mdev, qkv)) 682 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR; 683 if (MLX5_CAP_GEN(mdev, apm)) 684 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG; 685 if (MLX5_CAP_GEN(mdev, xrc)) 686 props->device_cap_flags |= IB_DEVICE_XRC; 687 if (MLX5_CAP_GEN(mdev, imaicl)) { 688 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW | 689 IB_DEVICE_MEM_WINDOW_TYPE_2B; 690 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 691 /* We support 'Gappy' memory registration too */ 692 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG; 693 } 694 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS; 695 if (MLX5_CAP_GEN(mdev, sho)) { 696 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER; 697 /* At this stage no support for signature handover */ 698 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 | 699 IB_PROT_T10DIF_TYPE_2 | 700 IB_PROT_T10DIF_TYPE_3; 701 props->sig_guard_cap = IB_GUARD_T10DIF_CRC | 702 IB_GUARD_T10DIF_CSUM; 703 } 704 if (MLX5_CAP_GEN(mdev, block_lb_mc)) 705 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK; 706 707 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) { 708 if (MLX5_CAP_ETH(mdev, csum_cap)) 709 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM; 710 711 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) { 712 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap); 713 if (max_tso) { 714 resp.tso_caps.max_tso = 1 << max_tso; 715 resp.tso_caps.supported_qpts |= 716 1 << IB_QPT_RAW_PACKET; 717 resp.response_length += sizeof(resp.tso_caps); 718 } 719 } 720 721 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) { 722 resp.rss_caps.rx_hash_function = 723 MLX5_RX_HASH_FUNC_TOEPLITZ; 724 resp.rss_caps.rx_hash_fields_mask = 725 MLX5_RX_HASH_SRC_IPV4 | 726 MLX5_RX_HASH_DST_IPV4 | 727 MLX5_RX_HASH_SRC_IPV6 | 728 MLX5_RX_HASH_DST_IPV6 | 729 MLX5_RX_HASH_SRC_PORT_TCP | 730 MLX5_RX_HASH_DST_PORT_TCP | 731 MLX5_RX_HASH_SRC_PORT_UDP | 732 MLX5_RX_HASH_DST_PORT_UDP; 733 resp.response_length += sizeof(resp.rss_caps); 734 } 735 } else { 736 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) 737 resp.response_length += sizeof(resp.tso_caps); 738 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) 739 resp.response_length += sizeof(resp.rss_caps); 740 } 741 742 if (MLX5_CAP_GEN(mdev, ipoib_ipoib_offloads)) { 743 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM; 744 props->device_cap_flags |= IB_DEVICE_UD_TSO; 745 } 746 747 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && 748 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) 749 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS; 750 751 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) 752 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING; 753 754 props->vendor_part_id = mdev->pdev->device; 755 props->hw_ver = mdev->pdev->revision; 756 757 props->max_mr_size = ~0ull; 758 props->page_size_cap = ~(min_page_size - 1); 759 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp); 760 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz); 761 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) / 762 sizeof(struct mlx5_wqe_data_seg); 763 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512); 764 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) - 765 sizeof(struct mlx5_wqe_raddr_seg)) / 766 sizeof(struct mlx5_wqe_data_seg); 767 props->max_sge = min(max_rq_sg, max_sq_sg); 768 props->max_sge_rd = MLX5_MAX_SGE_RD; 769 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq); 770 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1; 771 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey); 772 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd); 773 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp); 774 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp); 775 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq); 776 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1; 777 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay); 778 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp; 779 props->max_srq_sge = max_rq_sg - 1; 780 props->max_fast_reg_page_list_len = 781 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size); 782 get_atomic_caps(dev, props); 783 props->masked_atomic_cap = IB_ATOMIC_NONE; 784 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg); 785 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg); 786 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach * 787 props->max_mcast_grp; 788 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */ 789 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz); 790 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL; 791 792#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 793 if (MLX5_CAP_GEN(mdev, pg)) 794 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING; 795 props->odp_caps = dev->odp_caps; 796#endif 797 798 if (MLX5_CAP_GEN(mdev, cd)) 799 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL; 800 801 if (!mlx5_core_is_pf(mdev)) 802 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION; 803 804 if (mlx5_ib_port_link_layer(ibdev, 1) == 805 IB_LINK_LAYER_ETHERNET) { 806 props->rss_caps.max_rwq_indirection_tables = 807 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt); 808 props->rss_caps.max_rwq_indirection_table_size = 809 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size); 810 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET; 811 props->max_wq_type_rq = 812 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq); 813 } 814 815 if (uhw->outlen) { 816 err = ib_copy_to_udata(uhw, &resp, resp.response_length); 817 818 if (err) 819 return err; 820 } 821 822 return 0; 823} 824 825enum mlx5_ib_width { 826 MLX5_IB_WIDTH_1X = 1 << 0, 827 MLX5_IB_WIDTH_2X = 1 << 1, 828 MLX5_IB_WIDTH_4X = 1 << 2, 829 MLX5_IB_WIDTH_8X = 1 << 3, 830 MLX5_IB_WIDTH_12X = 1 << 4 831}; 832 833static int translate_active_width(struct ib_device *ibdev, u8 active_width, 834 u8 *ib_width) 835{ 836 struct mlx5_ib_dev *dev = to_mdev(ibdev); 837 int err = 0; 838 839 if (active_width & MLX5_IB_WIDTH_1X) { 840 *ib_width = IB_WIDTH_1X; 841 } else if (active_width & MLX5_IB_WIDTH_2X) { 842 *ib_width = IB_WIDTH_2X; 843 } else if (active_width & MLX5_IB_WIDTH_4X) { 844 *ib_width = IB_WIDTH_4X; 845 } else if (active_width & MLX5_IB_WIDTH_8X) { 846 *ib_width = IB_WIDTH_8X; 847 } else if (active_width & MLX5_IB_WIDTH_12X) { 848 *ib_width = IB_WIDTH_12X; 849 } else { 850 mlx5_ib_dbg(dev, "Invalid active_width %d\n", 851 (int)active_width); 852 err = -EINVAL; 853 } 854 855 return err; 856} 857 858enum ib_max_vl_num { 859 __IB_MAX_VL_0 = 1, 860 __IB_MAX_VL_0_1 = 2, 861 __IB_MAX_VL_0_3 = 3, 862 __IB_MAX_VL_0_7 = 4, 863 __IB_MAX_VL_0_14 = 5, 864}; 865 866enum mlx5_vl_hw_cap { 867 MLX5_VL_HW_0 = 1, 868 MLX5_VL_HW_0_1 = 2, 869 MLX5_VL_HW_0_2 = 3, 870 MLX5_VL_HW_0_3 = 4, 871 MLX5_VL_HW_0_4 = 5, 872 MLX5_VL_HW_0_5 = 6, 873 MLX5_VL_HW_0_6 = 7, 874 MLX5_VL_HW_0_7 = 8, 875 MLX5_VL_HW_0_14 = 15 876}; 877 878static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap, 879 u8 *max_vl_num) 880{ 881 switch (vl_hw_cap) { 882 case MLX5_VL_HW_0: 883 *max_vl_num = __IB_MAX_VL_0; 884 break; 885 case MLX5_VL_HW_0_1: 886 *max_vl_num = __IB_MAX_VL_0_1; 887 break; 888 case MLX5_VL_HW_0_3: 889 *max_vl_num = __IB_MAX_VL_0_3; 890 break; 891 case MLX5_VL_HW_0_7: 892 *max_vl_num = __IB_MAX_VL_0_7; 893 break; 894 case MLX5_VL_HW_0_14: 895 *max_vl_num = __IB_MAX_VL_0_14; 896 break; 897 898 default: 899 return -EINVAL; 900 } 901 902 return 0; 903} 904 905static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port, 906 struct ib_port_attr *props) 907{ 908 struct mlx5_ib_dev *dev = to_mdev(ibdev); 909 struct mlx5_core_dev *mdev = dev->mdev; 910 u32 *rep; 911 int replen = MLX5_ST_SZ_BYTES(query_hca_vport_context_out); 912 struct mlx5_ptys_reg *ptys; 913 struct mlx5_pmtu_reg *pmtu; 914 struct mlx5_pvlc_reg pvlc; 915 void *ctx; 916 int err; 917 918 rep = mlx5_vzalloc(replen); 919 ptys = kzalloc(sizeof(*ptys), GFP_KERNEL); 920 pmtu = kzalloc(sizeof(*pmtu), GFP_KERNEL); 921 if (!rep || !ptys || !pmtu) { 922 err = -ENOMEM; 923 goto out; 924 } 925 926 memset(props, 0, sizeof(*props)); 927 928 err = mlx5_query_hca_vport_context(mdev, port, 0, rep, replen); 929 if (err) 930 goto out; 931 932 ctx = MLX5_ADDR_OF(query_hca_vport_context_out, rep, hca_vport_context); 933 934 props->lid = MLX5_GET(hca_vport_context, ctx, lid); 935 props->lmc = MLX5_GET(hca_vport_context, ctx, lmc); 936 props->sm_lid = MLX5_GET(hca_vport_context, ctx, sm_lid); 937 props->sm_sl = MLX5_GET(hca_vport_context, ctx, sm_sl); 938 props->state = MLX5_GET(hca_vport_context, ctx, vport_state); 939 props->phys_state = MLX5_GET(hca_vport_context, ctx, 940 port_physical_state); 941 props->port_cap_flags = MLX5_GET(hca_vport_context, ctx, cap_mask1); 942 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size)); 943 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg); 944 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size)); 945 props->bad_pkey_cntr = MLX5_GET(hca_vport_context, ctx, 946 pkey_violation_counter); 947 props->qkey_viol_cntr = MLX5_GET(hca_vport_context, ctx, 948 qkey_violation_counter); 949 props->subnet_timeout = MLX5_GET(hca_vport_context, ctx, 950 subnet_timeout); 951 props->init_type_reply = MLX5_GET(hca_vport_context, ctx, 952 init_type_reply); 953 props->grh_required = MLX5_GET(hca_vport_context, ctx, grh_required); 954 955 ptys->proto_mask |= MLX5_PTYS_IB; 956 ptys->local_port = port; 957 err = mlx5_core_access_ptys(mdev, ptys, 0); 958 if (err) 959 goto out; 960 961 err = translate_active_width(ibdev, ptys->ib_link_width_oper, 962 &props->active_width); 963 if (err) 964 goto out; 965 966 props->active_speed = (u8)ptys->ib_proto_oper; 967 968 pmtu->local_port = port; 969 err = mlx5_core_access_pmtu(mdev, pmtu, 0); 970 if (err) 971 goto out; 972 973 props->max_mtu = pmtu->max_mtu; 974 props->active_mtu = pmtu->oper_mtu; 975 976 memset(&pvlc, 0, sizeof(pvlc)); 977 pvlc.local_port = port; 978 err = mlx5_core_access_pvlc(mdev, &pvlc, 0); 979 if (err) 980 goto out; 981 982 err = translate_max_vl_num(ibdev, pvlc.vl_hw_cap, 983 &props->max_vl_num); 984out: 985 kvfree(rep); 986 kfree(ptys); 987 kfree(pmtu); 988 return err; 989} 990 991int mlx5_ib_query_port(struct ib_device *ibdev, u8 port, 992 struct ib_port_attr *props) 993{ 994 switch (mlx5_get_vport_access_method(ibdev)) { 995 case MLX5_VPORT_ACCESS_METHOD_MAD: 996 return mlx5_query_mad_ifc_port(ibdev, port, props); 997 998 case MLX5_VPORT_ACCESS_METHOD_HCA: 999 return mlx5_query_hca_port(ibdev, port, props); 1000 1001 case MLX5_VPORT_ACCESS_METHOD_NIC: 1002 return mlx5_query_port_roce(ibdev, port, props); 1003 1004 default: 1005 return -EINVAL; 1006 } 1007} 1008 1009static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index, 1010 union ib_gid *gid) 1011{ 1012 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1013 struct mlx5_core_dev *mdev = dev->mdev; 1014 1015 switch (mlx5_get_vport_access_method(ibdev)) { 1016 case MLX5_VPORT_ACCESS_METHOD_MAD: 1017 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid); 1018 1019 case MLX5_VPORT_ACCESS_METHOD_HCA: 1020 return mlx5_query_hca_vport_gid(mdev, port, 0, index, gid); 1021 1022 default: 1023 return -EINVAL; 1024 } 1025 1026} 1027 1028static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, 1029 u16 *pkey) 1030{ 1031 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1032 struct mlx5_core_dev *mdev = dev->mdev; 1033 1034 switch (mlx5_get_vport_access_method(ibdev)) { 1035 case MLX5_VPORT_ACCESS_METHOD_MAD: 1036 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey); 1037 1038 case MLX5_VPORT_ACCESS_METHOD_HCA: 1039 case MLX5_VPORT_ACCESS_METHOD_NIC: 1040 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index, 1041 pkey); 1042 default: 1043 return -EINVAL; 1044 } 1045} 1046 1047static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask, 1048 struct ib_device_modify *props) 1049{ 1050 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1051 struct mlx5_reg_node_desc in; 1052 struct mlx5_reg_node_desc out; 1053 int err; 1054 1055 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) 1056 return -EOPNOTSUPP; 1057 1058 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC)) 1059 return 0; 1060 1061 /* 1062 * If possible, pass node desc to FW, so it can generate 1063 * a 144 trap. If cmd fails, just ignore. 1064 */ 1065 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1066 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out, 1067 sizeof(out), MLX5_REG_NODE_DESC, 0, 1); 1068 if (err) 1069 return err; 1070 1071 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX); 1072 1073 return err; 1074} 1075 1076static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask, 1077 struct ib_port_modify *props) 1078{ 1079 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1080 struct ib_port_attr attr; 1081 u32 tmp; 1082 int err; 1083 1084 /* 1085 * CM layer calls ib_modify_port() regardless of the link 1086 * layer. For Ethernet ports, qkey violation and Port 1087 * capabilities are meaningless. 1088 */ 1089 if (mlx5_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_ETHERNET) 1090 return 0; 1091 1092 mutex_lock(&dev->cap_mask_mutex); 1093 1094 err = mlx5_ib_query_port(ibdev, port, &attr); 1095 if (err) 1096 goto out; 1097 1098 tmp = (attr.port_cap_flags | props->set_port_cap_mask) & 1099 ~props->clr_port_cap_mask; 1100 1101 err = mlx5_set_port_caps(dev->mdev, port, tmp); 1102 1103out: 1104 mutex_unlock(&dev->cap_mask_mutex); 1105 return err; 1106} 1107 1108static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev, 1109 struct ib_udata *udata) 1110{ 1111 struct mlx5_ib_dev *dev = to_mdev(ibdev); 1112 struct mlx5_ib_alloc_ucontext_req_v2 req = {}; 1113 struct mlx5_ib_alloc_ucontext_resp resp = {}; 1114 struct mlx5_ib_ucontext *context; 1115 struct mlx5_uuar_info *uuari; 1116 struct mlx5_uar *uars; 1117 int gross_uuars; 1118 int num_uars; 1119 int ver; 1120 int uuarn; 1121 int err; 1122 int i; 1123 size_t reqlen; 1124 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2, 1125 max_cqe_version); 1126 1127 if (!dev->ib_active) 1128 return ERR_PTR(-EAGAIN); 1129 1130 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr)) 1131 return ERR_PTR(-EINVAL); 1132 1133 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr); 1134 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req)) 1135 ver = 0; 1136 else if (reqlen >= min_req_v2) 1137 ver = 2; 1138 else 1139 return ERR_PTR(-EINVAL); 1140 1141 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req))); 1142 if (err) 1143 return ERR_PTR(err); 1144 1145 if (req.flags) 1146 return ERR_PTR(-EINVAL); 1147 1148 if (req.total_num_uuars > MLX5_MAX_UUARS) 1149 return ERR_PTR(-ENOMEM); 1150 1151 if (req.total_num_uuars == 0) 1152 return ERR_PTR(-EINVAL); 1153 1154 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2) 1155 return ERR_PTR(-EOPNOTSUPP); 1156 1157 if (reqlen > sizeof(req) && 1158 !ib_is_udata_cleared(udata, sizeof(req), 1159 reqlen - sizeof(req))) 1160 return ERR_PTR(-EOPNOTSUPP); 1161 1162 req.total_num_uuars = ALIGN(req.total_num_uuars, 1163 MLX5_NON_FP_BF_REGS_PER_PAGE); 1164 if (req.num_low_latency_uuars > req.total_num_uuars - 1) 1165 return ERR_PTR(-EINVAL); 1166 1167 num_uars = req.total_num_uuars / MLX5_NON_FP_BF_REGS_PER_PAGE; 1168 gross_uuars = num_uars * MLX5_BF_REGS_PER_PAGE; 1169 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp); 1170 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf)) 1171 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size); 1172 resp.cache_line_size = cache_line_size(); 1173 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq); 1174 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq); 1175 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1176 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz); 1177 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz); 1178 resp.cqe_version = min_t(__u8, 1179 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version), 1180 req.max_cqe_version); 1181 resp.response_length = min(offsetof(typeof(resp), response_length) + 1182 sizeof(resp.response_length), udata->outlen); 1183 1184 context = kzalloc(sizeof(*context), GFP_KERNEL); 1185 if (!context) 1186 return ERR_PTR(-ENOMEM); 1187 1188 uuari = &context->uuari; 1189 mutex_init(&uuari->lock); 1190 uars = kcalloc(num_uars, sizeof(*uars), GFP_KERNEL); 1191 if (!uars) { 1192 err = -ENOMEM; 1193 goto out_ctx; 1194 } 1195 1196 uuari->bitmap = kcalloc(BITS_TO_LONGS(gross_uuars), 1197 sizeof(*uuari->bitmap), 1198 GFP_KERNEL); 1199 if (!uuari->bitmap) { 1200 err = -ENOMEM; 1201 goto out_uar_ctx; 1202 } 1203 /* 1204 * clear all fast path uuars 1205 */ 1206 for (i = 0; i < gross_uuars; i++) { 1207 uuarn = i & 3; 1208 if (uuarn == 2 || uuarn == 3) 1209 set_bit(i, uuari->bitmap); 1210 } 1211 1212 uuari->count = kcalloc(gross_uuars, sizeof(*uuari->count), GFP_KERNEL); 1213 if (!uuari->count) { 1214 err = -ENOMEM; 1215 goto out_bitmap; 1216 } 1217 1218 for (i = 0; i < num_uars; i++) { 1219 err = mlx5_cmd_alloc_uar(dev->mdev, &uars[i].index); 1220 if (err) 1221 goto out_count; 1222 } 1223 1224#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1225 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range; 1226#endif 1227 1228 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) { 1229 err = mlx5_alloc_transport_domain(dev->mdev, 1230 &context->tdn); 1231 if (err) 1232 goto out_uars; 1233 } 1234 1235 INIT_LIST_HEAD(&context->vma_private_list); 1236 INIT_LIST_HEAD(&context->db_page_list); 1237 mutex_init(&context->db_page_mutex); 1238 1239 resp.tot_uuars = req.total_num_uuars; 1240 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports); 1241 1242 if (field_avail(typeof(resp), cqe_version, udata->outlen)) 1243 resp.response_length += sizeof(resp.cqe_version); 1244 1245 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) { 1246 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE | 1247 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH; 1248 resp.response_length += sizeof(resp.cmds_supp_uhw); 1249 } 1250 1251 /* 1252 * We don't want to expose information from the PCI bar that is located 1253 * after 4096 bytes, so if the arch only supports larger pages, let's 1254 * pretend we don't support reading the HCA's core clock. This is also 1255 * forced by mmap function. 1256 */ 1257 if (PAGE_SIZE <= 4096 && 1258 field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) { 1259 resp.comp_mask |= 1260 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET; 1261 resp.hca_core_clock_offset = 1262 offsetof(struct mlx5_init_seg, internal_timer_h) % 1263 PAGE_SIZE; 1264 resp.response_length += sizeof(resp.hca_core_clock_offset) + 1265 sizeof(resp.reserved2); 1266 } 1267 1268 err = ib_copy_to_udata(udata, &resp, resp.response_length); 1269 if (err) 1270 goto out_td; 1271 1272 uuari->ver = ver; 1273 uuari->num_low_latency_uuars = req.num_low_latency_uuars; 1274 uuari->uars = uars; 1275 uuari->num_uars = num_uars; 1276 context->cqe_version = resp.cqe_version; 1277 1278 return &context->ibucontext; 1279 1280out_td: 1281 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1282 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1283 1284out_uars: 1285 for (i--; i >= 0; i--) 1286 mlx5_cmd_free_uar(dev->mdev, uars[i].index); 1287out_count: 1288 kfree(uuari->count); 1289 1290out_bitmap: 1291 kfree(uuari->bitmap); 1292 1293out_uar_ctx: 1294 kfree(uars); 1295 1296out_ctx: 1297 kfree(context); 1298 return ERR_PTR(err); 1299} 1300 1301static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext) 1302{ 1303 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1304 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1305 struct mlx5_uuar_info *uuari = &context->uuari; 1306 int i; 1307 1308 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) 1309 mlx5_dealloc_transport_domain(dev->mdev, context->tdn); 1310 1311 for (i = 0; i < uuari->num_uars; i++) { 1312 if (mlx5_cmd_free_uar(dev->mdev, uuari->uars[i].index)) 1313 mlx5_ib_warn(dev, "failed to free UAR 0x%x\n", uuari->uars[i].index); 1314 } 1315 1316 kfree(uuari->count); 1317 kfree(uuari->bitmap); 1318 kfree(uuari->uars); 1319 kfree(context); 1320 1321 return 0; 1322} 1323 1324static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev, int index) 1325{ 1326 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + index; 1327} 1328 1329static int get_command(unsigned long offset) 1330{ 1331 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK; 1332} 1333 1334static int get_arg(unsigned long offset) 1335{ 1336 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1); 1337} 1338 1339static int get_index(unsigned long offset) 1340{ 1341 return get_arg(offset); 1342} 1343 1344static void mlx5_ib_vma_open(struct vm_area_struct *area) 1345{ 1346 /* vma_open is called when a new VMA is created on top of our VMA. This 1347 * is done through either mremap flow or split_vma (usually due to 1348 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA, 1349 * as this VMA is strongly hardware related. Therefore we set the 1350 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from 1351 * calling us again and trying to do incorrect actions. We assume that 1352 * the original VMA size is exactly a single page, and therefore all 1353 * "splitting" operation will not happen to it. 1354 */ 1355 area->vm_ops = NULL; 1356} 1357 1358static void mlx5_ib_vma_close(struct vm_area_struct *area) 1359{ 1360 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data; 1361 1362 /* It's guaranteed that all VMAs opened on a FD are closed before the 1363 * file itself is closed, therefore no sync is needed with the regular 1364 * closing flow. (e.g. mlx5 ib_dealloc_ucontext) 1365 * However need a sync with accessing the vma as part of 1366 * mlx5_ib_disassociate_ucontext. 1367 * The close operation is usually called under mm->mmap_sem except when 1368 * process is exiting. 1369 * The exiting case is handled explicitly as part of 1370 * mlx5_ib_disassociate_ucontext. 1371 */ 1372 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data; 1373 1374 /* setting the vma context pointer to null in the mlx5_ib driver's 1375 * private data, to protect a race condition in 1376 * mlx5_ib_disassociate_ucontext(). 1377 */ 1378 mlx5_ib_vma_priv_data->vma = NULL; 1379 list_del(&mlx5_ib_vma_priv_data->list); 1380 kfree(mlx5_ib_vma_priv_data); 1381} 1382 1383static const struct vm_operations_struct mlx5_ib_vm_ops = { 1384 .open = mlx5_ib_vma_open, 1385 .close = mlx5_ib_vma_close 1386}; 1387 1388static int mlx5_ib_set_vma_data(struct vm_area_struct *vma, 1389 struct mlx5_ib_ucontext *ctx) 1390{ 1391 struct mlx5_ib_vma_private_data *vma_prv; 1392 struct list_head *vma_head = &ctx->vma_private_list; 1393 1394 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL); 1395 if (!vma_prv) 1396 return -ENOMEM; 1397 1398 vma_prv->vma = vma; 1399 vma->vm_private_data = vma_prv; 1400 vma->vm_ops = &mlx5_ib_vm_ops; 1401 1402 list_add(&vma_prv->list, vma_head); 1403 1404 return 0; 1405} 1406 1407static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext) 1408{ 1409 int ret; 1410 struct vm_area_struct *vma; 1411 struct mlx5_ib_vma_private_data *vma_private, *n; 1412 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1413 struct task_struct *owning_process = NULL; 1414 struct mm_struct *owning_mm = NULL; 1415 1416 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID); 1417 if (!owning_process) 1418 return; 1419 1420 owning_mm = get_task_mm(owning_process); 1421 if (!owning_mm) { 1422 pr_info("no mm, disassociate ucontext is pending task termination\n"); 1423 while (1) { 1424 put_task_struct(owning_process); 1425 usleep_range(1000, 2000); 1426 owning_process = get_pid_task(ibcontext->tgid, 1427 PIDTYPE_PID); 1428 if (!owning_process || owning_process->task_thread-> 1429 td_proc->p_state == PRS_ZOMBIE) { 1430 pr_info("disassociate ucontext done, task was terminated\n"); 1431 /* in case task was dead need to release the 1432 * task struct. 1433 */ 1434 if (owning_process) 1435 put_task_struct(owning_process); 1436 return; 1437 } 1438 } 1439 } 1440 1441 /* need to protect from a race on closing the vma as part of 1442 * mlx5_ib_vma_close. 1443 */ 1444 down_write(&owning_mm->mmap_sem); 1445 list_for_each_entry_safe(vma_private, n, &context->vma_private_list, 1446 list) { 1447 vma = vma_private->vma; 1448 ret = zap_vma_ptes(vma, vma->vm_start, 1449 PAGE_SIZE); 1450 if (ret == -ENOTSUP) { 1451 if (bootverbose) 1452 WARN_ONCE( 1453 "%s: zap_vma_ptes not implemented for unmanaged mappings", __func__); 1454 } else { 1455 WARN(ret, "%s: zap_vma_ptes failed, error %d", 1456 __func__, -ret); 1457 } 1458 /* context going to be destroyed, should 1459 * not access ops any more. 1460 */ 1461 /* XXXKIB vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); */ 1462 vma->vm_ops = NULL; 1463 list_del(&vma_private->list); 1464 kfree(vma_private); 1465 } 1466 up_write(&owning_mm->mmap_sem); 1467 mmput(owning_mm); 1468 put_task_struct(owning_process); 1469} 1470 1471static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd) 1472{ 1473 switch (cmd) { 1474 case MLX5_IB_MMAP_WC_PAGE: 1475 return "WC"; 1476 case MLX5_IB_MMAP_REGULAR_PAGE: 1477 return "best effort WC"; 1478 case MLX5_IB_MMAP_NC_PAGE: 1479 return "NC"; 1480 default: 1481 return NULL; 1482 } 1483} 1484 1485static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd, 1486 struct vm_area_struct *vma, 1487 struct mlx5_ib_ucontext *context) 1488{ 1489 struct mlx5_uuar_info *uuari = &context->uuari; 1490 int err; 1491 unsigned long idx; 1492 phys_addr_t pfn, pa; 1493 pgprot_t prot; 1494 1495 switch (cmd) { 1496 case MLX5_IB_MMAP_WC_PAGE: 1497/* Some architectures don't support WC memory */ 1498#if defined(CONFIG_X86) 1499 if (!pat_enabled()) 1500 return -EPERM; 1501#elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU))) 1502 return -EPERM; 1503#endif 1504 /* fall through */ 1505 case MLX5_IB_MMAP_REGULAR_PAGE: 1506 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */ 1507 prot = pgprot_writecombine(vma->vm_page_prot); 1508 break; 1509 case MLX5_IB_MMAP_NC_PAGE: 1510 prot = pgprot_noncached(vma->vm_page_prot); 1511 break; 1512 default: 1513 return -EINVAL; 1514 } 1515 1516 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1517 return -EINVAL; 1518 1519 idx = get_index(vma->vm_pgoff); 1520 if (idx >= uuari->num_uars) 1521 return -EINVAL; 1522 1523 pfn = uar_index2pfn(dev, uuari->uars[idx].index); 1524 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn); 1525 1526 vma->vm_page_prot = prot; 1527 err = io_remap_pfn_range(vma, vma->vm_start, pfn, 1528 PAGE_SIZE, vma->vm_page_prot); 1529 if (err) { 1530 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%llx, pfn=%pa, mmap_cmd=%s\n", 1531 err, (unsigned long long)vma->vm_start, &pfn, mmap_cmd2str(cmd)); 1532 return -EAGAIN; 1533 } 1534 1535 pa = pfn << PAGE_SHIFT; 1536 mlx5_ib_dbg(dev, "mapped %s at 0x%llx, PA %pa\n", mmap_cmd2str(cmd), 1537 (unsigned long long)vma->vm_start, &pa); 1538 1539 return mlx5_ib_set_vma_data(vma, context); 1540} 1541 1542static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma) 1543{ 1544 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext); 1545 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device); 1546 unsigned long command; 1547 phys_addr_t pfn; 1548 1549 command = get_command(vma->vm_pgoff); 1550 switch (command) { 1551 case MLX5_IB_MMAP_WC_PAGE: 1552 case MLX5_IB_MMAP_NC_PAGE: 1553 case MLX5_IB_MMAP_REGULAR_PAGE: 1554 return uar_mmap(dev, command, vma, context); 1555 1556 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES: 1557 return -ENOSYS; 1558 1559 case MLX5_IB_MMAP_CORE_CLOCK: 1560 if (vma->vm_end - vma->vm_start != PAGE_SIZE) 1561 return -EINVAL; 1562 1563 if (vma->vm_flags & VM_WRITE) 1564 return -EPERM; 1565 1566 /* Don't expose to user-space information it shouldn't have */ 1567 if (PAGE_SIZE > 4096) 1568 return -EOPNOTSUPP; 1569 1570 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); 1571 pfn = (dev->mdev->iseg_base + 1572 offsetof(struct mlx5_init_seg, internal_timer_h)) >> 1573 PAGE_SHIFT; 1574 if (io_remap_pfn_range(vma, vma->vm_start, pfn, 1575 PAGE_SIZE, vma->vm_page_prot)) 1576 return -EAGAIN; 1577 1578 mlx5_ib_dbg(dev, "mapped internal timer at 0x%llx, PA 0x%llx\n", 1579 (unsigned long long)vma->vm_start, 1580 (unsigned long long)pfn << PAGE_SHIFT); 1581 break; 1582 1583 default: 1584 return -EINVAL; 1585 } 1586 1587 return 0; 1588} 1589 1590static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev, 1591 struct ib_ucontext *context, 1592 struct ib_udata *udata) 1593{ 1594 struct mlx5_ib_alloc_pd_resp resp; 1595 struct mlx5_ib_pd *pd; 1596 int err; 1597 1598 pd = kmalloc(sizeof(*pd), GFP_KERNEL); 1599 if (!pd) 1600 return ERR_PTR(-ENOMEM); 1601 1602 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn); 1603 if (err) { 1604 kfree(pd); 1605 return ERR_PTR(err); 1606 } 1607 1608 if (context) { 1609 resp.pdn = pd->pdn; 1610 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) { 1611 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn); 1612 kfree(pd); 1613 return ERR_PTR(-EFAULT); 1614 } 1615 } 1616 1617 return &pd->ibpd; 1618} 1619 1620static int mlx5_ib_dealloc_pd(struct ib_pd *pd) 1621{ 1622 struct mlx5_ib_dev *mdev = to_mdev(pd->device); 1623 struct mlx5_ib_pd *mpd = to_mpd(pd); 1624 1625 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn); 1626 kfree(mpd); 1627 1628 return 0; 1629} 1630 1631enum { 1632 MATCH_CRITERIA_ENABLE_OUTER_BIT, 1633 MATCH_CRITERIA_ENABLE_MISC_BIT, 1634 MATCH_CRITERIA_ENABLE_INNER_BIT 1635}; 1636 1637#define HEADER_IS_ZERO(match_criteria, headers) \ 1638 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \ 1639 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \ 1640 1641static u8 get_match_criteria_enable(u32 *match_criteria) 1642{ 1643 u8 match_criteria_enable; 1644 1645 match_criteria_enable = 1646 (!HEADER_IS_ZERO(match_criteria, outer_headers)) << 1647 MATCH_CRITERIA_ENABLE_OUTER_BIT; 1648 match_criteria_enable |= 1649 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) << 1650 MATCH_CRITERIA_ENABLE_MISC_BIT; 1651 match_criteria_enable |= 1652 (!HEADER_IS_ZERO(match_criteria, inner_headers)) << 1653 MATCH_CRITERIA_ENABLE_INNER_BIT; 1654 1655 return match_criteria_enable; 1656} 1657 1658static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val) 1659{ 1660 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask); 1661 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val); 1662} 1663 1664static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val) 1665{ 1666 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask); 1667 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val); 1668 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2); 1669 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2); 1670} 1671 1672#define LAST_ETH_FIELD vlan_tag 1673#define LAST_IB_FIELD sl 1674#define LAST_IPV4_FIELD tos 1675#define LAST_IPV6_FIELD traffic_class 1676#define LAST_TCP_UDP_FIELD src_port 1677 1678/* Field is the last supported field */ 1679#define FIELDS_NOT_SUPPORTED(filter, field)\ 1680 memchr_inv((void *)&filter.field +\ 1681 sizeof(filter.field), 0,\ 1682 sizeof(filter) -\ 1683 offsetof(typeof(filter), field) -\ 1684 sizeof(filter.field)) 1685 1686static int parse_flow_attr(u32 *match_c, u32 *match_v, 1687 const union ib_flow_spec *ib_spec) 1688{ 1689 void *outer_headers_c = MLX5_ADDR_OF(fte_match_param, match_c, 1690 outer_headers); 1691 void *outer_headers_v = MLX5_ADDR_OF(fte_match_param, match_v, 1692 outer_headers); 1693 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c, 1694 misc_parameters); 1695 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v, 1696 misc_parameters); 1697 1698 switch (ib_spec->type) { 1699 case IB_FLOW_SPEC_ETH: 1700 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD)) 1701 return -ENOTSUPP; 1702 1703 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1704 dmac_47_16), 1705 ib_spec->eth.mask.dst_mac); 1706 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1707 dmac_47_16), 1708 ib_spec->eth.val.dst_mac); 1709 1710 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1711 smac_47_16), 1712 ib_spec->eth.mask.src_mac); 1713 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1714 smac_47_16), 1715 ib_spec->eth.val.src_mac); 1716 1717 if (ib_spec->eth.mask.vlan_tag) { 1718 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1719 cvlan_tag, 1); 1720 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1721 cvlan_tag, 1); 1722 1723 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1724 first_vid, ntohs(ib_spec->eth.mask.vlan_tag)); 1725 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1726 first_vid, ntohs(ib_spec->eth.val.vlan_tag)); 1727 1728 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1729 first_cfi, 1730 ntohs(ib_spec->eth.mask.vlan_tag) >> 12); 1731 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1732 first_cfi, 1733 ntohs(ib_spec->eth.val.vlan_tag) >> 12); 1734 1735 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1736 first_prio, 1737 ntohs(ib_spec->eth.mask.vlan_tag) >> 13); 1738 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1739 first_prio, 1740 ntohs(ib_spec->eth.val.vlan_tag) >> 13); 1741 } 1742 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1743 ethertype, ntohs(ib_spec->eth.mask.ether_type)); 1744 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1745 ethertype, ntohs(ib_spec->eth.val.ether_type)); 1746 break; 1747 case IB_FLOW_SPEC_IPV4: 1748 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD)) 1749 return -ENOTSUPP; 1750 1751 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1752 ethertype, 0xffff); 1753 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1754 ethertype, ETH_P_IP); 1755 1756 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1757 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1758 &ib_spec->ipv4.mask.src_ip, 1759 sizeof(ib_spec->ipv4.mask.src_ip)); 1760 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1761 src_ipv4_src_ipv6.ipv4_layout.ipv4), 1762 &ib_spec->ipv4.val.src_ip, 1763 sizeof(ib_spec->ipv4.val.src_ip)); 1764 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1765 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1766 &ib_spec->ipv4.mask.dst_ip, 1767 sizeof(ib_spec->ipv4.mask.dst_ip)); 1768 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1769 dst_ipv4_dst_ipv6.ipv4_layout.ipv4), 1770 &ib_spec->ipv4.val.dst_ip, 1771 sizeof(ib_spec->ipv4.val.dst_ip)); 1772 1773 set_tos(outer_headers_c, outer_headers_v, 1774 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos); 1775 1776 set_proto(outer_headers_c, outer_headers_v, 1777 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto); 1778 break; 1779 case IB_FLOW_SPEC_IPV6: 1780 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD)) 1781 return -ENOTSUPP; 1782 1783 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, 1784 ethertype, 0xffff); 1785 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, 1786 ethertype, IPPROTO_IPV6); 1787 1788 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1789 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1790 &ib_spec->ipv6.mask.src_ip, 1791 sizeof(ib_spec->ipv6.mask.src_ip)); 1792 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1793 src_ipv4_src_ipv6.ipv6_layout.ipv6), 1794 &ib_spec->ipv6.val.src_ip, 1795 sizeof(ib_spec->ipv6.val.src_ip)); 1796 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_c, 1797 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1798 &ib_spec->ipv6.mask.dst_ip, 1799 sizeof(ib_spec->ipv6.mask.dst_ip)); 1800 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, outer_headers_v, 1801 dst_ipv4_dst_ipv6.ipv6_layout.ipv6), 1802 &ib_spec->ipv6.val.dst_ip, 1803 sizeof(ib_spec->ipv6.val.dst_ip)); 1804 1805 set_tos(outer_headers_c, outer_headers_v, 1806 ib_spec->ipv6.mask.traffic_class, 1807 ib_spec->ipv6.val.traffic_class); 1808 1809 set_proto(outer_headers_c, outer_headers_v, 1810 ib_spec->ipv6.mask.next_hdr, 1811 ib_spec->ipv6.val.next_hdr); 1812 1813 MLX5_SET(fte_match_set_misc, misc_params_c, 1814 outer_ipv6_flow_label, 1815 ntohl(ib_spec->ipv6.mask.flow_label)); 1816 MLX5_SET(fte_match_set_misc, misc_params_v, 1817 outer_ipv6_flow_label, 1818 ntohl(ib_spec->ipv6.val.flow_label)); 1819 break; 1820 case IB_FLOW_SPEC_TCP: 1821 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1822 LAST_TCP_UDP_FIELD)) 1823 return -ENOTSUPP; 1824 1825 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1826 0xff); 1827 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1828 IPPROTO_TCP); 1829 1830 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_sport, 1831 ntohs(ib_spec->tcp_udp.mask.src_port)); 1832 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_sport, 1833 ntohs(ib_spec->tcp_udp.val.src_port)); 1834 1835 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, tcp_dport, 1836 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1837 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, tcp_dport, 1838 ntohs(ib_spec->tcp_udp.val.dst_port)); 1839 break; 1840 case IB_FLOW_SPEC_UDP: 1841 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask, 1842 LAST_TCP_UDP_FIELD)) 1843 return -ENOTSUPP; 1844 1845 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, ip_protocol, 1846 0xff); 1847 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, ip_protocol, 1848 IPPROTO_UDP); 1849 1850 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_sport, 1851 ntohs(ib_spec->tcp_udp.mask.src_port)); 1852 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_sport, 1853 ntohs(ib_spec->tcp_udp.val.src_port)); 1854 1855 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_c, udp_dport, 1856 ntohs(ib_spec->tcp_udp.mask.dst_port)); 1857 MLX5_SET(fte_match_set_lyr_2_4, outer_headers_v, udp_dport, 1858 ntohs(ib_spec->tcp_udp.val.dst_port)); 1859 break; 1860 default: 1861 return -EINVAL; 1862 } 1863 1864 return 0; 1865} 1866 1867/* If a flow could catch both multicast and unicast packets, 1868 * it won't fall into the multicast flow steering table and this rule 1869 * could steal other multicast packets. 1870 */ 1871static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr) 1872{ 1873 struct ib_flow_spec_eth *eth_spec; 1874 1875 if (ib_attr->type != IB_FLOW_ATTR_NORMAL || 1876 ib_attr->size < sizeof(struct ib_flow_attr) + 1877 sizeof(struct ib_flow_spec_eth) || 1878 ib_attr->num_of_specs < 1) 1879 return false; 1880 1881 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1); 1882 if (eth_spec->type != IB_FLOW_SPEC_ETH || 1883 eth_spec->size != sizeof(*eth_spec)) 1884 return false; 1885 1886 return is_multicast_ether_addr(eth_spec->mask.dst_mac) && 1887 is_multicast_ether_addr(eth_spec->val.dst_mac); 1888} 1889 1890static bool is_valid_attr(const struct ib_flow_attr *flow_attr) 1891{ 1892 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1); 1893 bool has_ipv4_spec = false; 1894 bool eth_type_ipv4 = true; 1895 unsigned int spec_index; 1896 1897 /* Validate that ethertype is correct */ 1898 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 1899 if (ib_spec->type == IB_FLOW_SPEC_ETH && 1900 ib_spec->eth.mask.ether_type) { 1901 if (!((ib_spec->eth.mask.ether_type == htons(0xffff)) && 1902 ib_spec->eth.val.ether_type == htons(ETH_P_IP))) 1903 eth_type_ipv4 = false; 1904 } else if (ib_spec->type == IB_FLOW_SPEC_IPV4) { 1905 has_ipv4_spec = true; 1906 } 1907 ib_spec = (void *)ib_spec + ib_spec->size; 1908 } 1909 return !has_ipv4_spec || eth_type_ipv4; 1910} 1911 1912static void put_flow_table(struct mlx5_ib_dev *dev, 1913 struct mlx5_ib_flow_prio *prio, bool ft_added) 1914{ 1915 prio->refcount -= !!ft_added; 1916 if (!prio->refcount) { 1917 mlx5_destroy_flow_table(prio->flow_table); 1918 prio->flow_table = NULL; 1919 } 1920} 1921 1922static int mlx5_ib_destroy_flow(struct ib_flow *flow_id) 1923{ 1924 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device); 1925 struct mlx5_ib_flow_handler *handler = container_of(flow_id, 1926 struct mlx5_ib_flow_handler, 1927 ibflow); 1928 struct mlx5_ib_flow_handler *iter, *tmp; 1929 1930 mutex_lock(&dev->flow_db.lock); 1931 1932 list_for_each_entry_safe(iter, tmp, &handler->list, list) { 1933 mlx5_del_flow_rule(iter->rule); 1934 put_flow_table(dev, iter->prio, true); 1935 list_del(&iter->list); 1936 kfree(iter); 1937 } 1938 1939 mlx5_del_flow_rule(handler->rule); 1940 put_flow_table(dev, handler->prio, true); 1941 mutex_unlock(&dev->flow_db.lock); 1942 1943 kfree(handler); 1944 1945 return 0; 1946} 1947 1948static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap) 1949{ 1950 priority *= 2; 1951 if (!dont_trap) 1952 priority++; 1953 return priority; 1954} 1955 1956enum flow_table_type { 1957 MLX5_IB_FT_RX, 1958 MLX5_IB_FT_TX 1959}; 1960 1961#define MLX5_FS_MAX_TYPES 10 1962#define MLX5_FS_MAX_ENTRIES 32000UL 1963static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev, 1964 struct ib_flow_attr *flow_attr, 1965 enum flow_table_type ft_type) 1966{ 1967 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP; 1968 struct mlx5_flow_namespace *ns = NULL; 1969 struct mlx5_ib_flow_prio *prio; 1970 struct mlx5_flow_table *ft; 1971 int num_entries; 1972 int num_groups; 1973 int priority; 1974 int err = 0; 1975 1976 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 1977 if (flow_is_multicast_only(flow_attr) && 1978 !dont_trap) 1979 priority = MLX5_IB_FLOW_MCAST_PRIO; 1980 else 1981 priority = ib_prio_to_core_prio(flow_attr->priority, 1982 dont_trap); 1983 ns = mlx5_get_flow_namespace(dev->mdev, 1984 MLX5_FLOW_NAMESPACE_BYPASS); 1985 num_entries = MLX5_FS_MAX_ENTRIES; 1986 num_groups = MLX5_FS_MAX_TYPES; 1987 prio = &dev->flow_db.prios[priority]; 1988 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 1989 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 1990 ns = mlx5_get_flow_namespace(dev->mdev, 1991 MLX5_FLOW_NAMESPACE_LEFTOVERS); 1992 build_leftovers_ft_param("bypass", &priority, 1993 &num_entries, 1994 &num_groups); 1995 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO]; 1996 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 1997 if (!MLX5_CAP_FLOWTABLE(dev->mdev, 1998 allow_sniffer_and_nic_rx_shared_tir)) 1999 return ERR_PTR(-ENOTSUPP); 2000 2001 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ? 2002 MLX5_FLOW_NAMESPACE_SNIFFER_RX : 2003 MLX5_FLOW_NAMESPACE_SNIFFER_TX); 2004 2005 prio = &dev->flow_db.sniffer[ft_type]; 2006 priority = 0; 2007 num_entries = 1; 2008 num_groups = 1; 2009 } 2010 2011 if (!ns) 2012 return ERR_PTR(-ENOTSUPP); 2013 2014 ft = prio->flow_table; 2015 if (!ft) { 2016 ft = mlx5_create_auto_grouped_flow_table(ns, priority, "bypass", 2017 num_entries, 2018 num_groups); 2019 2020 if (!IS_ERR(ft)) { 2021 prio->refcount = 0; 2022 prio->flow_table = ft; 2023 } else { 2024 err = PTR_ERR(ft); 2025 } 2026 } 2027 2028 return err ? ERR_PTR(err) : prio; 2029} 2030 2031static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev, 2032 struct mlx5_ib_flow_prio *ft_prio, 2033 const struct ib_flow_attr *flow_attr, 2034 struct mlx5_flow_destination *dst) 2035{ 2036 struct mlx5_flow_table *ft = ft_prio->flow_table; 2037 struct mlx5_ib_flow_handler *handler; 2038 struct mlx5_flow_spec *spec; 2039 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr); 2040 unsigned int spec_index; 2041 u32 action; 2042 int err = 0; 2043 2044 if (!is_valid_attr(flow_attr)) 2045 return ERR_PTR(-EINVAL); 2046 2047 spec = mlx5_vzalloc(sizeof(*spec)); 2048 handler = kzalloc(sizeof(*handler), GFP_KERNEL); 2049 if (!handler || !spec) { 2050 err = -ENOMEM; 2051 goto free; 2052 } 2053 2054 INIT_LIST_HEAD(&handler->list); 2055 2056 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) { 2057 err = parse_flow_attr(spec->match_criteria, 2058 spec->match_value, ib_flow); 2059 if (err < 0) 2060 goto free; 2061 2062 ib_flow += ((union ib_flow_spec *)ib_flow)->size; 2063 } 2064 2065 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria); 2066 action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST : 2067 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO; 2068 handler->rule = mlx5_add_flow_rule(ft, spec->match_criteria_enable, 2069 spec->match_criteria, 2070 spec->match_value, 2071 action, 2072 MLX5_FS_DEFAULT_FLOW_TAG, 2073 dst); 2074 2075 if (IS_ERR(handler->rule)) { 2076 err = PTR_ERR(handler->rule); 2077 goto free; 2078 } 2079 2080 ft_prio->refcount++; 2081 handler->prio = ft_prio; 2082 2083 ft_prio->flow_table = ft; 2084free: 2085 if (err) 2086 kfree(handler); 2087 kvfree(spec); 2088 return err ? ERR_PTR(err) : handler; 2089} 2090 2091static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev, 2092 struct mlx5_ib_flow_prio *ft_prio, 2093 struct ib_flow_attr *flow_attr, 2094 struct mlx5_flow_destination *dst) 2095{ 2096 struct mlx5_ib_flow_handler *handler_dst = NULL; 2097 struct mlx5_ib_flow_handler *handler = NULL; 2098 2099 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL); 2100 if (!IS_ERR(handler)) { 2101 handler_dst = create_flow_rule(dev, ft_prio, 2102 flow_attr, dst); 2103 if (IS_ERR(handler_dst)) { 2104 mlx5_del_flow_rule(handler->rule); 2105 ft_prio->refcount--; 2106 kfree(handler); 2107 handler = handler_dst; 2108 } else { 2109 list_add(&handler_dst->list, &handler->list); 2110 } 2111 } 2112 2113 return handler; 2114} 2115enum { 2116 LEFTOVERS_MC, 2117 LEFTOVERS_UC, 2118}; 2119 2120static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev, 2121 struct mlx5_ib_flow_prio *ft_prio, 2122 struct ib_flow_attr *flow_attr, 2123 struct mlx5_flow_destination *dst) 2124{ 2125 struct mlx5_ib_flow_handler *handler_ucast = NULL; 2126 struct mlx5_ib_flow_handler *handler = NULL; 2127 2128 static struct { 2129 struct ib_flow_attr flow_attr; 2130 struct ib_flow_spec_eth eth_flow; 2131 } leftovers_specs[] = { 2132 [LEFTOVERS_MC] = { 2133 .flow_attr = { 2134 .num_of_specs = 1, 2135 .size = sizeof(leftovers_specs[0]) 2136 }, 2137 .eth_flow = { 2138 .type = IB_FLOW_SPEC_ETH, 2139 .size = sizeof(struct ib_flow_spec_eth), 2140 .mask = {.dst_mac = {0x1} }, 2141 .val = {.dst_mac = {0x1} } 2142 } 2143 }, 2144 [LEFTOVERS_UC] = { 2145 .flow_attr = { 2146 .num_of_specs = 1, 2147 .size = sizeof(leftovers_specs[0]) 2148 }, 2149 .eth_flow = { 2150 .type = IB_FLOW_SPEC_ETH, 2151 .size = sizeof(struct ib_flow_spec_eth), 2152 .mask = {.dst_mac = {0x1} }, 2153 .val = {.dst_mac = {} } 2154 } 2155 } 2156 }; 2157 2158 handler = create_flow_rule(dev, ft_prio, 2159 &leftovers_specs[LEFTOVERS_MC].flow_attr, 2160 dst); 2161 if (!IS_ERR(handler) && 2162 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) { 2163 handler_ucast = create_flow_rule(dev, ft_prio, 2164 &leftovers_specs[LEFTOVERS_UC].flow_attr, 2165 dst); 2166 if (IS_ERR(handler_ucast)) { 2167 mlx5_del_flow_rule(handler->rule); 2168 ft_prio->refcount--; 2169 kfree(handler); 2170 handler = handler_ucast; 2171 } else { 2172 list_add(&handler_ucast->list, &handler->list); 2173 } 2174 } 2175 2176 return handler; 2177} 2178 2179static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev, 2180 struct mlx5_ib_flow_prio *ft_rx, 2181 struct mlx5_ib_flow_prio *ft_tx, 2182 struct mlx5_flow_destination *dst) 2183{ 2184 struct mlx5_ib_flow_handler *handler_rx; 2185 struct mlx5_ib_flow_handler *handler_tx; 2186 int err; 2187 static const struct ib_flow_attr flow_attr = { 2188 .num_of_specs = 0, 2189 .size = sizeof(flow_attr) 2190 }; 2191 2192 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst); 2193 if (IS_ERR(handler_rx)) { 2194 err = PTR_ERR(handler_rx); 2195 goto err; 2196 } 2197 2198 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst); 2199 if (IS_ERR(handler_tx)) { 2200 err = PTR_ERR(handler_tx); 2201 goto err_tx; 2202 } 2203 2204 list_add(&handler_tx->list, &handler_rx->list); 2205 2206 return handler_rx; 2207 2208err_tx: 2209 mlx5_del_flow_rule(handler_rx->rule); 2210 ft_rx->refcount--; 2211 kfree(handler_rx); 2212err: 2213 return ERR_PTR(err); 2214} 2215 2216static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp, 2217 struct ib_flow_attr *flow_attr, 2218 int domain) 2219{ 2220 struct mlx5_ib_dev *dev = to_mdev(qp->device); 2221 struct mlx5_ib_qp *mqp = to_mqp(qp); 2222 struct mlx5_ib_flow_handler *handler = NULL; 2223 struct mlx5_flow_destination *dst = NULL; 2224 struct mlx5_ib_flow_prio *ft_prio_tx = NULL; 2225 struct mlx5_ib_flow_prio *ft_prio; 2226 int err; 2227 2228 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) 2229 return ERR_PTR(-ENOSPC); 2230 2231 if (domain != IB_FLOW_DOMAIN_USER || 2232 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) || 2233 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP)) 2234 return ERR_PTR(-EINVAL); 2235 2236 dst = kzalloc(sizeof(*dst), GFP_KERNEL); 2237 if (!dst) 2238 return ERR_PTR(-ENOMEM); 2239 2240 mutex_lock(&dev->flow_db.lock); 2241 2242 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX); 2243 if (IS_ERR(ft_prio)) { 2244 err = PTR_ERR(ft_prio); 2245 goto unlock; 2246 } 2247 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2248 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX); 2249 if (IS_ERR(ft_prio_tx)) { 2250 err = PTR_ERR(ft_prio_tx); 2251 ft_prio_tx = NULL; 2252 goto destroy_ft; 2253 } 2254 } 2255 2256 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR; 2257 if (mqp->flags & MLX5_IB_QP_RSS) 2258 dst->tir_num = mqp->rss_qp.tirn; 2259 else 2260 dst->tir_num = mqp->raw_packet_qp.rq.tirn; 2261 2262 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) { 2263 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) { 2264 handler = create_dont_trap_rule(dev, ft_prio, 2265 flow_attr, dst); 2266 } else { 2267 handler = create_flow_rule(dev, ft_prio, flow_attr, 2268 dst); 2269 } 2270 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT || 2271 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) { 2272 handler = create_leftovers_rule(dev, ft_prio, flow_attr, 2273 dst); 2274 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) { 2275 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst); 2276 } else { 2277 err = -EINVAL; 2278 goto destroy_ft; 2279 } 2280 2281 if (IS_ERR(handler)) { 2282 err = PTR_ERR(handler); 2283 handler = NULL; 2284 goto destroy_ft; 2285 } 2286 2287 mutex_unlock(&dev->flow_db.lock); 2288 kfree(dst); 2289 2290 return &handler->ibflow; 2291 2292destroy_ft: 2293 put_flow_table(dev, ft_prio, false); 2294 if (ft_prio_tx) 2295 put_flow_table(dev, ft_prio_tx, false); 2296unlock: 2297 mutex_unlock(&dev->flow_db.lock); 2298 kfree(dst); 2299 kfree(handler); 2300 return ERR_PTR(err); 2301} 2302 2303static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2304{ 2305 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2306 int err; 2307 2308 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num); 2309 if (err) 2310 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n", 2311 ibqp->qp_num, gid->raw); 2312 2313 return err; 2314} 2315 2316static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid) 2317{ 2318 struct mlx5_ib_dev *dev = to_mdev(ibqp->device); 2319 int err; 2320 2321 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num); 2322 if (err) 2323 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n", 2324 ibqp->qp_num, gid->raw); 2325 2326 return err; 2327} 2328 2329static int init_node_data(struct mlx5_ib_dev *dev) 2330{ 2331 int err; 2332 2333 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc); 2334 if (err) 2335 return err; 2336 2337 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid); 2338} 2339 2340static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr, 2341 char *buf) 2342{ 2343 struct mlx5_ib_dev *dev = 2344 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2345 2346 return sprintf(buf, "%lld\n", (long long)dev->mdev->priv.fw_pages); 2347} 2348 2349static ssize_t show_reg_pages(struct device *device, 2350 struct device_attribute *attr, char *buf) 2351{ 2352 struct mlx5_ib_dev *dev = 2353 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2354 2355 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages)); 2356} 2357 2358static ssize_t show_hca(struct device *device, struct device_attribute *attr, 2359 char *buf) 2360{ 2361 struct mlx5_ib_dev *dev = 2362 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2363 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device); 2364} 2365 2366static ssize_t show_rev(struct device *device, struct device_attribute *attr, 2367 char *buf) 2368{ 2369 struct mlx5_ib_dev *dev = 2370 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2371 return sprintf(buf, "%x\n", dev->mdev->pdev->revision); 2372} 2373 2374static ssize_t show_board(struct device *device, struct device_attribute *attr, 2375 char *buf) 2376{ 2377 struct mlx5_ib_dev *dev = 2378 container_of(device, struct mlx5_ib_dev, ib_dev.dev); 2379 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN, 2380 dev->mdev->board_id); 2381} 2382 2383static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL); 2384static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL); 2385static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL); 2386static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL); 2387static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL); 2388 2389static struct device_attribute *mlx5_class_attributes[] = { 2390 &dev_attr_hw_rev, 2391 &dev_attr_hca_type, 2392 &dev_attr_board_id, 2393 &dev_attr_fw_pages, 2394 &dev_attr_reg_pages, 2395}; 2396 2397static void pkey_change_handler(struct work_struct *work) 2398{ 2399 struct mlx5_ib_port_resources *ports = 2400 container_of(work, struct mlx5_ib_port_resources, 2401 pkey_change_work); 2402 2403 mutex_lock(&ports->devr->mutex); 2404 mlx5_ib_gsi_pkey_change(ports->gsi); 2405 mutex_unlock(&ports->devr->mutex); 2406} 2407 2408static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev) 2409{ 2410 struct mlx5_ib_qp *mqp; 2411 struct mlx5_ib_cq *send_mcq, *recv_mcq; 2412 struct mlx5_core_cq *mcq; 2413 struct list_head cq_armed_list; 2414 unsigned long flags_qp; 2415 unsigned long flags_cq; 2416 unsigned long flags; 2417 2418 INIT_LIST_HEAD(&cq_armed_list); 2419 2420 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/ 2421 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags); 2422 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) { 2423 spin_lock_irqsave(&mqp->sq.lock, flags_qp); 2424 if (mqp->sq.tail != mqp->sq.head) { 2425 send_mcq = to_mcq(mqp->ibqp.send_cq); 2426 spin_lock_irqsave(&send_mcq->lock, flags_cq); 2427 if (send_mcq->mcq.comp && 2428 mqp->ibqp.send_cq->comp_handler) { 2429 if (!send_mcq->mcq.reset_notify_added) { 2430 send_mcq->mcq.reset_notify_added = 1; 2431 list_add_tail(&send_mcq->mcq.reset_notify, 2432 &cq_armed_list); 2433 } 2434 } 2435 spin_unlock_irqrestore(&send_mcq->lock, flags_cq); 2436 } 2437 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp); 2438 spin_lock_irqsave(&mqp->rq.lock, flags_qp); 2439 /* no handling is needed for SRQ */ 2440 if (!mqp->ibqp.srq) { 2441 if (mqp->rq.tail != mqp->rq.head) { 2442 recv_mcq = to_mcq(mqp->ibqp.recv_cq); 2443 spin_lock_irqsave(&recv_mcq->lock, flags_cq); 2444 if (recv_mcq->mcq.comp && 2445 mqp->ibqp.recv_cq->comp_handler) { 2446 if (!recv_mcq->mcq.reset_notify_added) { 2447 recv_mcq->mcq.reset_notify_added = 1; 2448 list_add_tail(&recv_mcq->mcq.reset_notify, 2449 &cq_armed_list); 2450 } 2451 } 2452 spin_unlock_irqrestore(&recv_mcq->lock, 2453 flags_cq); 2454 } 2455 } 2456 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp); 2457 } 2458 /*At that point all inflight post send were put to be executed as of we 2459 * lock/unlock above locks Now need to arm all involved CQs. 2460 */ 2461 list_for_each_entry(mcq, &cq_armed_list, reset_notify) { 2462 mcq->comp(mcq, NULL); 2463 } 2464 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags); 2465} 2466 2467static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context, 2468 enum mlx5_dev_event event, unsigned long param) 2469{ 2470 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context; 2471 struct ib_event ibev; 2472 bool fatal = false; 2473 u8 port = (u8)param; 2474 2475 switch (event) { 2476 case MLX5_DEV_EVENT_SYS_ERROR: 2477 ibev.event = IB_EVENT_DEVICE_FATAL; 2478 mlx5_ib_handle_internal_error(ibdev); 2479 fatal = true; 2480 break; 2481 2482 case MLX5_DEV_EVENT_PORT_UP: 2483 case MLX5_DEV_EVENT_PORT_DOWN: 2484 case MLX5_DEV_EVENT_PORT_INITIALIZED: 2485 /* In RoCE, port up/down events are handled in 2486 * mlx5_netdev_event(). 2487 */ 2488 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) == 2489 IB_LINK_LAYER_ETHERNET) 2490 return; 2491 2492 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ? 2493 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; 2494 break; 2495 2496 case MLX5_DEV_EVENT_LID_CHANGE: 2497 ibev.event = IB_EVENT_LID_CHANGE; 2498 break; 2499 2500 case MLX5_DEV_EVENT_PKEY_CHANGE: 2501 ibev.event = IB_EVENT_PKEY_CHANGE; 2502 2503 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work); 2504 break; 2505 2506 case MLX5_DEV_EVENT_GUID_CHANGE: 2507 ibev.event = IB_EVENT_GID_CHANGE; 2508 break; 2509 2510 case MLX5_DEV_EVENT_CLIENT_REREG: 2511 ibev.event = IB_EVENT_CLIENT_REREGISTER; 2512 break; 2513 2514 default: 2515 /* unsupported event */ 2516 return; 2517 } 2518 2519 ibev.device = &ibdev->ib_dev; 2520 ibev.element.port_num = port; 2521 2522 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) { 2523 mlx5_ib_warn(ibdev, "warning: event(%d) on port %d\n", event, port); 2524 return; 2525 } 2526 2527 if (ibdev->ib_active) 2528 ib_dispatch_event(&ibev); 2529 2530 if (fatal) 2531 ibdev->ib_active = false; 2532} 2533 2534static void get_ext_port_caps(struct mlx5_ib_dev *dev) 2535{ 2536 int port; 2537 2538 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) 2539 mlx5_query_ext_port_caps(dev, port); 2540} 2541 2542static int get_port_caps(struct mlx5_ib_dev *dev) 2543{ 2544 struct ib_device_attr *dprops = NULL; 2545 struct ib_port_attr *pprops = NULL; 2546 int err = -ENOMEM; 2547 int port; 2548 struct ib_udata uhw = {.inlen = 0, .outlen = 0}; 2549 2550 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL); 2551 if (!pprops) 2552 goto out; 2553 2554 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL); 2555 if (!dprops) 2556 goto out; 2557 2558 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw); 2559 if (err) { 2560 mlx5_ib_warn(dev, "query_device failed %d\n", err); 2561 goto out; 2562 } 2563 2564 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) { 2565 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops); 2566 if (err) { 2567 mlx5_ib_warn(dev, "query_port %d failed %d\n", 2568 port, err); 2569 break; 2570 } 2571 dev->mdev->port_caps[port - 1].pkey_table_len = 2572 dprops->max_pkeys; 2573 dev->mdev->port_caps[port - 1].gid_table_len = 2574 pprops->gid_tbl_len; 2575 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n", 2576 dprops->max_pkeys, pprops->gid_tbl_len); 2577 } 2578 2579out: 2580 kfree(pprops); 2581 kfree(dprops); 2582 2583 return err; 2584} 2585 2586static void destroy_umrc_res(struct mlx5_ib_dev *dev) 2587{ 2588 int err; 2589 2590 err = mlx5_mr_cache_cleanup(dev); 2591 if (err) 2592 mlx5_ib_warn(dev, "mr cache cleanup failed\n"); 2593 2594 mlx5_ib_destroy_qp(dev->umrc.qp); 2595 ib_free_cq(dev->umrc.cq); 2596 ib_dealloc_pd(dev->umrc.pd); 2597} 2598 2599enum { 2600 MAX_UMR_WR = 128, 2601}; 2602 2603static int create_umr_res(struct mlx5_ib_dev *dev) 2604{ 2605 struct ib_qp_init_attr *init_attr = NULL; 2606 struct ib_qp_attr *attr = NULL; 2607 struct ib_pd *pd; 2608 struct ib_cq *cq; 2609 struct ib_qp *qp; 2610 int ret; 2611 2612 attr = kzalloc(sizeof(*attr), GFP_KERNEL); 2613 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL); 2614 if (!attr || !init_attr) { 2615 ret = -ENOMEM; 2616 goto error_0; 2617 } 2618 2619 pd = ib_alloc_pd(&dev->ib_dev, 0); 2620 if (IS_ERR(pd)) { 2621 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n"); 2622 ret = PTR_ERR(pd); 2623 goto error_0; 2624 } 2625 2626 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ); 2627 if (IS_ERR(cq)) { 2628 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n"); 2629 ret = PTR_ERR(cq); 2630 goto error_2; 2631 } 2632 2633 init_attr->send_cq = cq; 2634 init_attr->recv_cq = cq; 2635 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR; 2636 init_attr->cap.max_send_wr = MAX_UMR_WR; 2637 init_attr->cap.max_send_sge = 1; 2638 init_attr->qp_type = MLX5_IB_QPT_REG_UMR; 2639 init_attr->port_num = 1; 2640 qp = mlx5_ib_create_qp(pd, init_attr, NULL); 2641 if (IS_ERR(qp)) { 2642 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n"); 2643 ret = PTR_ERR(qp); 2644 goto error_3; 2645 } 2646 qp->device = &dev->ib_dev; 2647 qp->real_qp = qp; 2648 qp->uobject = NULL; 2649 qp->qp_type = MLX5_IB_QPT_REG_UMR; 2650 2651 attr->qp_state = IB_QPS_INIT; 2652 attr->port_num = 1; 2653 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX | 2654 IB_QP_PORT, NULL); 2655 if (ret) { 2656 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n"); 2657 goto error_4; 2658 } 2659 2660 memset(attr, 0, sizeof(*attr)); 2661 attr->qp_state = IB_QPS_RTR; 2662 attr->path_mtu = IB_MTU_256; 2663 2664 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2665 if (ret) { 2666 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n"); 2667 goto error_4; 2668 } 2669 2670 memset(attr, 0, sizeof(*attr)); 2671 attr->qp_state = IB_QPS_RTS; 2672 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL); 2673 if (ret) { 2674 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n"); 2675 goto error_4; 2676 } 2677 2678 dev->umrc.qp = qp; 2679 dev->umrc.cq = cq; 2680 dev->umrc.pd = pd; 2681 2682 sema_init(&dev->umrc.sem, MAX_UMR_WR); 2683 ret = mlx5_mr_cache_init(dev); 2684 if (ret) { 2685 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret); 2686 goto error_4; 2687 } 2688 2689 kfree(attr); 2690 kfree(init_attr); 2691 2692 return 0; 2693 2694error_4: 2695 mlx5_ib_destroy_qp(qp); 2696 2697error_3: 2698 ib_free_cq(cq); 2699 2700error_2: 2701 ib_dealloc_pd(pd); 2702 2703error_0: 2704 kfree(attr); 2705 kfree(init_attr); 2706 return ret; 2707} 2708 2709static int create_dev_resources(struct mlx5_ib_resources *devr) 2710{ 2711 struct ib_srq_init_attr attr; 2712 struct mlx5_ib_dev *dev; 2713 struct ib_cq_init_attr cq_attr = {.cqe = 1}; 2714 int port; 2715 int ret = 0; 2716 2717 dev = container_of(devr, struct mlx5_ib_dev, devr); 2718 2719 mutex_init(&devr->mutex); 2720 2721 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL); 2722 if (IS_ERR(devr->p0)) { 2723 ret = PTR_ERR(devr->p0); 2724 goto error0; 2725 } 2726 devr->p0->device = &dev->ib_dev; 2727 devr->p0->uobject = NULL; 2728 atomic_set(&devr->p0->usecnt, 0); 2729 2730 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL); 2731 if (IS_ERR(devr->c0)) { 2732 ret = PTR_ERR(devr->c0); 2733 goto error1; 2734 } 2735 devr->c0->device = &dev->ib_dev; 2736 devr->c0->uobject = NULL; 2737 devr->c0->comp_handler = NULL; 2738 devr->c0->event_handler = NULL; 2739 devr->c0->cq_context = NULL; 2740 atomic_set(&devr->c0->usecnt, 0); 2741 2742 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2743 if (IS_ERR(devr->x0)) { 2744 ret = PTR_ERR(devr->x0); 2745 goto error2; 2746 } 2747 devr->x0->device = &dev->ib_dev; 2748 devr->x0->inode = NULL; 2749 atomic_set(&devr->x0->usecnt, 0); 2750 mutex_init(&devr->x0->tgt_qp_mutex); 2751 INIT_LIST_HEAD(&devr->x0->tgt_qp_list); 2752 2753 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL); 2754 if (IS_ERR(devr->x1)) { 2755 ret = PTR_ERR(devr->x1); 2756 goto error3; 2757 } 2758 devr->x1->device = &dev->ib_dev; 2759 devr->x1->inode = NULL; 2760 atomic_set(&devr->x1->usecnt, 0); 2761 mutex_init(&devr->x1->tgt_qp_mutex); 2762 INIT_LIST_HEAD(&devr->x1->tgt_qp_list); 2763 2764 memset(&attr, 0, sizeof(attr)); 2765 attr.attr.max_sge = 1; 2766 attr.attr.max_wr = 1; 2767 attr.srq_type = IB_SRQT_XRC; 2768 attr.ext.xrc.cq = devr->c0; 2769 attr.ext.xrc.xrcd = devr->x0; 2770 2771 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2772 if (IS_ERR(devr->s0)) { 2773 ret = PTR_ERR(devr->s0); 2774 goto error4; 2775 } 2776 devr->s0->device = &dev->ib_dev; 2777 devr->s0->pd = devr->p0; 2778 devr->s0->uobject = NULL; 2779 devr->s0->event_handler = NULL; 2780 devr->s0->srq_context = NULL; 2781 devr->s0->srq_type = IB_SRQT_XRC; 2782 devr->s0->ext.xrc.xrcd = devr->x0; 2783 devr->s0->ext.xrc.cq = devr->c0; 2784 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt); 2785 atomic_inc(&devr->s0->ext.xrc.cq->usecnt); 2786 atomic_inc(&devr->p0->usecnt); 2787 atomic_set(&devr->s0->usecnt, 0); 2788 2789 memset(&attr, 0, sizeof(attr)); 2790 attr.attr.max_sge = 1; 2791 attr.attr.max_wr = 1; 2792 attr.srq_type = IB_SRQT_BASIC; 2793 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL); 2794 if (IS_ERR(devr->s1)) { 2795 ret = PTR_ERR(devr->s1); 2796 goto error5; 2797 } 2798 devr->s1->device = &dev->ib_dev; 2799 devr->s1->pd = devr->p0; 2800 devr->s1->uobject = NULL; 2801 devr->s1->event_handler = NULL; 2802 devr->s1->srq_context = NULL; 2803 devr->s1->srq_type = IB_SRQT_BASIC; 2804 devr->s1->ext.xrc.cq = devr->c0; 2805 atomic_inc(&devr->p0->usecnt); 2806 atomic_set(&devr->s0->usecnt, 0); 2807 2808 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) { 2809 INIT_WORK(&devr->ports[port].pkey_change_work, 2810 pkey_change_handler); 2811 devr->ports[port].devr = devr; 2812 } 2813 2814 return 0; 2815 2816error5: 2817 mlx5_ib_destroy_srq(devr->s0); 2818error4: 2819 mlx5_ib_dealloc_xrcd(devr->x1); 2820error3: 2821 mlx5_ib_dealloc_xrcd(devr->x0); 2822error2: 2823 mlx5_ib_destroy_cq(devr->c0); 2824error1: 2825 mlx5_ib_dealloc_pd(devr->p0); 2826error0: 2827 return ret; 2828} 2829 2830static void destroy_dev_resources(struct mlx5_ib_resources *devr) 2831{ 2832 struct mlx5_ib_dev *dev = 2833 container_of(devr, struct mlx5_ib_dev, devr); 2834 int port; 2835 2836 mlx5_ib_destroy_srq(devr->s1); 2837 mlx5_ib_destroy_srq(devr->s0); 2838 mlx5_ib_dealloc_xrcd(devr->x0); 2839 mlx5_ib_dealloc_xrcd(devr->x1); 2840 mlx5_ib_destroy_cq(devr->c0); 2841 mlx5_ib_dealloc_pd(devr->p0); 2842 2843 /* Make sure no change P_Key work items are still executing */ 2844 for (port = 0; port < dev->num_ports; ++port) 2845 cancel_work_sync(&devr->ports[port].pkey_change_work); 2846} 2847 2848static u32 get_core_cap_flags(struct ib_device *ibdev) 2849{ 2850 struct mlx5_ib_dev *dev = to_mdev(ibdev); 2851 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1); 2852 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type); 2853 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version); 2854 u32 ret = 0; 2855 2856 if (ll == IB_LINK_LAYER_INFINIBAND) 2857 return RDMA_CORE_PORT_IBA_IB; 2858 2859 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP)) 2860 return 0; 2861 2862 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP)) 2863 return 0; 2864 2865 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP) 2866 ret |= RDMA_CORE_PORT_IBA_ROCE; 2867 2868 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP) 2869 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; 2870 2871 return ret; 2872} 2873 2874static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num, 2875 struct ib_port_immutable *immutable) 2876{ 2877 struct ib_port_attr attr; 2878 int err; 2879 2880 err = mlx5_ib_query_port(ibdev, port_num, &attr); 2881 if (err) 2882 return err; 2883 2884 immutable->pkey_tbl_len = attr.pkey_tbl_len; 2885 immutable->gid_tbl_len = attr.gid_tbl_len; 2886 immutable->core_cap_flags = get_core_cap_flags(ibdev); 2887 immutable->max_mad_size = IB_MGMT_MAD_SIZE; 2888 2889 return 0; 2890} 2891 2892static void get_dev_fw_str(struct ib_device *ibdev, char *str, 2893 size_t str_len) 2894{ 2895 struct mlx5_ib_dev *dev = 2896 container_of(ibdev, struct mlx5_ib_dev, ib_dev); 2897 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev), 2898 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev)); 2899} 2900 2901static int mlx5_roce_lag_init(struct mlx5_ib_dev *dev) 2902{ 2903 return 0; 2904} 2905 2906static void mlx5_roce_lag_cleanup(struct mlx5_ib_dev *dev) 2907{ 2908} 2909 2910static void mlx5_remove_roce_notifier(struct mlx5_ib_dev *dev) 2911{ 2912 if (dev->roce.nb.notifier_call) { 2913 unregister_netdevice_notifier(&dev->roce.nb); 2914 dev->roce.nb.notifier_call = NULL; 2915 } 2916} 2917 2918static int mlx5_enable_roce(struct mlx5_ib_dev *dev) 2919{ 2920 VNET_ITERATOR_DECL(vnet_iter); 2921 struct net_device *idev; 2922 int err; 2923 2924 /* Check if mlx5en net device already exists */ 2925 VNET_LIST_RLOCK(); 2926 VNET_FOREACH(vnet_iter) { 2927 IFNET_RLOCK(); 2928 CURVNET_SET_QUIET(vnet_iter); 2929 CK_STAILQ_FOREACH(idev, &V_ifnet, if_link) { 2930 /* check if network interface belongs to mlx5en */ 2931 if (!mlx5_netdev_match(idev, dev->mdev, "mce")) 2932 continue; 2933 write_lock(&dev->roce.netdev_lock); 2934 dev->roce.netdev = idev; 2935 write_unlock(&dev->roce.netdev_lock); 2936 } 2937 CURVNET_RESTORE(); 2938 IFNET_RUNLOCK(); 2939 } 2940 VNET_LIST_RUNLOCK(); 2941 2942 dev->roce.nb.notifier_call = mlx5_netdev_event; 2943 err = register_netdevice_notifier(&dev->roce.nb); 2944 if (err) { 2945 dev->roce.nb.notifier_call = NULL; 2946 return err; 2947 } 2948 2949 err = mlx5_nic_vport_enable_roce(dev->mdev); 2950 if (err) 2951 goto err_unregister_netdevice_notifier; 2952 2953 err = mlx5_roce_lag_init(dev); 2954 if (err) 2955 goto err_disable_roce; 2956 2957 return 0; 2958 2959err_disable_roce: 2960 mlx5_nic_vport_disable_roce(dev->mdev); 2961 2962err_unregister_netdevice_notifier: 2963 mlx5_remove_roce_notifier(dev); 2964 return err; 2965} 2966 2967static void mlx5_disable_roce(struct mlx5_ib_dev *dev) 2968{ 2969 mlx5_roce_lag_cleanup(dev); 2970 mlx5_nic_vport_disable_roce(dev->mdev); 2971} 2972 2973static void mlx5_ib_dealloc_q_port_counter(struct mlx5_ib_dev *dev, u8 port_num) 2974{ 2975 mlx5_vport_dealloc_q_counter(dev->mdev, 2976 MLX5_INTERFACE_PROTOCOL_IB, 2977 dev->port[port_num].q_cnt_id); 2978 dev->port[port_num].q_cnt_id = 0; 2979} 2980 2981static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev *dev) 2982{ 2983 unsigned int i; 2984 2985 for (i = 0; i < dev->num_ports; i++) 2986 mlx5_ib_dealloc_q_port_counter(dev, i); 2987} 2988 2989static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev *dev) 2990{ 2991 int i; 2992 int ret; 2993 2994 for (i = 0; i < dev->num_ports; i++) { 2995 ret = mlx5_vport_alloc_q_counter(dev->mdev, 2996 MLX5_INTERFACE_PROTOCOL_IB, 2997 &dev->port[i].q_cnt_id); 2998 if (ret) { 2999 mlx5_ib_warn(dev, 3000 "couldn't allocate queue counter for port %d, err %d\n", 3001 i + 1, ret); 3002 goto dealloc_counters; 3003 } 3004 } 3005 3006 return 0; 3007 3008dealloc_counters: 3009 while (--i >= 0) 3010 mlx5_ib_dealloc_q_port_counter(dev, i); 3011 3012 return ret; 3013} 3014 3015static const char * const names[] = { 3016 "rx_write_requests", 3017 "rx_read_requests", 3018 "rx_atomic_requests", 3019 "out_of_buffer", 3020 "out_of_sequence", 3021 "duplicate_request", 3022 "rnr_nak_retry_err", 3023 "packet_seq_err", 3024 "implied_nak_seq_err", 3025 "local_ack_timeout_err", 3026}; 3027 3028static const size_t stats_offsets[] = { 3029 MLX5_BYTE_OFF(query_q_counter_out, rx_write_requests), 3030 MLX5_BYTE_OFF(query_q_counter_out, rx_read_requests), 3031 MLX5_BYTE_OFF(query_q_counter_out, rx_atomic_requests), 3032 MLX5_BYTE_OFF(query_q_counter_out, out_of_buffer), 3033 MLX5_BYTE_OFF(query_q_counter_out, out_of_sequence), 3034 MLX5_BYTE_OFF(query_q_counter_out, duplicate_request), 3035 MLX5_BYTE_OFF(query_q_counter_out, rnr_nak_retry_err), 3036 MLX5_BYTE_OFF(query_q_counter_out, packet_seq_err), 3037 MLX5_BYTE_OFF(query_q_counter_out, implied_nak_seq_err), 3038 MLX5_BYTE_OFF(query_q_counter_out, local_ack_timeout_err), 3039}; 3040 3041static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev, 3042 u8 port_num) 3043{ 3044 BUILD_BUG_ON(ARRAY_SIZE(names) != ARRAY_SIZE(stats_offsets)); 3045 3046 /* We support only per port stats */ 3047 if (port_num == 0) 3048 return NULL; 3049 3050 return rdma_alloc_hw_stats_struct(names, ARRAY_SIZE(names), 3051 RDMA_HW_STATS_DEFAULT_LIFESPAN); 3052} 3053 3054static int mlx5_ib_get_hw_stats(struct ib_device *ibdev, 3055 struct rdma_hw_stats *stats, 3056 u8 port, int index) 3057{ 3058 struct mlx5_ib_dev *dev = to_mdev(ibdev); 3059 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out); 3060 void *out; 3061 __be32 val; 3062 int ret; 3063 int i; 3064 3065 if (!port || !stats) 3066 return -ENOSYS; 3067 3068 out = mlx5_vzalloc(outlen); 3069 if (!out) 3070 return -ENOMEM; 3071 3072 ret = mlx5_vport_query_q_counter(dev->mdev, 3073 dev->port[port - 1].q_cnt_id, 0, 3074 out, outlen); 3075 if (ret) 3076 goto free; 3077 3078 for (i = 0; i < ARRAY_SIZE(names); i++) { 3079 val = *(__be32 *)(out + stats_offsets[i]); 3080 stats->value[i] = (u64)be32_to_cpu(val); 3081 } 3082free: 3083 kvfree(out); 3084 return ARRAY_SIZE(names); 3085} 3086 3087static void *mlx5_ib_add(struct mlx5_core_dev *mdev) 3088{ 3089 struct mlx5_ib_dev *dev; 3090 enum rdma_link_layer ll; 3091 int port_type_cap; 3092 int err; 3093 int i; 3094 3095 port_type_cap = MLX5_CAP_GEN(mdev, port_type); 3096 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap); 3097 3098 if ((ll == IB_LINK_LAYER_ETHERNET) && !MLX5_CAP_GEN(mdev, roce)) 3099 return NULL; 3100 3101 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev)); 3102 if (!dev) 3103 return NULL; 3104 3105 dev->mdev = mdev; 3106 3107 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port), 3108 GFP_KERNEL); 3109 if (!dev->port) 3110 goto err_dealloc; 3111 3112 rwlock_init(&dev->roce.netdev_lock); 3113 err = get_port_caps(dev); 3114 if (err) 3115 goto err_free_port; 3116 3117 if (mlx5_use_mad_ifc(dev)) 3118 get_ext_port_caps(dev); 3119 3120 MLX5_INIT_DOORBELL_LOCK(&dev->uar_lock); 3121 3122 snprintf(dev->ib_dev.name, IB_DEVICE_NAME_MAX, "mlx5_%d", device_get_unit(mdev->pdev->dev.bsddev)); 3123 dev->ib_dev.owner = THIS_MODULE; 3124 dev->ib_dev.node_type = RDMA_NODE_IB_CA; 3125 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */; 3126 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports); 3127 dev->ib_dev.phys_port_cnt = dev->num_ports; 3128 dev->ib_dev.num_comp_vectors = 3129 dev->mdev->priv.eq_table.num_comp_vectors; 3130 dev->ib_dev.dma_device = &mdev->pdev->dev; 3131 3132 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION; 3133 dev->ib_dev.uverbs_cmd_mask = 3134 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | 3135 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | 3136 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | 3137 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | 3138 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | 3139 (1ull << IB_USER_VERBS_CMD_CREATE_AH) | 3140 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) | 3141 (1ull << IB_USER_VERBS_CMD_REG_MR) | 3142 (1ull << IB_USER_VERBS_CMD_REREG_MR) | 3143 (1ull << IB_USER_VERBS_CMD_DEREG_MR) | 3144 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | 3145 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | 3146 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | 3147 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | 3148 (1ull << IB_USER_VERBS_CMD_CREATE_QP) | 3149 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | 3150 (1ull << IB_USER_VERBS_CMD_QUERY_QP) | 3151 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) | 3152 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) | 3153 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) | 3154 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) | 3155 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) | 3156 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) | 3157 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) | 3158 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) | 3159 (1ull << IB_USER_VERBS_CMD_OPEN_QP); 3160 dev->ib_dev.uverbs_ex_cmd_mask = 3161 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) | 3162 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) | 3163 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP); 3164 3165 dev->ib_dev.query_device = mlx5_ib_query_device; 3166 dev->ib_dev.query_port = mlx5_ib_query_port; 3167 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer; 3168 if (ll == IB_LINK_LAYER_ETHERNET) 3169 dev->ib_dev.get_netdev = mlx5_ib_get_netdev; 3170 dev->ib_dev.query_gid = mlx5_ib_query_gid; 3171 dev->ib_dev.add_gid = mlx5_ib_add_gid; 3172 dev->ib_dev.del_gid = mlx5_ib_del_gid; 3173 dev->ib_dev.query_pkey = mlx5_ib_query_pkey; 3174 dev->ib_dev.modify_device = mlx5_ib_modify_device; 3175 dev->ib_dev.modify_port = mlx5_ib_modify_port; 3176 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext; 3177 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext; 3178 dev->ib_dev.mmap = mlx5_ib_mmap; 3179 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd; 3180 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd; 3181 dev->ib_dev.create_ah = mlx5_ib_create_ah; 3182 dev->ib_dev.query_ah = mlx5_ib_query_ah; 3183 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah; 3184 dev->ib_dev.create_srq = mlx5_ib_create_srq; 3185 dev->ib_dev.modify_srq = mlx5_ib_modify_srq; 3186 dev->ib_dev.query_srq = mlx5_ib_query_srq; 3187 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq; 3188 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv; 3189 dev->ib_dev.create_qp = mlx5_ib_create_qp; 3190 dev->ib_dev.modify_qp = mlx5_ib_modify_qp; 3191 dev->ib_dev.query_qp = mlx5_ib_query_qp; 3192 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp; 3193 dev->ib_dev.post_send = mlx5_ib_post_send; 3194 dev->ib_dev.post_recv = mlx5_ib_post_recv; 3195 dev->ib_dev.create_cq = mlx5_ib_create_cq; 3196 dev->ib_dev.modify_cq = mlx5_ib_modify_cq; 3197 dev->ib_dev.resize_cq = mlx5_ib_resize_cq; 3198 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq; 3199 dev->ib_dev.poll_cq = mlx5_ib_poll_cq; 3200 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq; 3201 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr; 3202 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr; 3203 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr; 3204 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr; 3205 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach; 3206 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach; 3207 dev->ib_dev.process_mad = mlx5_ib_process_mad; 3208 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr; 3209 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg; 3210 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status; 3211 dev->ib_dev.get_port_immutable = mlx5_port_immutable; 3212 dev->ib_dev.get_dev_fw_str = get_dev_fw_str; 3213 if (mlx5_core_is_pf(mdev)) { 3214 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config; 3215 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state; 3216 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats; 3217 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid; 3218 } 3219 3220 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext; 3221 3222 mlx5_ib_internal_fill_odp_caps(dev); 3223 3224 if (MLX5_CAP_GEN(mdev, imaicl)) { 3225 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw; 3226 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw; 3227 dev->ib_dev.uverbs_cmd_mask |= 3228 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) | 3229 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW); 3230 } 3231 3232 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt) && 3233 MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) { 3234 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats; 3235 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats; 3236 } 3237 3238 if (MLX5_CAP_GEN(mdev, xrc)) { 3239 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd; 3240 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd; 3241 dev->ib_dev.uverbs_cmd_mask |= 3242 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) | 3243 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD); 3244 } 3245 3246 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) == 3247 IB_LINK_LAYER_ETHERNET) { 3248 dev->ib_dev.create_flow = mlx5_ib_create_flow; 3249 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow; 3250 dev->ib_dev.create_wq = mlx5_ib_create_wq; 3251 dev->ib_dev.modify_wq = mlx5_ib_modify_wq; 3252 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq; 3253 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table; 3254 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table; 3255 dev->ib_dev.uverbs_ex_cmd_mask |= 3256 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) | 3257 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) | 3258 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) | 3259 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) | 3260 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) | 3261 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) | 3262 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL); 3263 } 3264 err = init_node_data(dev); 3265 if (err) 3266 goto err_free_port; 3267 3268 mutex_init(&dev->flow_db.lock); 3269 mutex_init(&dev->cap_mask_mutex); 3270 INIT_LIST_HEAD(&dev->qp_list); 3271 spin_lock_init(&dev->reset_flow_resource_lock); 3272 3273 if (ll == IB_LINK_LAYER_ETHERNET) { 3274 err = mlx5_enable_roce(dev); 3275 if (err) 3276 goto err_free_port; 3277 } 3278 3279 err = create_dev_resources(&dev->devr); 3280 if (err) 3281 goto err_disable_roce; 3282 3283 err = mlx5_ib_odp_init_one(dev); 3284 if (err) 3285 goto err_rsrc; 3286 3287 err = mlx5_ib_alloc_q_counters(dev); 3288 if (err) 3289 goto err_odp; 3290 3291 err = ib_register_device(&dev->ib_dev, NULL); 3292 if (err) 3293 goto err_q_cnt; 3294 3295 err = create_umr_res(dev); 3296 if (err) 3297 goto err_dev; 3298 3299 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) { 3300 err = device_create_file(&dev->ib_dev.dev, 3301 mlx5_class_attributes[i]); 3302 if (err) 3303 goto err_umrc; 3304 } 3305 3306 err = mlx5_ib_init_congestion(dev); 3307 if (err) 3308 goto err_umrc; 3309 3310 dev->ib_active = true; 3311 3312 return dev; 3313 3314err_umrc: 3315 destroy_umrc_res(dev); 3316 3317err_dev: 3318 ib_unregister_device(&dev->ib_dev); 3319 3320err_q_cnt: 3321 mlx5_ib_dealloc_q_counters(dev); 3322 3323err_odp: 3324 mlx5_ib_odp_remove_one(dev); 3325 3326err_rsrc: 3327 destroy_dev_resources(&dev->devr); 3328 3329err_disable_roce: 3330 if (ll == IB_LINK_LAYER_ETHERNET) { 3331 mlx5_disable_roce(dev); 3332 mlx5_remove_roce_notifier(dev); 3333 } 3334 3335err_free_port: 3336 kfree(dev->port); 3337 3338err_dealloc: 3339 ib_dealloc_device((struct ib_device *)dev); 3340 3341 return NULL; 3342} 3343 3344static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context) 3345{ 3346 struct mlx5_ib_dev *dev = context; 3347 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1); 3348 3349 mlx5_ib_cleanup_congestion(dev); 3350 mlx5_remove_roce_notifier(dev); 3351 ib_unregister_device(&dev->ib_dev); 3352 mlx5_ib_dealloc_q_counters(dev); 3353 destroy_umrc_res(dev); 3354 mlx5_ib_odp_remove_one(dev); 3355 destroy_dev_resources(&dev->devr); 3356 if (ll == IB_LINK_LAYER_ETHERNET) 3357 mlx5_disable_roce(dev); 3358 kfree(dev->port); 3359 ib_dealloc_device(&dev->ib_dev); 3360} 3361 3362static struct mlx5_interface mlx5_ib_interface = { 3363 .add = mlx5_ib_add, 3364 .remove = mlx5_ib_remove, 3365 .event = mlx5_ib_event, 3366 .protocol = MLX5_INTERFACE_PROTOCOL_IB, 3367}; 3368 3369static int __init mlx5_ib_init(void) 3370{ 3371 int err; 3372 3373 err = mlx5_ib_odp_init(); 3374 if (err) 3375 return err; 3376 3377 err = mlx5_register_interface(&mlx5_ib_interface); 3378 if (err) 3379 goto clean_odp; 3380 3381 return err; 3382 3383clean_odp: 3384 mlx5_ib_odp_cleanup(); 3385 return err; 3386} 3387 3388static void __exit mlx5_ib_cleanup(void) 3389{ 3390 mlx5_unregister_interface(&mlx5_ib_interface); 3391 mlx5_ib_odp_cleanup(); 3392} 3393 3394static void 3395mlx5_ib_show_version(void __unused *arg) 3396{ 3397 3398 printf("%s", mlx5_version); 3399} 3400SYSINIT(mlx5_ib_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5_ib_show_version, NULL); 3401 3402module_init_order(mlx5_ib_init, SI_ORDER_SEVENTH); 3403module_exit_order(mlx5_ib_cleanup, SI_ORDER_SEVENTH); 3404