1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Authors: Ravi Pokala (rpokala@freebsd.org) 5 * 6 * Copyright (c) 2018 Panasas 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32#ifndef _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ 33#define _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ 34 35/* JEDEC DIMMs include one or more SMBus devices. 36 * 37 * At a minimum, they have an EEPROM containing either 256 bytes (DDR3) or 512 38 * bytes (DDR4) of "Serial Presence Detect" (SPD) information. The SPD contains 39 * data used by the memory controller to configure itself, and it also includes 40 * asset information. The layout of SPD data is defined in: 41 * 42 * JEDEC Standard 21-C, Annex K (DDR3) 43 * JEDEC Standard 21-C, Annex L (DDR4) 44 * 45 * DIMMs may also include a "Thermal Sensor on DIMM" (TSOD), which reports 46 * temperature data. While not strictly required, the TSOD is so often included 47 * that JEDEC defined standards for single chips which include both SPD and TSOD 48 * functions. They respond on multiple SMBus addresses, depending on the 49 * function. 50 * 51 * JEDEC Standard 21-C, TSE2002av (DDR3) 52 * JEDEC Standard 21-C, TSE2004av (DDR4) 53 */ 54 55/* TSE2004av defines several Device Type Identifiers (DTIs), which are the high 56 * nybble of the SMBus address. Addresses with DTIs of PROTECT (or PAGE, which 57 * has the same value) are essentially "broadcast" addresses; all SPD devices 58 * respond to them, changing their mode based on the Logical Serial Address 59 * (LSA) encoded in bits [3:1]. For normal SPD access, bits [3:1] encode the 60 * DIMM slot number. 61 */ 62#define JEDEC_SPD_PAGE_SIZE 256 63#define JEDEC_DTI_SPD 0xa0 64#define JEDEC_DTI_TSOD 0x30 65#define JEDEC_DTI_PROTECT 0x60 66#define JEDEC_LSA_PROTECT_SET0 0x02 67#define JEDEC_LSA_PROTECT_SET1 0x08 68#define JEDEC_LSA_PROTECT_SET2 0x0a 69#define JEDEC_LSA_PROTECT_SET3 0x00 70#define JEDEC_LSA_PROTECT_CLR 0x06 71#define JEDEC_LSA_PROTECT_GET0 0x03 72#define JEDEC_LSA_PROTECT_GET1 0x09 73#define JEDEC_LSA_PROTECT_GET2 0x0b 74#define JEDEC_LSA_PROTECT_GET3 0x01 75#define JEDEC_DTI_PAGE 0x60 76#define JEDEC_LSA_PAGE_SET0 0x0c 77#define JEDEC_LSA_PAGE_SET1 0x0e 78#define JEDEC_LSA_PAGE_GET 0x0d 79 80/* The offsets and lengths of various SPD bytes are defined in Annex K (DDR3) 81 * and Annex L (DDR4). Conveniently, the DRAM type is at the same offset for 82 * both versions. 83 * 84 * This list only includes information needed to get the asset information and 85 * calculate the DIMM capacity. 86 */ 87#define SPD_OFFSET_DRAM_TYPE 2 88#define SPD_OFFSET_DDR3_SDRAM_CAPACITY 4 89#define SPD_OFFSET_DDR3_DIMM_RANKS 7 90#define SPD_OFFSET_DDR3_SDRAM_WIDTH 7 91#define SPD_OFFSET_DDR3_BUS_WIDTH 8 92#define SPD_OFFSET_DDR3_TSOD_PRESENT 32 93#define SPD_OFFSET_DDR3_SERIAL 122 94#define SPD_LEN_DDR3_SERIAL 4 95#define SPD_OFFSET_DDR3_PARTNUM 128 96#define SPD_LEN_DDR3_PARTNUM 18 97#define SPD_OFFSET_DDR4_SDRAM_CAPACITY 4 98#define SPD_OFFSET_DDR4_SDRAM_PKG_TYPE 6 99#define SPD_OFFSET_DDR4_DIMM_RANKS 12 100#define SPD_OFFSET_DDR4_SDRAM_WIDTH 12 101#define SPD_OFFSET_DDR4_BUS_WIDTH 13 102#define SPD_OFFSET_DDR4_TSOD_PRESENT 14 103#define SPD_OFFSET_DDR4_SERIAL 325 104#define SPD_LEN_DDR4_SERIAL 4 105#define SPD_OFFSET_DDR4_PARTNUM 329 106#define SPD_LEN_DDR4_PARTNUM 20 107 108/* The "DRAM Type" field of the SPD enumerates various memory technologies which 109 * have been used over the years. The list is append-only, so we need only refer 110 * to the latest SPD specification. In this case, Annex L for DDR4. 111 */ 112enum dram_type { 113 DRAM_TYPE_RESERVED = 0x00, 114 DRAM_TYPE_FAST_PAGE_MODE = 0x01, 115 DRAM_TYPE_EDO = 0x02, 116 DRAM_TYPE_PIPLEINED_NYBBLE = 0x03, 117 DRAM_TYPE_SDRAM = 0x04, 118 DRAM_TYPE_ROM = 0x05, 119 DRAM_TYPE_DDR_SGRAM = 0x06, 120 DRAM_TYPE_DDR_SDRAM = 0x07, 121 DRAM_TYPE_DDR2_SDRAM = 0x08, 122 DRAM_TYPE_DDR2_SDRAM_FBDIMM = 0x09, 123 DRAM_TYPE_DDR2_SDRAM_FBDIMM_PROBE = 0x0a, 124 DRAM_TYPE_DDR3_SDRAM = 0x0b, 125 DRAM_TYPE_DDR4_SDRAM = 0x0c, 126 DRAM_TYPE_RESERVED_0D = 0x0d, 127 DRAM_TYPE_DDR4E_SDRAM = 0x0e, 128 DRAM_TYPE_LPDDR3_SDRAM = 0x0f, 129 DRAM_TYPE_LPDDR4_SDRAM = 0x10, 130}; 131 132/* The TSOD is accessed using a simple word interface, which is identical 133 * between TSE2002av (DDR3) and TSE2004av (DDR4). 134 */ 135#define TSOD_REG_CAPABILITES 0 136#define TSOD_REG_CONFIG 1 137#define TSOD_REG_LIM_HIGH 2 138#define TSOD_REG_LIM_LOW 3 139#define TSOD_REG_LIM_CRIT 4 140#define TSOD_REG_TEMPERATURE 5 141#define TSOD_REG_MANUFACTURER 6 142#define TSOD_REG_DEV_REV 7 143 144#endif /* _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ */ 145 146/* vi: set ts=8 sw=4 sts=8 noet: */ 147