1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Authors: Joe Kloss; Ravi Pokala (rpokala@freebsd.org)
5 *
6 * Copyright (c) 2017-2018 Panasas
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 *    notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 *    notice, this list of conditions and the following disclaimer in the
15 *    documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32#ifndef _DEV__IMCSMB__IMCSMB_REG_H_
33#define _DEV__IMCSMB__IMCSMB_REG_H_
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/endian.h>
40#include <sys/errno.h>
41#include <sys/lock.h>
42#include <sys/mutex.h>
43#include <sys/syslog.h>
44#include <sys/bus.h>
45
46#include <machine/bus.h>
47#include <machine/atomic.h>
48
49#include <dev/pci/pcivar.h>
50#include <dev/pci/pcireg.h>
51
52#include <dev/smbus/smbconf.h>
53
54/* Intel (Sandy,Ivy)bridge and (Has,Broad)well CPUs have integrated memory
55 * controllers (iMCs), each of which having up to two SMBus controllers. They
56 * are programmed via sets of registers in the same PCI device, which are
57 * identical other than the register numbers.
58 *
59 * The full documentation for these registers can be found in volume two of the
60 * datasheets for the CPUs. Refer to the links in imcsmb_pci.c
61 */
62
63#define	IMCSMB_REG_STATUS0			0x0180
64#define	IMCSMB_REG_STATUS1			0x0190
65#define		IMCSMB_STATUS_BUSY_BIT		0x10000000
66#define		IMCSMB_STATUS_BUS_ERROR_BIT	0x20000000
67#define		IMCSMB_STATUS_WRITE_DATA_DONE	0x40000000
68#define		IMCSMB_STATUS_READ_DATA_VALID	0x80000000
69
70#define	IMCSMB_REG_COMMAND0			0x0184
71#define	IMCSMB_REG_COMMAND1			0x0194
72#define		IMCSMB_CMD_WORD_ACCESS		0x20000000
73#define		IMCSMB_CMD_WRITE_BIT		0x08000000
74#define		IMCSMB_CMD_TRIGGER_BIT		0x80000000
75
76#define	IMCSMB_REG_CONTROL0			0x0188
77#define	IMCSMB_REG_CONTROL1			0x0198
78#define		IMCSMB_CNTL_POLL_EN		0x00000100
79#define		IMCSMB_CNTL_CLK_OVERRIDE	0x08000000
80#define		IMCSMB_CNTL_DTI_MASK		0xf0000000
81#define		IMCSMB_CNTL_WRITE_DISABLE_BIT	0x04000000
82
83#endif /* _DEV__IMCSMB__IMCSMB_REG_H_ */
84
85/* vi: set ts=8 sw=4 sts=8 noet: */
86