1/* 2 * Copyright (c) 2014 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Matthew Dillon <dillon@backplane.com> and was subsequently ported 6 * to FreeBSD by Michael Gmelin <freebsd@grem.de> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in 16 * the documentation and/or other materials provided with the 17 * distribution. 18 * 3. Neither the name of The DragonFly Project nor the names of its 19 * contributors may be used to endorse or promote products derived 20 * from this software without specific, prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 23 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 24 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 25 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 26 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 28 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 29 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 30 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 31 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 32 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 33 * SUCH DAMAGE. 34 * 35 * $FreeBSD$ 36 */ 37/* 38 * Intel fourth generation mobile cpus integrated I2C device. 39 * 40 * Datasheet reference: Section 22. 41 * 42 * http://www.intel.com/content/www/us/en/processors/core/4th-gen-core-family-mobile-i-o-datasheet.html?wapkw=datasheets+4th+generation 43 * 44 * This is a from-scratch driver under the BSD license using the Intel data 45 * sheet and the linux driver for reference. All code is freshly written 46 * without referencing the linux driver code. However, during testing 47 * I am also using the linux driver code as a reference to help resolve any 48 * issues that come. These will be specifically documented in the code. 49 * 50 * This controller is an I2C master only and cannot act as a slave. The IO 51 * voltage should be set by the BIOS. Standard (100Kb/s) and Fast (400Kb/s) 52 * and fast mode plus (1MB/s) is supported. High speed mode (3.4 MB/s) is NOT 53 * supported. 54 */ 55 56#ifndef _ICHIIC_IG4_REG_H_ 57#define _ICHIIC_IG4_REG_H_ 58 59/* 60 * 22.2 MMIO registers can be accessed through BAR0 in PCI mode or through 61 * BAR1 when in ACPI mode. 62 * 63 * Register width is 32-bits 64 * 65 * 22.2 Default Values on device reset are 0 except as specified here: 66 * TAR_ADD 0x00000055 67 * SS_SCL_HCNT 0x00000264 68 * SS_SCL_LCNT 0x000002C2 69 * FS_SCL_HCNT 0x0000006E 70 * FS_SCL_LCNT 0x000000CF 71 * INTR_MASK 0x000008FF 72 * I2C_STA 0x00000006 73 * SDA_HOLD 0x00000001 74 * SDA_SETUP 0x00000064 75 * COMP_PARAM1 0x00FFFF6E 76 */ 77 78#define IG4_REG_CTL 0x0000 /* RW Control Register */ 79#define IG4_REG_TAR_ADD 0x0004 /* RW Target Address */ 80#define IG4_REG_HS_MADDR 0x000C /* RW High Speed Master Mode Code Address*/ 81#define IG4_REG_DATA_CMD 0x0010 /* RW Data Buffer and Command */ 82#define IG4_REG_SS_SCL_HCNT 0x0014 /* RW Std Speed clock High Count */ 83#define IG4_REG_SS_SCL_LCNT 0x0018 /* RW Std Speed clock Low Count */ 84#define IG4_REG_FS_SCL_HCNT 0x001C /* RW Fast Speed clock High Count */ 85#define IG4_REG_FS_SCL_LCNT 0x0020 /* RW Fast Speed clock Low Count */ 86#define IG4_REG_INTR_STAT 0x002C /* RO Interrupt Status */ 87#define IG4_REG_INTR_MASK 0x0030 /* RW Interrupt Mask */ 88#define IG4_REG_RAW_INTR_STAT 0x0034 /* RO Raw Interrupt Status */ 89#define IG4_REG_RX_TL 0x0038 /* RW Receive FIFO Threshold */ 90#define IG4_REG_TX_TL 0x003C /* RW Transmit FIFO Threshold */ 91#define IG4_REG_CLR_INTR 0x0040 /* RO Clear Interrupt */ 92#define IG4_REG_CLR_RX_UNDER 0x0044 /* RO Clear RX_Under Interrupt */ 93#define IG4_REG_CLR_RX_OVER 0x0048 /* RO Clear RX_Over Interrupt */ 94#define IG4_REG_CLR_TX_OVER 0x004C /* RO Clear TX_Over Interrupt */ 95#define IG4_REG_CLR_RD_REQ 0x0050 /* RO Clear RD_Req Interrupt */ 96#define IG4_REG_CLR_TX_ABORT 0x0054 /* RO Clear TX_Abort Interrupt */ 97#define IG4_REG_CLR_RX_DONE 0x0058 /* RO Clear RX_Done Interrupt */ 98#define IG4_REG_CLR_ACTIVITY 0x005C /* RO Clear Activity Interrupt */ 99#define IG4_REG_CLR_STOP_DET 0x0060 /* RO Clear STOP Detection Int */ 100#define IG4_REG_CLR_START_DET 0x0064 /* RO Clear START Detection Int */ 101#define IG4_REG_CLR_GEN_CALL 0x0068 /* RO Clear General Call Interrupt */ 102#define IG4_REG_I2C_EN 0x006C /* RW I2C Enable */ 103#define IG4_REG_I2C_STA 0x0070 /* RO I2C Status */ 104#define IG4_REG_TXFLR 0x0074 /* RO Transmit FIFO Level */ 105#define IG4_REG_RXFLR 0x0078 /* RO Receive FIFO Level */ 106#define IG4_REG_SDA_HOLD 0x007C /* RW SDA Hold Time Length */ 107#define IG4_REG_TX_ABRT_SOURCE 0x0080 /* RO Transmit Abort Source */ 108#define IG4_REG_SLV_DATA_NACK 0x0084 /* RW General Slave Data NACK */ 109#define IG4_REG_DMA_CTRL 0x0088 /* RW DMA Control */ 110#define IG4_REG_DMA_TDLR 0x008C /* RW DMA Transmit Data Level */ 111#define IG4_REG_DMA_RDLR 0x0090 /* RW DMA Receive Data Level */ 112#define IG4_REG_SDA_SETUP 0x0094 /* RW SDA Setup */ 113#define IG4_REG_ACK_GENERAL_CALL 0x0098 /* RW I2C ACK General Call */ 114#define IG4_REG_ENABLE_STATUS 0x009C /* RO Enable Status */ 115/* Available at least on Atom SoCs, Haswell mobile and some Skylakes. */ 116#define IG4_REG_COMP_PARAM1 0x00F4 /* RO Component Parameter */ 117#define IG4_REG_COMP_VER 0x00F8 /* RO Component Version */ 118/* Available at least on Atom SoCs */ 119#define IG4_REG_COMP_TYPE 0x00FC /* RO Probe width/endian? (linux) */ 120/* 0x200-0x2FF - Additional registers available on Skylake-U/Y and others */ 121#define IG4_REG_RESETS_SKL 0x0204 /* RW Reset Register */ 122#define IG4_REG_ACTIVE_LTR_VALUE 0x0210 /* RW Active LTR Value */ 123#define IG4_REG_IDLE_LTR_VALUE 0x0214 /* RW Idle LTR Value */ 124#define IG4_REG_TX_ACK_COUNT 0x0218 /* RO TX ACK Count */ 125#define IG4_REG_RX_BYTE_COUNT 0x021C /* RO RX ACK Count */ 126#define IG4_REG_DEVIDLE_CTRL 0x024C /* RW Device Control */ 127/* Available at least on Atom SoCs */ 128#define IG4_REG_CLK_PARMS 0x0800 /* RW Clock Parameters */ 129/* Available at least on Atom SoCs and Haswell mobile */ 130#define IG4_REG_RESETS_HSW 0x0804 /* RW Reset Register */ 131#define IG4_REG_GENERAL 0x0808 /* RW General Register */ 132/* These LTR config registers are at least available on Haswell mobile. */ 133#define IG4_REG_SW_LTR_VALUE 0x0810 /* RW SW LTR Value */ 134#define IG4_REG_AUTO_LTR_VALUE 0x0814 /* RW Auto LTR Value */ 135 136/* 137 * CTL - Control Register 22.2.1 138 * Default Value: 0x0000007F. 139 * 140 * RESTARTEN - RW Restart Enable 141 * 10BIT - RW Controller operates in 10-bit mode, else 7-bit 142 * 143 * NOTE: When restart is disabled the controller is incapable of 144 * performing the following functions: 145 * 146 * Sending a START Byte 147 * Performing any high-speed mode op 148 * Performing direction changes in combined format mode 149 * Performing a read operation with a 10-bit address 150 * 151 * Attempting to perform the above operations will result in the 152 * TX_ABORT bit being set in RAW_INTR_STAT. 153 */ 154#define IG4_CTL_SLAVE_DISABLE 0x0040 /* snarfed from linux */ 155#define IG4_CTL_RESTARTEN 0x0020 /* Allow Restart when master */ 156#define IG4_CTL_10BIT 0x0010 /* ctlr accepts 10-bit addresses */ 157#define IG4_CTL_SPEED_MASK 0x0006 /* speed at which the I2C operates */ 158#define IG4_CTL_MASTER 0x0001 /* snarfed from linux */ 159 160#define IG4_CTL_SPEED_HIGH 0x0006 /* snarfed from linux */ 161#define IG4_CTL_SPEED_FAST 0x0004 /* snarfed from linux */ 162#define IG4_CTL_SPEED_STD 0x0002 /* snarfed from linux */ 163 164/* 165 * TAR_ADD - Target Address Register 22.2.2 166 * Default Value: 0x00000055F 167 * 168 * 10BIT - RW controller starts its transfers in 10-bit 169 * address mode, else 7-bit. 170 * 171 * SPECIAL - RW Indicates whether software performs a General Call 172 * or START BYTE command. 173 * 174 * 0 Ignore GC_OR_START and use TAR address. 175 * 176 * 1 Perform special I2C Command based on GC_OR_START. 177 * 178 * GC_OR_START - RW (only if SPECIAL is set) 179 * 180 * 0 General Call Address. After issuing a General Call, 181 * only writes may be performed. Attempting to issue 182 * a read command results in IX_ABRT in RAW_INTR_STAT. 183 * The controller remains in General Call mode until 184 * bit 11 (SPECIAL) is cleared. 185 * 186 * 1 START BYTE. 187 * 188 * 189 * IC_TAR - RW when transmitting a general call, these bits are 190 * ignored. To generate a START BYTE, the address 191 * needs to be written into these bits once. 192 * 193 * This register should only be updated when the IIC is disabled (I2C_ENABLE=0) 194 */ 195#define IG4_TAR_10BIT 0x1000 /* start xfer in 10-bit mode */ 196#define IG4_TAR_SPECIAL 0x0800 /* Perform special command */ 197#define IG4_TAR_GC_OR_START 0x0400 /* General Call or Start */ 198#define IG4_TAR_ADDR_MASK 0x03FF /* Target address */ 199 200/* 201 * TAR_DATA_CMD - Data Buffer and Command Register 22.2.3 202 * 203 * RESTART - RW This bit controls whether a forced RESTART is 204 * issued before the byte is sent or received. 205 * 206 * 0 If not set a RESTART is only issued if the transfer 207 * direction is changing from the previous command. 208 * 209 * 1 A RESTART is issued before the byte is sent or 210 * received, regardless of whether or not the transfer 211 * direction is changing from the previous command. 212 * 213 * STOP - RW This bit controls whether a STOP is issued after 214 * the byte is sent or received. 215 * 216 * 0 STOP is not issued after this byte, regardless 217 * of whether or not the Tx FIFO is empty. 218 * 219 * 1 STOP is issued after this byte, regardless of 220 * whether or not the Tx FIFO is empty. If the 221 * Tx FIFO is not empty the master immediately tries 222 * to start a new transfer by issuing a START and 223 * arbitrating for the bus. 224 * 225 * i.e. the STOP is issued along with this byte, 226 * within the write stream. 227 * 228 * COMMAND - RW Control whether a read or write is performed. 229 * 230 * 0 WRITE 231 * 232 * 1 READ 233 * 234 * DATA (7:0) - RW Contains the data to be transmitted or received 235 * on the I2C bus. 236 * 237 * NOTE: Writing to this register causes a START + slave + RW to be 238 * issued if the direction has changed or the last data byte was 239 * sent with a STOP. 240 * 241 * NOTE: We control termination? so this register must be written 242 * for each byte we wish to receive. We can then drain the 243 * receive FIFO. 244 */ 245 246#define IG4_DATA_RESTART 0x0400 /* Force RESTART */ 247#define IG4_DATA_STOP 0x0200 /* Force STOP[+START] */ 248#define IG4_DATA_COMMAND_RD 0x0100 /* bus direction 0=write 1=read */ 249#define IG4_DATA_MASK 0x00FF 250 251/* 252 * SS_SCL_HCNT - Standard Speed Clock High Count Register 22.2.4 253 * SS_SCL_LCNT - Standard Speed Clock Low Count Register 22.2.5 254 * FS_SCL_HCNT - Fast Speed Clock High Count Register 22.2.6 255 * FS_SCL_LCNT - Fast Speed Clock Low Count Register 22.2.7 256 * 257 * COUNT (15:0) - Set the period count to a value between 6 and 258 * 65525. 259 */ 260#define IG4_SCL_CLOCK_MASK 0xFFFFU /* count bits in register */ 261 262/* 263 * INTR_STAT - (RO) Interrupt Status Register 22.2.8 264 * INTR_MASK - (RW) Interrupt Mask Register 22.2.9 265 * RAW_INTR_STAT- (RO) Raw Interrupt Status Register 22.2.10 266 * 267 * GEN_CALL Set only when a general call (broadcast) address 268 * is received and acknowleged, stays set until 269 * cleared by reading CLR_GEN_CALL. 270 * 271 * START_DET Set when a START or RESTART condition has occurred 272 * on the interface. 273 * 274 * STOP_DET Set when a STOP condition has occurred on the 275 * interface. 276 * 277 * ACTIVITY Set by any activity on the interface. Cleared 278 * by reading CLR_ACTIVITY or CLR_INTR. 279 * 280 * TX_ABRT Indicates the controller as a transmitter is 281 * unable to complete the intended action. When set, 282 * the controller will hold the TX FIFO in a reset 283 * state (flushed) until CLR_TX_ABORT is read to 284 * clear the condition. Once cleared, the TX FIFO 285 * will be available again. 286 * 287 * TX_EMPTY Indicates that the transmitter is at or below 288 * the specified TX_TL threshold. Automatically 289 * cleared by HW when the buffer level goes above 290 * the threshold. 291 * 292 * TX_OVER Indicates that the processor attempted to write 293 * to the TX FIFO while the TX FIFO was full. Cleared 294 * by reading CLR_TX_OVER. 295 * 296 * RX_FULL Indicates that the receive FIFO has reached or 297 * exceeded the specified RX_TL threshold. Cleared 298 * by HW when the cpu drains the FIFO to below the 299 * threshold. 300 * 301 * RX_OVER Indicates that the receive FIFO was unable to 302 * accept new data and data was lost. Cleared by 303 * reading CLR_RX_OVER. 304 * 305 * RX_UNDER Indicates that the cpu attempted to read data 306 * from the receive buffer while the RX FIFO was 307 * empty. Cleared by reading CLR_RX_UNDER. 308 * 309 * NOTES ON RAW_INTR_STAT: 310 * 311 * This register can be used to monitor the GEN_CALL, START_DET, 312 * STOP_DET, ACTIVITY, TX_ABRT, TX_EMPTY, TX_OVER, RX_FULL, RX_OVER, 313 * and RX_UNDER bits. The documentation is a bit unclear but presumably 314 * this is the unlatched version. 315 * 316 * Code should test FIFO conditions using the I2C_STA (status) register, 317 * not the interrupt status registers. 318 */ 319 320#define IG4_INTR_GEN_CALL 0x0800 321#define IG4_INTR_START_DET 0x0400 322#define IG4_INTR_STOP_DET 0x0200 323#define IG4_INTR_ACTIVITY 0x0100 324#define IG4_INTR_TX_ABRT 0x0040 325#define IG4_INTR_TX_EMPTY 0x0010 326#define IG4_INTR_TX_OVER 0x0008 327#define IG4_INTR_RX_FULL 0x0004 328#define IG4_INTR_RX_OVER 0x0002 329#define IG4_INTR_RX_UNDER 0x0001 330 331#define IG4_INTR_ERR_MASK (IG4_INTR_TX_ABRT | IG4_INTR_TX_OVER | \ 332 IG4_INTR_RX_OVER | IG4_INTR_RX_UNDER) 333 334/* 335 * RX_TL - (RW) Receive FIFO Threshold Register 22.2.11 336 * TX_TL - (RW) Transmit FIFO Threshold Register 22.2.12 337 * 338 * Specify the receive and transmit FIFO threshold register. The 339 * FIFOs have 16 elements. The valid range is 0-15. Setting a 340 * value greater than 15 causes the actual value to be the maximum 341 * depth of the FIFO. 342 * 343 * Generally speaking since everything is messaged, we can use a 344 * mid-level setting for both parameters and (e.g.) fully drain the 345 * receive FIFO on the STOP_DET condition to handle loose ends. 346 */ 347#define IG4_FIFO_MASK 0x00FF 348#define IG4_FIFO_LIMIT 16 349 350/* 351 * CLR_INTR - (RO) Clear Interrupt Register 22.2.13 352 * CLR_RX_UNDER - (RO) Clear Interrupt Register (specific) 22.2.14 353 * CLR_RX_OVER - (RO) Clear Interrupt Register (specific) 22.2.15 354 * CLR_TX_OVER - (RO) Clear Interrupt Register (specific) 22.2.16 355 * CLR_TX_ABORT - (RO) Clear Interrupt Register (specific) 22.2.17 356 * CLR_ACTIVITY - (RO) Clear Interrupt Register (specific) 22.2.18 357 * CLR_STOP_DET - (RO) Clear Interrupt Register (specific) 22.2.19 358 * CLR_START_DET- (RO) Clear Interrupt Register (specific) 22.2.20 359 * CLR_GEN_CALL - (RO) Clear Interrupt Register (specific) 22.2.21 360 * 361 * CLR_* specific operations clear the appropriate bit in the 362 * RAW_INTR_STAT register. Intel does not really document whether 363 * these operations clear the normal interrupt status register. 364 * 365 * CLR_INTR clears bits in the normal interrupt status register and 366 * presumably also the raw(?) register? Intel is again unclear. 367 * 368 * NOTE: CLR_INTR only clears software-clearable interrupts. Hardware 369 * clearable interrupts are controlled entirely by the hardware. 370 * CLR_INTR also clears the TX_ABRT_SOURCE register. 371 * 372 * NOTE: CLR_TX_ABORT also clears the TX_ABRT_SOURCE register and releases 373 * the TX FIFO from its flushed/reset state, allowing more writes 374 * to the TX FIFO. 375 * 376 * NOTE: CLR_ACTIVITY has no effect if the I2C bus is still active. 377 * Intel documents that the bit is automatically cleared when 378 * there is no further activity on the bus. 379 */ 380#define IG4_CLR_BIT 0x0001 /* Reflects source */ 381 382/* 383 * I2C_EN - (RW) I2C Enable Register 22.2.22 384 * 385 * ABORT Software can abort an I2C transfer by setting this 386 * bit. In response, the controller issues the STOP 387 * condition over the I2C bus, followed by TX FIFO flush. 388 * Hardware will clear the bit once the STOP has 389 * been detected. This bit can only be set while the 390 * I2C interface is enabled. 391 * 392 * I2C_ENABLE Enable the controller, else disable it. 393 * (Use I2C_ENABLE_STATUS to poll enable status 394 * & wait for changes) 395 */ 396#define IG4_I2C_ABORT 0x0002 397#define IG4_I2C_ENABLE 0x0001 398 399/* 400 * I2C_STA - (RO) I2C Status Register 22.2.23 401 */ 402#define IG4_STATUS_ACTIVITY 0x0020 /* Controller is active */ 403#define IG4_STATUS_RX_FULL 0x0010 /* RX FIFO completely full */ 404#define IG4_STATUS_RX_NOTEMPTY 0x0008 /* RX FIFO not empty */ 405#define IG4_STATUS_TX_EMPTY 0x0004 /* TX FIFO completely empty */ 406#define IG4_STATUS_TX_NOTFULL 0x0002 /* TX FIFO not full */ 407#define IG4_STATUS_I2C_ACTIVE 0x0001 /* I2C bus is active */ 408 409/* 410 * TXFLR - (RO) Transmit FIFO Level Register 22.2.24 411 * RXFLR - (RO) Receive FIFO Level Register 22.2.25 412 * 413 * Read the number of entries currently in the Transmit or Receive 414 * FIFOs. Note that for some reason the mask is 9 bits instead of 415 * the 8 bits the fill level controls. 416 */ 417#define IG4_FIFOLVL_MASK 0x01FF 418 419/* 420 * SDA_HOLD - (RW) SDA Hold Time Length Register 22.2.26 421 * 422 * Set the SDA hold time length register in I2C clocks. 423 */ 424#define IG4_SDA_TX_HOLD_MASK 0x0000FFFF 425 426/* 427 * TX_ABRT_SOURCE- (RO) Transmit Abort Source Register 22.2.27 428 * 429 * Indicates the cause of a transmit abort. This can indicate a 430 * software programming error or a device expected address width 431 * mismatch or other issues. The NORESTART conditions and GENCALL_NOACK 432 * can only occur if a programming error was made in the driver software. 433 * 434 * In particular, it should be possible to detect whether any devices 435 * are on the bus by observing the GENCALL_READ status, and it might 436 * be possible to detect ADDR7 vs ADDR10 mismatches. 437 */ 438#define IG4_ABRTSRC_TRANSFER 0x00010000 /* Abort initiated by user */ 439#define IG4_ABRTSRC_ARBLOST 0x00001000 /* Arbitration lost */ 440#define IG4_ABRTSRC_NORESTART_10 0x00000400 /* RESTART disabled */ 441#define IG4_ABRTSRC_NORESTART_START 0x00000200 /* RESTART disabled */ 442#define IG4_ABRTSRC_ACKED_START 0x00000080 /* Improper acked START */ 443#define IG4_ABRTSRC_GENCALL_READ 0x00000020 /* Improper GENCALL */ 444#define IG4_ABRTSRC_GENCALL_NOACK 0x00000010 /* Nobody acked GENCALL */ 445#define IG4_ABRTSRC_TXNOACK_DATA 0x00000008 /* data phase no ACK */ 446#define IG4_ABRTSRC_TXNOACK_ADDR10_2 0x00000004 /* addr10/1 phase no ACK */ 447#define IG4_ABRTSRC_TXNOACK_ADDR10_1 0x00000002 /* addr10/2 phase no ACK */ 448#define IG4_ABRTSRC_TXNOACK_ADDR7 0x00000001 /* addr7 phase no ACK */ 449 450/* 451 * SLV_DATA_NACK - (RW) Generate Slave DATA NACK Register 22.2.28 452 * 453 * When the controller is a receiver a NACK can be generated on 454 * receipt of data. 455 * 456 * NACK_GENERATE Set to 0 for normal NACK/ACK generation. 457 * Set to 1 to generate a NACK after next data 458 * byte received. 459 * 460 */ 461#define IG4_NACK_GENERATE 0x0001 462 463/* 464 * DMA_CTRL - (RW) DMA Control Register 22.2.29 465 * 466 * Enables DMA on the transmit and/or receive DMA channel. 467 */ 468#define IG4_TX_DMA_ENABLE 0x0002 469#define IG4_RX_DMA_ENABLE 0x0001 470 471/* 472 * DMA_TDLR - (RW) DMA Transmit Data Level Register 22.2.30 473 * DMA_RDLR - (RW) DMA Receive Data Level Register 22.2.31 474 * 475 * Similar to RX_TL and TX_TL but controls when a DMA burst occurs 476 * to empty or fill the FIFOs. Use the same IG4_FIFO_MASK and 477 * IG4_FIFO_LIMIT defines for RX_RL and TX_TL. 478 */ 479/* empty */ 480 481/* 482 * SDA_SETUP - (RW) SDA Setup Time Length Register 22.2.32 483 * 484 * Set the SDA setup time length register in I2C clocks. 485 * The register must be programmed with a value >=2. 486 * (Defaults to 0x64). 487 */ 488#define IG4_SDA_SETUP_MASK 0x00FF 489 490/* 491 * ACK_GEN_CALL - (RW) ACK General Call Register 22.2.33 492 * 493 * Control whether the controller responds with a ACK or NACK when 494 * it receives an I2C General Call address. 495 * 496 * If set to 0 a NACK is generated and a General Call interrupt is 497 * NOT generated. Otherwise an ACK + interrupt is generated. 498 */ 499#define IG4_ACKGC_ACK 0x0001 500 501/* 502 * ENABLE_STATUS - (RO) Enable Status Registger 22.2.34 503 * 504 * DATA_LOST - Indicates that a slave receiver operation has 505 * been aborted with at least one data byte received 506 * from a transfer due to the I2C controller being 507 * disabled (IG4_I2C_ENABLE -> 0) 508 * 509 * ENABLED - Intel documentation is lacking but I assume this 510 * is a reflection of the IG4_I2C_ENABLE bit in the 511 * I2C_EN register. 512 * 513 */ 514#define IG4_ENASTAT_DATA_LOST 0x0004 515#define IG4_ENASTAT_ENABLED 0x0001 516 517/* 518 * COMP_PARAM1 - (RO) Component Parameter Register 22.2.35 519 * Default Value 0x00FFFF6E 520 * 521 * VALID - Intel documentation is unclear but I believe this 522 * must be read as a 1 to indicate that the rest of 523 * the bits in the register are valid. 524 * 525 * HASDMA - Indicates that the chip is DMA-capable. Presumably 526 * in certain virtualization cases the chip might be 527 * set to not be DMA-capable. 528 * 529 * INTR_IO - Indicates that all interrupts are combined to 530 * generate one interrupt. If not set, interrupts 531 * are individual (more virtualization stuff?) 532 * 533 * HCCNT_RO - Indicates that the clock timing registers are 534 * RW. If not set, the registers are RO. 535 * (more virtualization stuff). 536 * 537 * MAXSPEED - Indicates the maximum speed supported. 538 * 539 * DATAW - Indicates the internal bus width in bits. 540 */ 541#define IG4_PARAM1_TXFIFO_DEPTH(v) ((((v) >> 16) & 0xFF) + 1) 542#define IG4_PARAM1_RXFIFO_DEPTH(v) ((((v) >> 8) & 0xFF) + 1) 543#define IG4_PARAM1_CONFIG_VALID 0x00000080 544#define IG4_PARAM1_CONFIG_HASDMA 0x00000040 545#define IG4_PARAM1_CONFIG_INTR_IO 0x00000020 546#define IG4_PARAM1_CONFIG_HCCNT_RO 0x00000010 547#define IG4_PARAM1_CONFIG_MAXSPEED_MASK 0x0000000C 548#define IG4_PARAM1_CONFIG_DATAW_MASK 0x00000003 549 550#define IG4_CONFIG_MAXSPEED_RESERVED00 0x00000000 551#define IG4_CONFIG_MAXSPEED_STANDARD 0x00000004 552#define IG4_CONFIG_MAXSPEED_FAST 0x00000008 553#define IG4_CONFIG_MAXSPEED_HIGH 0x0000000C 554 555#define IG4_CONFIG_DATAW_8 0x00000000 556#define IG4_CONFIG_DATAW_16 0x00000001 557#define IG4_CONFIG_DATAW_32 0x00000002 558#define IG4_CONFIG_DATAW_RESERVED11 0x00000003 559 560/* 561 * COMP_VER - (RO) Component Version Register 22.2.36 562 * 563 * Contains the chip version number. All 32 bits. 564 */ 565#define IG4_COMP_MIN_VER 0x3131352A 566 567/* 568 * COMP_TYPE - (RO) (linux) Endian and bus width probe 569 * 570 * Read32 from this register and test against IG4_COMP_TYPE 571 * to determine the bus width. e.g. 01404457 = endian-reversed, 572 * and 00000140 or 00004457 means internal 16-bit bus (?). 573 * 574 * This register is not in the intel documentation, I pulled it 575 * from the linux driver i2c-designware-core.c. 576 */ 577#define IG4_COMP_TYPE 0x44570140 578 579/* 580 * RESETS - (RW) Resets Register 22.2.37 581 * 582 * Used to reset the I2C host controller by SW. There is no timing 583 * requirement, software can assert and de-assert in back-to-back 584 * transactions. 585 * 586 * 00 I2C host controller is NOT in reset. 587 * 01 (reserved) 588 * 10 (reserved) 589 * 11 I2C host controller is in reset. 590 */ 591#define IG4_RESETS_ASSERT_HSW 0x0003 592#define IG4_RESETS_DEASSERT_HSW 0x0000 593 594/* Skylake-U/Y and Kaby Lake-U/Y have the reset bits inverted */ 595#define IG4_RESETS_DEASSERT_SKL 0x0003 596#define IG4_RESETS_ASSERT_SKL 0x0000 597 598/* Newer versions of the I2C controller allow to check whether 599 * the above ASSERT/DEASSERT is necessary by querying the DEVIDLE_CONTROL 600 * register. 601 * 602 * the RESTORE_REQUIRED bit can be cleared by writing 1 603 * the DEVICE_IDLE status can be set to put the controller in an idle state 604 * 605 */ 606#define IG4_RESTORE_REQUIRED 0x0008 607#define IG4_DEVICE_IDLE 0x0004 608 609/* 610 * GENERAL - (RW) General Reigster 22.2.38 611 * 612 * IOVOLT 0=1.8V 1=3.3V 613 * 614 * LTR 0=Auto 1=SW 615 * 616 * In Auto mode the BIOS will write to the host controller's 617 * AUTO LTR Value register (offset 0x0814) with the active 618 * state LTR value, and will write to the SW LTR Value register 619 * (offset 0x0810) with the idle state LTR value. 620 * 621 * In SW mode the SW will write to the host controller SW LTR 622 * value (offset 0x0810). It is the SW responsibility to update 623 * the LTR with the appropriate value. 624 */ 625#define IG4_GENERAL_IOVOLT3_3 0x0008 626#define IG4_GENERAL_SWMODE 0x0004 627 628/* 629 * SW_LTR_VALUE - (RW) SW LTR Value Register 22.2.39 630 * AUTO_LTR_VALUE - (RW) SW LTR Value Register 22.2.40 631 * 632 * Default value is 0x00000800 which means the best possible 633 * service/response time. 634 * 635 * It isn't quite clear how the snooping works. There are two scale 636 * bits for both sets but two of the four codes are reserved. The 637 * *SNOOP_VALUE() is specified as a 10-bit latency value. If 0, it 638 * indicates that the device cannot tolerate any delay and needs the 639 * best possible service/response time. 640 * 641 * I think this is for snooping (testing) the I2C bus. The lowest 642 * delay (0) probably runs the controller polling at a high, power hungry 643 * rate. But I dunno. 644 */ 645#define IG4_SWLTR_NSNOOP_REQ 0x80000000 /* (ro) */ 646#define IG4_SWLTR_NSNOOP_SCALE_MASK 0x1C000000 /* (ro) */ 647#define IG4_SWLTR_NSNOOP_SCALE_1US 0x08000000 /* (ro) */ 648#define IG4_SWLTR_NSNOOP_SCALE_32US 0x0C000000 /* (ro) */ 649#define IG4_SWLTR_NSNOOP_VALUE_DECODE(v) (((v) >> 16) & 0x3F) 650#define IG4_SWLTR_NSNOOP_VALUE_ENCODE(v) (((v) & 0x3F) << 16) 651 652#define IG4_SWLTR_SNOOP_REQ 0x00008000 /* (rw) */ 653#define IG4_SWLTR_SNOOP_SCALE_MASK 0x00001C00 /* (rw) */ 654#define IG4_SWLTR_SNOOP_SCALE_1US 0x00000800 /* (rw) */ 655#define IG4_SWLTR_SNOOP_SCALE_32US 0x00000C00 /* (rw) */ 656#define IG4_SWLTR_SNOOP_VALUE_DECODE(v) ((v) & 0x3F) 657#define IG4_SWLTR_SNOOP_VALUE_ENCODE(v) ((v) & 0x3F) 658 659#endif /* _ICHIIC_IG4_REG_H_ */ 660