1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008 Joseph Koshy 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31#ifndef _DEV_HWPMC_CORE_H_ 32#define _DEV_HWPMC_CORE_H_ 1 33 34#define IA32_PERF_CAPABILITIES 0x345 35#define PERFCAP_LBR_FORMAT 0x003f 36#define PERFCAP_PEBS_TRAP 0x0040 37#define PERFCAP_PEBS_SAVEARCH 0x0080 38#define PERFCAP_PEBS_RECFORMAT 0x0f00 39#define PERFCAP_SMM_FREEZE 0x1000 40#define PERFCAP_FW_WRITE 0x2000 /* full width write aliases */ 41 42#define IAF_OS 0x1 43#define IAF_USR 0x2 44#define IAF_ANY 0x4 45#define IAF_PMI 0x8 46 47/* 48 * Programmable PMCs. 49 */ 50struct pmc_md_iap_op_pmcallocate { 51 uint32_t pm_iap_config; 52 uint64_t pm_iap_rsp; 53}; 54 55#define IAP_EVSEL(C) ((C) & 0xFF) 56#define IAP_UMASK(C) (((C) & 0xFF) << 8) 57#define IAP_USR (1 << 16) 58#define IAP_OS (1 << 17) 59#define IAP_EDGE (1 << 18) 60#define IAP_INT (1 << 20) 61#define IAP_ANY (1 << 21) 62#define IAP_EN (1 << 22) 63#define IAP_INV (1 << 23) 64#define IAP_CMASK(C) (((C) & 0xFF) << 24) 65 66#define IAP_EVSEL_GET(C) ((C) & 0xFF) 67#define IAP_UMASK_GET(C) (((C) & 0xFF00) >> 8) 68 69#define IA_OFFCORE_RSP_MASK_I7WM 0x000000F7FF 70#define IA_OFFCORE_RSP_MASK_SBIB 0x3F807F8FFF 71 72#ifdef _KERNEL 73 74/* 75 * Fixed-function counters. 76 */ 77 78#define IAF_MASK 0xF 79 80#define IAF_COUNTER_MASK 0x0000ffffffffffff 81#define IAF_CTR0 0x309 82#define IAF_CTR1 0x30A 83#define IAF_CTR2 0x30B 84 85/* 86 * The IAF_CTRL MSR is laid out in the following way. 87 * 88 * Bit Position Use 89 * 63 - 12 Reserved (do not touch) 90 * 11 Ctr 2 PMI 91 * 10 Reserved (do not touch) 92 * 9-8 Ctr 2 Enable 93 * 7 Ctr 1 PMI 94 * 6 Reserved (do not touch) 95 * 5-4 Ctr 1 Enable 96 * 3 Ctr 0 PMI 97 * 2 Reserved (do not touch) 98 * 1-0 Ctr 0 Enable (3: All Levels, 2: User, 1: OS, 0: Disable) 99 */ 100 101#define IAF_OFFSET 32 102#define IAF_CTRL 0x38D 103#define IAF_CTRL_MASK 0x0000000000000bbb 104 105/* 106 * Programmable counters. 107 */ 108 109#define IAP_PMC0 0x0C1 110#define IAP_A_PMC0 0x4C1 111 112/* 113 * IAP_EVSEL(n) is laid out in the following way. 114 * 115 * Bit Position Use 116 * 63-31 Reserved (do not touch) 117 * 31-24 Counter Mask 118 * 23 Invert 119 * 22 Enable 120 * 21 Reserved (do not touch) 121 * 20 APIC Interrupt Enable 122 * 19 Pin Control 123 * 18 Edge Detect 124 * 17 OS 125 * 16 User 126 * 15-8 Unit Mask 127 * 7-0 Event Select 128 */ 129 130#define IAP_EVSEL_MASK 0x00000000ffdfffff 131#define IAP_EVSEL0 0x186 132 133/* 134 * Simplified programming interface in Intel Performance Architecture 135 * v2 and later. 136 */ 137 138#define IA_GLOBAL_STATUS 0x38E 139#define IA_GLOBAL_CTRL 0x38F 140 141/* 142 * IA_GLOBAL_CTRL is laid out in the following way. 143 * 144 * Bit Position Use 145 * 63-35 Reserved (do not touch) 146 * 34 IAF Counter 2 Enable 147 * 33 IAF Counter 1 Enable 148 * 32 IAF Counter 0 Enable 149 * 31-0 Depends on programmable counters 150 */ 151 152/* The mask is only for the fixed porttion of the register. */ 153#define IAF_GLOBAL_CTRL_MASK 0x0000000700000000 154 155/* The mask is only for the programmable porttion of the register. */ 156#define IAP_GLOBAL_CTRL_MASK 0x00000000ffffffff 157 158/* The mask is for both the fixed and programmable porttions of the register. */ 159#define IA_GLOBAL_CTRL_MASK 0x00000007ffffffff 160 161#define IA_GLOBAL_OVF_CTRL 0x390 162 163#define IA_GLOBAL_STATUS_FLAG_CONDCHG (1ULL << 63) 164#define IA_GLOBAL_STATUS_FLAG_OVFBUF (1ULL << 62) 165 166/* 167 * Offcore response configuration. 168 */ 169#define IA_OFFCORE_RSP0 0x1A6 170#define IA_OFFCORE_RSP1 0x1A7 171 172struct pmc_md_iaf_pmc { 173 uint64_t pm_iaf_ctrl; 174}; 175 176struct pmc_md_iap_pmc { 177 uint32_t pm_iap_evsel; 178 uint64_t pm_iap_rsp; 179}; 180 181/* 182 * Prototypes. 183 */ 184 185int pmc_core_initialize(struct pmc_mdep *_md, int _maxcpu, 186 int _version_override); 187void pmc_core_finalize(struct pmc_mdep *_md); 188 189int pmc_iaf_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width); 190void pmc_iaf_finalize(struct pmc_mdep *_md); 191 192int pmc_iap_initialize(struct pmc_mdep *_md, int _maxcpu, int _npmc, int _width, 193 int _flags); 194void pmc_iap_finalize(struct pmc_mdep *_md); 195 196#endif /* _KERNEL */ 197#endif /* _DEV_HWPMC_CORE_H */ 198