1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2004-2005 MARVELL SEMICONDUCTOR ISRAEL, LTD.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 *
28 * $FreeBSD$
29 */
30#ifndef __INCmvSatah
31#define __INCmvSatah
32
33#ifndef SUPPORT_MV_SATA_GEN_1
34#define SUPPORT_MV_SATA_GEN_1 1
35#endif
36
37#ifndef SUPPORT_MV_SATA_GEN_2
38#define SUPPORT_MV_SATA_GEN_2 0
39#endif
40
41#ifndef SUPPORT_MV_SATA_GEN_2E
42#define SUPPORT_MV_SATA_GEN_2E 0
43#endif
44
45#if (SUPPORT_MV_SATA_GEN_1 + SUPPORT_MV_SATA_GEN_2 + SUPPORT_MV_SATA_GEN_2E) > 1
46
47#define MV_SATA_GEN_1(x) ((x)->sataAdapterGeneration==1)
48#define MV_SATA_GEN_2(x) ((x)->sataAdapterGeneration>=2)
49#define MV_SATA_GEN_2E(x) ((x)->sataAdapterGeneration==3)
50
51#elif SUPPORT_MV_SATA_GEN_1==1
52
53#define MV_SATA_GEN_1(x) 1
54#define MV_SATA_GEN_2(x) 0
55#define MV_SATA_GEN_2E(x) 0
56
57#elif SUPPORT_MV_SATA_GEN_2==1
58
59#define MV_SATA_GEN_1(x) 0
60#define MV_SATA_GEN_2(x) 1
61#define MV_SATA_GEN_2E(x) 0
62
63#elif SUPPORT_MV_SATA_GEN_2E==1
64
65#define MV_SATA_GEN_1(x)  0
66#define MV_SATA_GEN_2(x)  1 /* gen2E impiles gen2 */
67#define MV_SATA_GEN_2E(x) 1
68
69#else
70#error "Which IC do you support?"
71#endif
72
73/* Definitions */
74/* MV88SX50XX specific defines */
75#define MV_SATA_VENDOR_ID		   				0x11AB
76#define MV_SATA_DEVICE_ID_5080			   		0x5080
77#define MV_SATA_DEVICE_ID_5081			   		0x5081
78#define MV_SATA_DEVICE_ID_6080			   		0x6080
79#define MV_SATA_DEVICE_ID_6081			   		0x6081
80
81#if defined(RR2310) || defined(RR1740) || defined(RR2210) || defined (RR2522)
82#define MV_SATA_CHANNELS_NUM					4
83#define MV_SATA_UNITS_NUM						1
84#else
85#define MV_SATA_CHANNELS_NUM					8
86#define MV_SATA_UNITS_NUM						2
87#endif
88
89#define MV_SATA_PCI_BAR0_SPACE_SIZE				(1<<18) /* 256 Kb*/
90
91#define CHANNEL_QUEUE_LENGTH					32
92#define CHANNEL_QUEUE_MASK					    0x1F
93
94#define MV_EDMA_QUEUE_LENGTH					32	/* Up to 32 outstanding	 */
95                        							/* commands per SATA channel*/
96#define MV_EDMA_QUEUE_MASK                      0x1F
97#define MV_EDMA_REQUEST_QUEUE_SIZE				1024 /* 32*32 = 1KBytes */
98#define MV_EDMA_RESPONSE_QUEUE_SIZE				256  /* 32*8 = 256 Bytes */
99
100#define MV_EDMA_REQUEST_ENTRY_SIZE				32
101#define MV_EDMA_RESPONSE_ENTRY_SIZE				8
102
103#define MV_EDMA_PRD_ENTRY_SIZE					16		/* 16Bytes*/
104#define MV_EDMA_PRD_NO_SNOOP_FLAG				0x00000001 /* MV_BIT0 */
105#define MV_EDMA_PRD_EOT_FLAG					0x00008000 /* MV_BIT15 */
106
107#define MV_ATA_IDENTIFY_DEV_DATA_LENGTH  		256	/* number of words(2 byte)*/
108#define MV_ATA_MODEL_NUMBER_LEN					40
109#define ATA_SECTOR_SIZE							512
110/* Log messages level defines */
111#define MV_DEBUG								0x1
112#define MV_DEBUG_INIT							0x2
113#define MV_DEBUG_INTERRUPTS						0x4
114#define MV_DEBUG_SATA_LINK						0x8
115#define MV_DEBUG_UDMA_COMMAND					0x10
116#define MV_DEBUG_NON_UDMA_COMMAND				0x20
117#define MV_DEBUG_ERROR							0x40
118
119
120/* Typedefs    */
121typedef enum mvUdmaType
122{
123	MV_UDMA_TYPE_READ, MV_UDMA_TYPE_WRITE
124} MV_UDMA_TYPE;
125
126typedef enum mvFlushType
127{
128	MV_FLUSH_TYPE_CALLBACK, MV_FLUSH_TYPE_NONE
129} MV_FLUSH_TYPE;
130
131typedef enum mvCompletionType
132{
133	MV_COMPLETION_TYPE_NORMAL, MV_COMPLETION_TYPE_ERROR,
134	MV_COMPLETION_TYPE_ABORT
135} MV_COMPLETION_TYPE;
136
137typedef enum mvEventType
138{
139	MV_EVENT_TYPE_ADAPTER_ERROR, MV_EVENT_TYPE_SATA_CABLE
140} MV_EVENT_TYPE;
141
142typedef enum mvEdmaMode
143{
144	MV_EDMA_MODE_QUEUED,
145	MV_EDMA_MODE_NOT_QUEUED,
146	MV_EDMA_MODE_NATIVE_QUEUING
147} MV_EDMA_MODE;
148
149typedef enum mvEdmaQueueResult
150{
151	MV_EDMA_QUEUE_RESULT_OK = 0,
152	MV_EDMA_QUEUE_RESULT_EDMA_DISABLED,
153	MV_EDMA_QUEUE_RESULT_FULL,
154	MV_EDMA_QUEUE_RESULT_BAD_LBA_ADDRESS,
155	MV_EDMA_QUEUE_RESULT_BAD_PARAMS
156} MV_EDMA_QUEUE_RESULT;
157
158typedef enum mvQueueCommandResult
159{
160	MV_QUEUE_COMMAND_RESULT_OK = 0,
161	MV_QUEUE_COMMAND_RESULT_QUEUED_MODE_DISABLED,
162	MV_QUEUE_COMMAND_RESULT_FULL,
163	MV_QUEUE_COMMAND_RESULT_BAD_LBA_ADDRESS,
164	MV_QUEUE_COMMAND_RESULT_BAD_PARAMS
165} MV_QUEUE_COMMAND_RESULT;
166
167typedef enum mvNonUdmaProtocol
168{
169    MV_NON_UDMA_PROTOCOL_NON_DATA,
170    MV_NON_UDMA_PROTOCOL_PIO_DATA_IN,
171    MV_NON_UDMA_PROTOCOL_PIO_DATA_OUT
172} MV_NON_UDMA_PROTOCOL;
173
174
175struct mvDmaRequestQueueEntry;
176struct mvDmaResponseQueueEntry;
177struct mvDmaCommandEntry;
178
179struct mvSataAdapter;
180struct mvStorageDevRegisters;
181
182typedef MV_BOOLEAN (* HPTLIBAPI mvSataCommandCompletionCallBack_t)(struct mvSataAdapter *,
183														 MV_U8,
184                                                         MV_COMPLETION_TYPE,
185														 MV_VOID_PTR, MV_U16,
186														 MV_U32,
187											    struct mvStorageDevRegisters SS_SEG*);
188
189typedef enum mvQueuedCommandType
190{
191	MV_QUEUED_COMMAND_TYPE_UDMA,
192	MV_QUEUED_COMMAND_TYPE_NONE_UDMA
193} MV_QUEUED_COMMAND_TYPE;
194
195typedef struct mvUdmaCommandParams
196{
197	MV_UDMA_TYPE readWrite;
198	MV_BOOLEAN   isEXT;
199	MV_U32       lowLBAAddress;
200	MV_U16       highLBAAddress;
201	MV_U16       numOfSectors;
202	MV_U32       prdLowAddr;
203	MV_U32       prdHighAddr;
204	mvSataCommandCompletionCallBack_t callBack;
205	MV_VOID_PTR  commandId;
206} MV_UDMA_COMMAND_PARAMS;
207
208typedef struct mvNoneUdmaCommandParams
209{
210  	MV_NON_UDMA_PROTOCOL protocolType;
211	MV_BOOLEAN  isEXT;
212	MV_U16_PTR	bufPtr;
213	MV_U32		count;
214	MV_U16		features;
215	MV_U16		sectorCount;
216	MV_U16		lbaLow;
217	MV_U16		lbaMid;
218	MV_U16		lbaHigh;
219	MV_U8		device;
220	MV_U8		command;
221    mvSataCommandCompletionCallBack_t callBack;
222	MV_VOID_PTR  commandId;
223} MV_NONE_UDMA_COMMAND_PARAMS;
224
225typedef struct mvQueueCommandInfo
226{
227	MV_QUEUED_COMMAND_TYPE	type;
228	union
229	{
230		MV_UDMA_COMMAND_PARAMS		udmaCommand;
231		MV_NONE_UDMA_COMMAND_PARAMS	NoneUdmaCommand;
232    } commandParams;
233} MV_QUEUE_COMMAND_INFO;
234
235/* The following structure is for the Core Driver internal usage */
236typedef struct mvQueuedCommandEntry
237{
238    MV_BOOLEAN   isFreeEntry;
239    MV_U8        commandTag;
240	struct mvQueuedCommandEntry	*next;
241	struct mvQueuedCommandEntry	*prev;
242	MV_QUEUE_COMMAND_INFO	commandInfo;
243} MV_QUEUED_COMMAND_ENTRY;
244
245/* The following structures are part of the Core Driver API */
246typedef struct mvSataChannel
247{
248	/* Fields set by Intermediate Application Layer */
249	MV_U8                       channelNumber;
250	MV_BOOLEAN                  waitingForInterrupt;
251	MV_BOOLEAN                  lba48Address;
252	MV_BOOLEAN                  maxReadTransfer;
253	struct mvDmaRequestQueueEntry SS_SEG *requestQueue;
254	struct mvDmaResponseQueueEntry SS_SEG *responseQueue;
255	MV_U32                      requestQueuePciHiAddress;
256	MV_U32                      requestQueuePciLowAddress;
257	MV_U32                      responseQueuePciHiAddress;
258	MV_U32                      responseQueuePciLowAddress;
259	/* Fields set by CORE driver */
260	struct mvSataAdapter        *mvSataAdapter;
261	MV_OS_SEMAPHORE             semaphore;
262	MV_U32                      eDmaRegsOffset;
263	MV_U16                      identifyDevice[MV_ATA_IDENTIFY_DEV_DATA_LENGTH];
264	MV_BOOLEAN                  EdmaActive;
265	MV_EDMA_MODE                queuedDMA;
266	MV_U8                       outstandingCommands;
267	MV_BOOLEAN					workAroundDone;
268	struct mvQueuedCommandEntry	commandsQueue[CHANNEL_QUEUE_LENGTH];
269	struct mvQueuedCommandEntry	*commandsQueueHead;
270	struct mvQueuedCommandEntry	*commandsQueueTail;
271	MV_BOOLEAN					queueCommandsEnabled;
272	MV_U8                       noneUdmaOutstandingCommands;
273	MV_U8                       EdmaQueuedCommands;
274    MV_U32                      freeIDsStack[CHANNEL_QUEUE_LENGTH];
275	MV_U32                      freeIDsNum;
276	MV_U32                      reqInPtr;
277	MV_U32                      rspOutPtr;
278} MV_SATA_CHANNEL;
279
280typedef struct mvSataAdapter
281{
282	/* Fields set by Intermediate Application Layer */
283	MV_U32            adapterId;
284	MV_U8             pcbVersion;
285    MV_U8             pciConfigRevisionId;
286    MV_U16            pciConfigDeviceId;
287	MV_VOID_PTR		  IALData;
288	MV_BUS_ADDR_T     adapterIoBaseAddress;
289	MV_U32            intCoalThre[MV_SATA_UNITS_NUM];
290	MV_U32            intTimeThre[MV_SATA_UNITS_NUM];
291	MV_BOOLEAN        (* HPTLIBAPI mvSataEventNotify)(struct mvSataAdapter *,
292										   MV_EVENT_TYPE,
293										   MV_U32, MV_U32);
294	MV_SATA_CHANNEL   *sataChannel[MV_SATA_CHANNELS_NUM];
295	MV_U32            pciCommand;
296	MV_U32            pciSerrMask;
297	MV_U32            pciInterruptMask;
298
299	/* Fields set by CORE driver */
300	MV_OS_SEMAPHORE   semaphore;
301	MV_U32			  mainMask;
302	MV_OS_SEMAPHORE	  interruptsMaskSem;
303    MV_BOOLEAN        implementA0Workarounds;
304    MV_BOOLEAN        implement50XXB0Workarounds;
305	MV_BOOLEAN        implement50XXB1Workarounds;
306	MV_BOOLEAN        implement50XXB2Workarounds;
307	MV_BOOLEAN        implement60X1A0Workarounds;
308	MV_BOOLEAN        implement60X1A1Workarounds;
309	MV_BOOLEAN        implement60X1B0Workarounds;
310	MV_BOOLEAN		  implement7042A0Workarounds;
311	MV_BOOLEAN		  implement7042A1Workarounds;
312	MV_U8			  sataAdapterGeneration;
313	MV_BOOLEAN		isPEX;
314	MV_U8             failLEDMask;
315    MV_U8			  signalAmps[MV_SATA_CHANNELS_NUM];
316	MV_U8			  pre[MV_SATA_CHANNELS_NUM];
317    MV_BOOLEAN        staggaredSpinup[MV_SATA_CHANNELS_NUM]; /* For 60x1 only */
318} MV_SATA_ADAPTER;
319
320typedef struct mvSataAdapterStatus
321{
322	/* Fields set by CORE driver */
323	MV_BOOLEAN		channelConnected[MV_SATA_CHANNELS_NUM];
324	MV_U32			pciDLLStatusAndControlRegister;
325	MV_U32			pciCommandRegister;
326	MV_U32			pciModeRegister;
327	MV_U32			pciSERRMaskRegister;
328	MV_U32			intCoalThre[MV_SATA_UNITS_NUM];
329	MV_U32			intTimeThre[MV_SATA_UNITS_NUM];
330	MV_U32			R00StatusBridgePortRegister[MV_SATA_CHANNELS_NUM];
331}MV_SATA_ADAPTER_STATUS;
332
333
334typedef struct mvSataChannelStatus
335{
336	/* Fields set by CORE driver */
337	MV_BOOLEAN		isConnected;
338	MV_U8			modelNumber[MV_ATA_MODEL_NUMBER_LEN];
339	MV_BOOLEAN		DMAEnabled;
340	MV_EDMA_MODE	queuedDMA;
341	MV_U8			outstandingCommands;
342	MV_U32			EdmaConfigurationRegister;
343	MV_U32			EdmaRequestQueueBaseAddressHighRegister;
344	MV_U32			EdmaRequestQueueInPointerRegister;
345	MV_U32			EdmaRequestQueueOutPointerRegister;
346	MV_U32			EdmaResponseQueueBaseAddressHighRegister;
347	MV_U32			EdmaResponseQueueInPointerRegister;
348	MV_U32			EdmaResponseQueueOutPointerRegister;
349	MV_U32			EdmaCommandRegister;
350	MV_U32			PHYModeRegister;
351}MV_SATA_CHANNEL_STATUS;
352
353/* this structure used by the IAL defines the PRD entries used by the EDMA HW */
354typedef struct mvSataEdmaPRDEntry
355{
356	volatile MV_U32	lowBaseAddr;
357	volatile MV_U16	byteCount;
358	volatile MV_U16	flags;
359	volatile MV_U32 highBaseAddr;
360	volatile MV_U32 reserved;
361}MV_SATA_EDMA_PRD_ENTRY;
362
363/* API Functions */
364
365/* CORE driver Adapter Management */
366MV_BOOLEAN HPTLIBAPI mvSataInitAdapter(MV_SATA_ADAPTER *pAdapter);
367
368MV_BOOLEAN HPTLIBAPI mvSataShutdownAdapter(MV_SATA_ADAPTER *pAdapter);
369
370MV_BOOLEAN HPTLIBAPI mvSataGetAdapterStatus(MV_SATA_ADAPTER *pAdapter,
371								  MV_SATA_ADAPTER_STATUS *pAdapterStatus);
372
373MV_U32  HPTLIBAPI mvSataReadReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset);
374
375MV_VOID HPTLIBAPI mvSataWriteReg(MV_SATA_ADAPTER *pAdapter, MV_U32 regOffset,
376					   MV_U32 regValue);
377
378MV_VOID HPTLIBAPI mvEnableAutoFlush(MV_VOID);
379MV_VOID HPTLIBAPI mvDisableAutoFlush(MV_VOID);
380
381
382/* CORE driver SATA Channel Management */
383MV_BOOLEAN HPTLIBAPI mvSataConfigureChannel(MV_SATA_ADAPTER *pAdapter,
384								  MV_U8 channelIndex);
385
386MV_BOOLEAN HPTLIBAPI mvSataRemoveChannel(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex);
387
388MV_BOOLEAN HPTLIBAPI mvSataIsStorageDeviceConnected(MV_SATA_ADAPTER *pAdapter,
389										  MV_U8 channelIndex);
390
391MV_BOOLEAN HPTLIBAPI mvSataChannelHardReset(MV_SATA_ADAPTER *pAdapter,
392								  MV_U8 channelIndex);
393
394MV_BOOLEAN HPTLIBAPI mvSataConfigEdmaMode(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
395								MV_EDMA_MODE eDmaMode, MV_U8 maxQueueDepth);
396
397MV_BOOLEAN HPTLIBAPI mvSataEnableChannelDma(MV_SATA_ADAPTER *pAdapter,
398								  MV_U8 channelIndex);
399
400MV_BOOLEAN HPTLIBAPI mvSataDisableChannelDma(MV_SATA_ADAPTER *pAdapter,
401								   MV_U8 channelIndex);
402
403MV_BOOLEAN HPTLIBAPI mvSataFlushDmaQueue(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
404							   MV_FLUSH_TYPE flushType);
405
406MV_U8 HPTLIBAPI mvSataNumOfDmaCommands(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex);
407
408MV_BOOLEAN HPTLIBAPI mvSataSetIntCoalParams (MV_SATA_ADAPTER *pAdapter, MV_U8 sataUnit,
409								   MV_U32 intCoalThre, MV_U32 intTimeThre);
410
411MV_BOOLEAN HPTLIBAPI mvSataSetChannelPhyParams(MV_SATA_ADAPTER *pAdapter,
412									 MV_U8 channelIndex,
413									 MV_U8 signalAmps, MV_U8 pre);
414
415MV_BOOLEAN HPTLIBAPI mvSataChannelPhyShutdown(MV_SATA_ADAPTER *pAdapter,
416									MV_U8 channelIndex);
417
418MV_BOOLEAN HPTLIBAPI mvSataChannelPhyPowerOn(MV_SATA_ADAPTER *pAdapter,
419									MV_U8 channelIndex);
420
421MV_BOOLEAN HPTLIBAPI mvSataChannelSetEdmaLoopBackMode(MV_SATA_ADAPTER *pAdapter,
422											MV_U8 channelIndex,
423											MV_BOOLEAN loopBackOn);
424
425MV_BOOLEAN HPTLIBAPI mvSataGetChannelStatus(MV_SATA_ADAPTER *pAdapter, MV_U8 channelIndex,
426								  MV_SATA_CHANNEL_STATUS *pChannelStatus);
427
428MV_QUEUE_COMMAND_RESULT HPTLIBAPI mvSataQueueCommand(MV_SATA_ADAPTER *pAdapter,
429										   MV_U8 channelIndex,
430										   MV_QUEUE_COMMAND_INFO SS_SEG *pCommandParams);
431
432/* Interrupt Service Routine */
433MV_BOOLEAN HPTLIBAPI mvSataInterruptServiceRoutine(MV_SATA_ADAPTER *pAdapter);
434
435MV_BOOLEAN HPTLIBAPI mvSataMaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter);
436
437MV_BOOLEAN HPTLIBAPI mvSataUnmaskAdapterInterrupt(MV_SATA_ADAPTER *pAdapter);
438
439/* Command Completion and Event Notification (user implemented) */
440MV_BOOLEAN HPTLIBAPI mvSataEventNotify(MV_SATA_ADAPTER *, MV_EVENT_TYPE ,
441							 MV_U32, MV_U32);
442
443/*
444 * Staggered spin-ip support and SATA interface speed control
445 * (relevant for 60x1 adapters)
446 */
447MV_BOOLEAN HPTLIBAPI mvSataEnableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter);
448MV_BOOLEAN HPTLIBAPI mvSataDisableStaggeredSpinUpAll (MV_SATA_ADAPTER *pAdapter);
449
450#endif
451