1/* $NetBSD: pcscpreg.h,v 1.2 2008/04/28 20:23:55 martin Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-2-Clause-NetBSD 5 * 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Izumi Tsutsui. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 23 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 24 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31 * POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* $FreeBSD$ */ 35 36#ifndef _AM53C974_H_ 37#define _AM53C974_H_ 38 39/* 40 * Am53c974 DMA engine registers 41 */ 42 43#define DMA_CMD 0x40 /* Command */ 44#define DMACMD_RSVD 0xFFFFFF28 /* reserved */ 45#define DMACMD_DIR 0x00000080 /* Transfer Direction (read:1) */ 46#define DMACMD_INTE 0x00000040 /* DMA Interrupt Enable */ 47#define DMACMD_MDL 0x00000010 /* Map to Memory Description List */ 48#define DMACMD_DIAG 0x00000004 /* Diagnostic */ 49#define DMACMD_CMD 0x00000003 /* Command Code Bit */ 50#define DMACMD_IDLE 0x00000000 /* Idle */ 51#define DMACMD_BLAST 0x00000001 /* Blast */ 52#define DMACMD_ABORT 0x00000002 /* Abort */ 53#define DMACMD_START 0x00000003 /* Start */ 54 55#define DMA_STC 0x44 /* Start Transfer Count */ 56#define DMA_SPA 0x48 /* Start Physical Address */ 57#define DMA_WBC 0x4C /* Working Byte Counter */ 58#define DMA_WAC 0x50 /* Working Address Counter */ 59 60#define DMA_STAT 0x54 /* Status Register */ 61#define DMASTAT_RSVD 0xFFFFFF80 /* reserved */ 62#define DMASTAT_PABT 0x00000040 /* PCI master/target Abort */ 63#define DMASTAT_BCMP 0x00000020 /* BLAST Complete */ 64#define DMASTAT_SINT 0x00000010 /* SCSI Interrupt */ 65#define DMASTAT_DONE 0x00000008 /* DMA Transfer Terminated */ 66#define DMASTAT_ABT 0x00000004 /* DMA Transfer Aborted */ 67#define DMASTAT_ERR 0x00000002 /* DMA Transfer Error */ 68#define DMASTAT_PWDN 0x00000001 /* Power Down Indicator */ 69 70#define DMA_SMDLA 0x58 /* Starting Memory Descpritor List Address */ 71#define DMA_WMAC 0x5C /* Working MDL Counter */ 72#define DMA_SBAC 0x70 /* SCSI Bus and Control */ 73 74#endif /* _AM53C974_H_ */ 75