1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 2016 Michael Zhilin <mizhka@gmail.com> 6 * Copyright (c) 2017 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Landon Fuller 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer, 17 * without modification. 18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 20 * redistribution must be conditioned upon including a substantially 21 * similar Disclaimer requirement for further binary redistribution. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37#include <sys/cdefs.h> 38__FBSDID("$FreeBSD$"); 39 40/* 41 * Broadcom ChipCommon driver. 42 * 43 * With the exception of some very early chipsets, the ChipCommon core 44 * has been included in all HND SoCs and chipsets based on the siba(4) 45 * and bcma(4) interconnects, providing a common interface to chipset 46 * identification, bus enumeration, UARTs, clocks, watchdog interrupts, 47 * GPIO, flash, etc. 48 */ 49 50#include <sys/param.h> 51#include <sys/kernel.h> 52#include <sys/lock.h> 53#include <sys/bus.h> 54#include <sys/rman.h> 55#include <sys/malloc.h> 56#include <sys/module.h> 57#include <sys/mutex.h> 58#include <sys/systm.h> 59 60#include <machine/bus.h> 61#include <machine/resource.h> 62 63#include <dev/bhnd/bhnd.h> 64#include <dev/bhnd/bhndvar.h> 65 66#include "chipcreg.h" 67#include "chipcvar.h" 68 69#include "chipc_private.h" 70 71devclass_t bhnd_chipc_devclass; /**< bhnd(4) chipcommon device class */ 72 73static struct bhnd_device_quirk chipc_quirks[]; 74 75/* Supported device identifiers */ 76static const struct bhnd_device chipc_devices[] = { 77 BHND_DEVICE(BCM, CC, NULL, chipc_quirks), 78 BHND_DEVICE(BCM, 4706_CC, NULL, chipc_quirks), 79 BHND_DEVICE_END 80}; 81 82 83/* Device quirks table */ 84static struct bhnd_device_quirk chipc_quirks[] = { 85 /* HND OTP controller revisions */ 86 BHND_CORE_QUIRK (HWREV_EQ (12), CHIPC_QUIRK_OTP_HND), /* (?) */ 87 BHND_CORE_QUIRK (HWREV_EQ (17), CHIPC_QUIRK_OTP_HND), /* BCM4311 */ 88 BHND_CORE_QUIRK (HWREV_EQ (22), CHIPC_QUIRK_OTP_HND), /* BCM4312 */ 89 90 /* IPX OTP controller revisions */ 91 BHND_CORE_QUIRK (HWREV_EQ (21), CHIPC_QUIRK_OTP_IPX), 92 BHND_CORE_QUIRK (HWREV_GTE(23), CHIPC_QUIRK_OTP_IPX), 93 94 BHND_CORE_QUIRK (HWREV_GTE(32), CHIPC_QUIRK_SUPPORTS_SPROM), 95 BHND_CORE_QUIRK (HWREV_GTE(35), CHIPC_QUIRK_SUPPORTS_CAP_EXT), 96 BHND_CORE_QUIRK (HWREV_GTE(49), CHIPC_QUIRK_IPX_OTPL_SIZE), 97 98 /* 4706 variant quirks */ 99 BHND_CORE_QUIRK (HWREV_EQ (38), CHIPC_QUIRK_4706_NFLASH), /* BCM5357? */ 100 BHND_CHIP_QUIRK (4706, HWREV_ANY, CHIPC_QUIRK_4706_NFLASH), 101 102 /* 4331 quirks*/ 103 BHND_CHIP_QUIRK (4331, HWREV_ANY, CHIPC_QUIRK_4331_EXTPA_MUX_SPROM), 104 BHND_PKG_QUIRK (4331, TN, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 105 BHND_PKG_QUIRK (4331, TNA0, CHIPC_QUIRK_4331_GPIO2_5_MUX_SPROM), 106 BHND_PKG_QUIRK (4331, TT, CHIPC_QUIRK_4331_EXTPA2_MUX_SPROM), 107 108 /* 4360 quirks */ 109 BHND_CHIP_QUIRK (4352, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 110 BHND_CHIP_QUIRK (43460, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 111 BHND_CHIP_QUIRK (43462, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 112 BHND_CHIP_QUIRK (43602, HWREV_LTE(2), CHIPC_QUIRK_4360_FEM_MUX_SPROM), 113 114 BHND_DEVICE_QUIRK_END 115}; 116 117static int chipc_add_children(struct chipc_softc *sc); 118 119static bhnd_nvram_src chipc_find_nvram_src(struct chipc_softc *sc, 120 struct chipc_caps *caps); 121static int chipc_read_caps(struct chipc_softc *sc, 122 struct chipc_caps *caps); 123 124static bool chipc_should_enable_muxed_sprom( 125 struct chipc_softc *sc); 126static int chipc_enable_otp_power(struct chipc_softc *sc); 127static void chipc_disable_otp_power(struct chipc_softc *sc); 128static int chipc_enable_sprom_pins(struct chipc_softc *sc); 129static void chipc_disable_sprom_pins(struct chipc_softc *sc); 130 131static int chipc_try_activate_resource(struct chipc_softc *sc, 132 device_t child, int type, int rid, 133 struct resource *r, bool req_direct); 134 135static int chipc_init_rman(struct chipc_softc *sc); 136static void chipc_free_rman(struct chipc_softc *sc); 137static struct rman *chipc_get_rman(struct chipc_softc *sc, int type); 138 139/* quirk and capability flag convenience macros */ 140#define CHIPC_QUIRK(_sc, _name) \ 141 ((_sc)->quirks & CHIPC_QUIRK_ ## _name) 142 143#define CHIPC_CAP(_sc, _name) \ 144 ((_sc)->caps._name) 145 146#define CHIPC_ASSERT_QUIRK(_sc, name) \ 147 KASSERT(CHIPC_QUIRK((_sc), name), ("quirk " __STRING(_name) " not set")) 148 149#define CHIPC_ASSERT_CAP(_sc, name) \ 150 KASSERT(CHIPC_CAP((_sc), name), ("capability " __STRING(_name) " not set")) 151 152static int 153chipc_probe(device_t dev) 154{ 155 const struct bhnd_device *id; 156 157 id = bhnd_device_lookup(dev, chipc_devices, sizeof(chipc_devices[0])); 158 if (id == NULL) 159 return (ENXIO); 160 161 bhnd_set_default_core_desc(dev); 162 return (BUS_PROBE_DEFAULT); 163} 164 165static int 166chipc_attach(device_t dev) 167{ 168 struct chipc_softc *sc; 169 int error; 170 171 sc = device_get_softc(dev); 172 sc->dev = dev; 173 sc->quirks = bhnd_device_quirks(dev, chipc_devices, 174 sizeof(chipc_devices[0])); 175 sc->sprom_refcnt = 0; 176 177 CHIPC_LOCK_INIT(sc); 178 STAILQ_INIT(&sc->mem_regions); 179 180 /* Set up resource management */ 181 if ((error = chipc_init_rman(sc))) { 182 device_printf(sc->dev, 183 "failed to initialize chipc resource state: %d\n", error); 184 goto failed; 185 } 186 187 /* Allocate the region containing the chipc register block */ 188 if ((sc->core_region = chipc_find_region_by_rid(sc, 0)) == NULL) { 189 error = ENXIO; 190 goto failed; 191 } 192 193 error = chipc_retain_region(sc, sc->core_region, 194 RF_ALLOCATED|RF_ACTIVE); 195 if (error) { 196 sc->core_region = NULL; 197 goto failed; 198 } 199 200 /* Save a direct reference to our chipc registers */ 201 sc->core = sc->core_region->cr_res; 202 203 /* Fetch and parse capability register(s) */ 204 if ((error = chipc_read_caps(sc, &sc->caps))) 205 goto failed; 206 207 if (bootverbose) 208 chipc_print_caps(sc->dev, &sc->caps); 209 210 /* Attach all supported child devices */ 211 if ((error = chipc_add_children(sc))) 212 goto failed; 213 214 /* 215 * Register ourselves with the bus; we're fully initialized and can 216 * response to ChipCommin API requests. 217 * 218 * Since our children may need access to ChipCommon, this must be done 219 * before attaching our children below (via bus_generic_attach). 220 */ 221 if ((error = bhnd_register_provider(dev, BHND_SERVICE_CHIPC))) 222 goto failed; 223 224 if ((error = bus_generic_attach(dev))) 225 goto failed; 226 227 return (0); 228 229failed: 230 device_delete_children(sc->dev); 231 232 if (sc->core_region != NULL) { 233 chipc_release_region(sc, sc->core_region, 234 RF_ALLOCATED|RF_ACTIVE); 235 } 236 237 chipc_free_rman(sc); 238 CHIPC_LOCK_DESTROY(sc); 239 return (error); 240} 241 242static int 243chipc_detach(device_t dev) 244{ 245 struct chipc_softc *sc; 246 int error; 247 248 sc = device_get_softc(dev); 249 250 if ((error = bus_generic_detach(dev))) 251 return (error); 252 253 if ((error = device_delete_children(dev))) 254 return (error); 255 256 if ((error = bhnd_deregister_provider(dev, BHND_SERVICE_ANY))) 257 return (error); 258 259 chipc_release_region(sc, sc->core_region, RF_ALLOCATED|RF_ACTIVE); 260 chipc_free_rman(sc); 261 262 CHIPC_LOCK_DESTROY(sc); 263 264 return (0); 265} 266 267static int 268chipc_add_children(struct chipc_softc *sc) 269{ 270 device_t child; 271 const char *flash_bus; 272 int error; 273 274 /* SPROM/OTP */ 275 if (sc->caps.nvram_src == BHND_NVRAM_SRC_SPROM || 276 sc->caps.nvram_src == BHND_NVRAM_SRC_OTP) 277 { 278 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_nvram", -1); 279 if (child == NULL) { 280 device_printf(sc->dev, "failed to add nvram device\n"); 281 return (ENXIO); 282 } 283 284 /* Both OTP and external SPROM are mapped at CHIPC_SPROM_OTP */ 285 error = chipc_set_mem_resource(sc, child, 0, CHIPC_SPROM_OTP, 286 CHIPC_SPROM_OTP_SIZE, 0, 0); 287 if (error) { 288 device_printf(sc->dev, "failed to set OTP memory " 289 "resource: %d\n", error); 290 return (error); 291 } 292 } 293 294 /* 295 * PMU/PWR_CTRL 296 * 297 * On AOB ("Always on Bus") devices, the PMU core (if it exists) is 298 * attached directly to the bhnd(4) bus -- not chipc. 299 */ 300 if (sc->caps.pmu && !sc->caps.aob) { 301 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pmu", -1); 302 if (child == NULL) { 303 device_printf(sc->dev, "failed to add pmu\n"); 304 return (ENXIO); 305 } 306 } else if (sc->caps.pwr_ctrl) { 307 child = BUS_ADD_CHILD(sc->dev, 0, "bhnd_pwrctl", -1); 308 if (child == NULL) { 309 device_printf(sc->dev, "failed to add pwrctl\n"); 310 return (ENXIO); 311 } 312 } 313 314 /* GPIO */ 315 child = BUS_ADD_CHILD(sc->dev, 0, "gpio", -1); 316 if (child == NULL) { 317 device_printf(sc->dev, "failed to add gpio\n"); 318 return (ENXIO); 319 } 320 321 error = chipc_set_mem_resource(sc, child, 0, 0, RM_MAX_END, 0, 0); 322 if (error) { 323 device_printf(sc->dev, "failed to set gpio memory resource: " 324 "%d\n", error); 325 return (error); 326 } 327 328 /* All remaining devices are SoC-only */ 329 if (bhnd_get_attach_type(sc->dev) != BHND_ATTACH_NATIVE) 330 return (0); 331 332 /* UARTs */ 333 for (u_int i = 0; i < min(sc->caps.num_uarts, CHIPC_UART_MAX); i++) { 334 int irq_rid, mem_rid; 335 336 irq_rid = 0; 337 mem_rid = 0; 338 339 child = BUS_ADD_CHILD(sc->dev, 0, "uart", -1); 340 if (child == NULL) { 341 device_printf(sc->dev, "failed to add uart%u\n", i); 342 return (ENXIO); 343 } 344 345 /* Shared IRQ */ 346 error = chipc_set_irq_resource(sc, child, irq_rid, 0); 347 if (error) { 348 device_printf(sc->dev, "failed to set uart%u irq %u\n", 349 i, 0); 350 return (error); 351 } 352 353 /* UART registers are mapped sequentially */ 354 error = chipc_set_mem_resource(sc, child, mem_rid, 355 CHIPC_UART(i), CHIPC_UART_SIZE, 0, 0); 356 if (error) { 357 device_printf(sc->dev, "failed to set uart%u memory " 358 "resource: %d\n", i, error); 359 return (error); 360 } 361 } 362 363 /* Flash */ 364 flash_bus = chipc_flash_bus_name(sc->caps.flash_type); 365 if (flash_bus != NULL) { 366 int rid; 367 368 child = BUS_ADD_CHILD(sc->dev, 0, flash_bus, -1); 369 if (child == NULL) { 370 device_printf(sc->dev, "failed to add %s device\n", 371 flash_bus); 372 return (ENXIO); 373 } 374 375 /* flash memory mapping */ 376 rid = 0; 377 error = chipc_set_mem_resource(sc, child, rid, 0, RM_MAX_END, 1, 378 1); 379 if (error) { 380 device_printf(sc->dev, "failed to set flash memory " 381 "resource %d: %d\n", rid, error); 382 return (error); 383 } 384 385 /* flashctrl registers */ 386 rid++; 387 error = chipc_set_mem_resource(sc, child, rid, 388 CHIPC_SFLASH_BASE, CHIPC_SFLASH_SIZE, 0, 0); 389 if (error) { 390 device_printf(sc->dev, "failed to set flash memory " 391 "resource %d: %d\n", rid, error); 392 return (error); 393 } 394 } 395 396 return (0); 397} 398 399/** 400 * Determine the NVRAM data source for this device. 401 * 402 * The SPROM, OTP, and flash capability flags must be fully populated in 403 * @p caps. 404 * 405 * @param sc chipc driver state. 406 * @param caps capability flags to be used to derive NVRAM configuration. 407 */ 408static bhnd_nvram_src 409chipc_find_nvram_src(struct chipc_softc *sc, struct chipc_caps *caps) 410{ 411 uint32_t otp_st, srom_ctrl; 412 413 /* 414 * We check for hardware presence in order of precedence. For example, 415 * SPROM is is always used in preference to internal OTP if found. 416 */ 417 if (CHIPC_QUIRK(sc, SUPPORTS_SPROM) && caps->sprom) { 418 srom_ctrl = bhnd_bus_read_4(sc->core, CHIPC_SPROM_CTRL); 419 if (srom_ctrl & CHIPC_SRC_PRESENT) 420 return (BHND_NVRAM_SRC_SPROM); 421 } 422 423 /* Check for programmed OTP H/W subregion (contains SROM data) */ 424 if (CHIPC_QUIRK(sc, SUPPORTS_OTP) && caps->otp_size > 0) { 425 /* TODO: need access to HND-OTP device */ 426 if (!CHIPC_QUIRK(sc, OTP_HND)) { 427 device_printf(sc->dev, 428 "NVRAM unavailable: unsupported OTP controller.\n"); 429 return (BHND_NVRAM_SRC_UNKNOWN); 430 } 431 432 otp_st = bhnd_bus_read_4(sc->core, CHIPC_OTPST); 433 if (otp_st & CHIPC_OTPS_GUP_HW) 434 return (BHND_NVRAM_SRC_OTP); 435 } 436 437 /* Check for flash */ 438 if (caps->flash_type != CHIPC_FLASH_NONE) 439 return (BHND_NVRAM_SRC_FLASH); 440 441 /* No NVRAM hardware capability declared */ 442 return (BHND_NVRAM_SRC_UNKNOWN); 443} 444 445/* Read and parse chipc capabilities */ 446static int 447chipc_read_caps(struct chipc_softc *sc, struct chipc_caps *caps) 448{ 449 uint32_t cap_reg; 450 uint32_t cap_ext_reg; 451 uint32_t regval; 452 453 /* Fetch cap registers */ 454 cap_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES); 455 cap_ext_reg = 0; 456 if (CHIPC_QUIRK(sc, SUPPORTS_CAP_EXT)) 457 cap_ext_reg = bhnd_bus_read_4(sc->core, CHIPC_CAPABILITIES_EXT); 458 459 /* Extract values */ 460 caps->num_uarts = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_NUM_UART); 461 caps->mipseb = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_MIPSEB); 462 caps->uart_gpio = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_UARTGPIO); 463 caps->uart_clock = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_UCLKSEL); 464 465 caps->extbus_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_EXTBUS); 466 caps->pwr_ctrl = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PWR_CTL); 467 caps->jtag_master = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_JTAGP); 468 469 caps->pll_type = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_PLL); 470 caps->backplane_64 = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_BKPLN64); 471 caps->boot_rom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ROM); 472 caps->pmu = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_PMU); 473 caps->eci = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_ECI); 474 caps->sprom = CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_SPROM); 475 caps->otp_size = CHIPC_GET_BITS(cap_reg, CHIPC_CAP_OTP_SIZE); 476 477 caps->seci = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_SECI); 478 caps->gsio = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_GSIO); 479 caps->aob = CHIPC_GET_FLAG(cap_ext_reg, CHIPC_CAP2_AOB); 480 481 /* Fetch OTP size for later IPX controller revisions */ 482 if (CHIPC_QUIRK(sc, IPX_OTPL_SIZE)) { 483 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 484 caps->otp_size = CHIPC_GET_BITS(regval, CHIPC_OTPL_SIZE); 485 } 486 487 /* Determine flash type and parameters */ 488 caps->cfi_width = 0; 489 switch (CHIPC_GET_BITS(cap_reg, CHIPC_CAP_FLASH)) { 490 case CHIPC_CAP_SFLASH_ST: 491 caps->flash_type = CHIPC_SFLASH_ST; 492 break; 493 case CHIPC_CAP_SFLASH_AT: 494 caps->flash_type = CHIPC_SFLASH_AT; 495 break; 496 case CHIPC_CAP_NFLASH: 497 /* unimplemented */ 498 caps->flash_type = CHIPC_NFLASH; 499 break; 500 case CHIPC_CAP_PFLASH: 501 caps->flash_type = CHIPC_PFLASH_CFI; 502 503 /* determine cfi width */ 504 regval = bhnd_bus_read_4(sc->core, CHIPC_FLASH_CFG); 505 if (CHIPC_GET_FLAG(regval, CHIPC_FLASH_CFG_DS)) 506 caps->cfi_width = 2; 507 else 508 caps->cfi_width = 1; 509 510 break; 511 case CHIPC_CAP_FLASH_NONE: 512 caps->flash_type = CHIPC_FLASH_NONE; 513 break; 514 515 } 516 517 /* Handle 4706_NFLASH fallback */ 518 if (CHIPC_QUIRK(sc, 4706_NFLASH) && 519 CHIPC_GET_FLAG(cap_reg, CHIPC_CAP_4706_NFLASH)) 520 { 521 caps->flash_type = CHIPC_NFLASH_4706; 522 } 523 524 525 /* Determine NVRAM source. Must occur after the SPROM/OTP/flash 526 * capability flags have been populated. */ 527 caps->nvram_src = chipc_find_nvram_src(sc, caps); 528 529 /* Determine the SPROM offset within OTP (if any). SPROM-formatted 530 * data is placed within the OTP general use region. */ 531 caps->sprom_offset = 0; 532 if (caps->nvram_src == BHND_NVRAM_SRC_OTP) { 533 CHIPC_ASSERT_QUIRK(sc, OTP_IPX); 534 535 /* Bit offset to GUP HW subregion containing SPROM data */ 536 regval = bhnd_bus_read_4(sc->core, CHIPC_OTPLAYOUT); 537 caps->sprom_offset = CHIPC_GET_BITS(regval, CHIPC_OTPL_GUP); 538 539 /* Convert to bytes */ 540 caps->sprom_offset /= 8; 541 } 542 543 return (0); 544} 545 546static int 547chipc_suspend(device_t dev) 548{ 549 return (bus_generic_suspend(dev)); 550} 551 552static int 553chipc_resume(device_t dev) 554{ 555 return (bus_generic_resume(dev)); 556} 557 558static void 559chipc_probe_nomatch(device_t dev, device_t child) 560{ 561 struct resource_list *rl; 562 const char *name; 563 564 name = device_get_name(child); 565 if (name == NULL) 566 name = "unknown device"; 567 568 device_printf(dev, "<%s> at", name); 569 570 rl = BUS_GET_RESOURCE_LIST(dev, child); 571 if (rl != NULL) { 572 resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#jx"); 573 resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%jd"); 574 } 575 576 printf(" (no driver attached)\n"); 577} 578 579static int 580chipc_print_child(device_t dev, device_t child) 581{ 582 struct resource_list *rl; 583 int retval = 0; 584 585 retval += bus_print_child_header(dev, child); 586 587 rl = BUS_GET_RESOURCE_LIST(dev, child); 588 if (rl != NULL) { 589 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, 590 "%#jx"); 591 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, 592 "%jd"); 593 } 594 595 retval += bus_print_child_domain(dev, child); 596 retval += bus_print_child_footer(dev, child); 597 598 return (retval); 599} 600 601static int 602chipc_child_pnpinfo_str(device_t dev, device_t child, char *buf, 603 size_t buflen) 604{ 605 if (buflen == 0) 606 return (EOVERFLOW); 607 608 *buf = '\0'; 609 return (0); 610} 611 612static int 613chipc_child_location_str(device_t dev, device_t child, char *buf, 614 size_t buflen) 615{ 616 if (buflen == 0) 617 return (EOVERFLOW); 618 619 *buf = '\0'; 620 return (ENXIO); 621} 622 623static device_t 624chipc_add_child(device_t dev, u_int order, const char *name, int unit) 625{ 626 struct chipc_softc *sc; 627 struct chipc_devinfo *dinfo; 628 device_t child; 629 630 sc = device_get_softc(dev); 631 632 child = device_add_child_ordered(dev, order, name, unit); 633 if (child == NULL) 634 return (NULL); 635 636 dinfo = malloc(sizeof(struct chipc_devinfo), M_BHND, M_NOWAIT); 637 if (dinfo == NULL) { 638 device_delete_child(dev, child); 639 return (NULL); 640 } 641 642 resource_list_init(&dinfo->resources); 643 dinfo->irq_mapped = false; 644 device_set_ivars(child, dinfo); 645 646 return (child); 647} 648 649static void 650chipc_child_deleted(device_t dev, device_t child) 651{ 652 struct chipc_devinfo *dinfo = device_get_ivars(child); 653 654 if (dinfo != NULL) { 655 /* Free the child's resource list */ 656 resource_list_free(&dinfo->resources); 657 658 /* Unmap the child's IRQ */ 659 if (dinfo->irq_mapped) { 660 bhnd_unmap_intr(dev, dinfo->irq); 661 dinfo->irq_mapped = false; 662 } 663 664 free(dinfo, M_BHND); 665 } 666 667 device_set_ivars(child, NULL); 668} 669 670static struct resource_list * 671chipc_get_resource_list(device_t dev, device_t child) 672{ 673 struct chipc_devinfo *dinfo = device_get_ivars(child); 674 return (&dinfo->resources); 675} 676 677 678/* Allocate region records for the given port, and add the port's memory 679 * range to the mem_rman */ 680static int 681chipc_rman_init_regions (struct chipc_softc *sc, bhnd_port_type type, 682 u_int port) 683{ 684 struct chipc_region *cr; 685 rman_res_t start, end; 686 u_int num_regions; 687 int error; 688 689 num_regions = bhnd_get_region_count(sc->dev, type, port); 690 for (u_int region = 0; region < num_regions; region++) { 691 /* Allocate new region record */ 692 cr = chipc_alloc_region(sc, type, port, region); 693 if (cr == NULL) 694 return (ENODEV); 695 696 /* Can't manage regions that cannot be allocated */ 697 if (cr->cr_rid < 0) { 698 BHND_DEBUG_DEV(sc->dev, "no rid for chipc region " 699 "%s%u.%u", bhnd_port_type_name(type), port, region); 700 chipc_free_region(sc, cr); 701 continue; 702 } 703 704 /* Add to rman's managed range */ 705 start = cr->cr_addr; 706 end = cr->cr_end; 707 if ((error = rman_manage_region(&sc->mem_rman, start, end))) { 708 chipc_free_region(sc, cr); 709 return (error); 710 } 711 712 /* Add to region list */ 713 STAILQ_INSERT_TAIL(&sc->mem_regions, cr, cr_link); 714 } 715 716 return (0); 717} 718 719/* Initialize memory state for all chipc port regions */ 720static int 721chipc_init_rman(struct chipc_softc *sc) 722{ 723 u_int num_ports; 724 int error; 725 726 /* Port types for which we'll register chipc_region mappings */ 727 bhnd_port_type types[] = { 728 BHND_PORT_DEVICE 729 }; 730 731 /* Initialize resource manager */ 732 sc->mem_rman.rm_start = 0; 733 sc->mem_rman.rm_end = BUS_SPACE_MAXADDR; 734 sc->mem_rman.rm_type = RMAN_ARRAY; 735 sc->mem_rman.rm_descr = "ChipCommon Device Memory"; 736 if ((error = rman_init(&sc->mem_rman))) { 737 device_printf(sc->dev, "could not initialize mem_rman: %d\n", 738 error); 739 return (error); 740 } 741 742 /* Populate per-port-region state */ 743 for (u_int i = 0; i < nitems(types); i++) { 744 num_ports = bhnd_get_port_count(sc->dev, types[i]); 745 for (u_int port = 0; port < num_ports; port++) { 746 error = chipc_rman_init_regions(sc, types[i], port); 747 if (error) { 748 device_printf(sc->dev, 749 "region init failed for %s%u: %d\n", 750 bhnd_port_type_name(types[i]), port, 751 error); 752 753 goto failed; 754 } 755 } 756 } 757 758 return (0); 759 760failed: 761 chipc_free_rman(sc); 762 return (error); 763} 764 765/* Free memory management state */ 766static void 767chipc_free_rman(struct chipc_softc *sc) 768{ 769 struct chipc_region *cr, *cr_next; 770 771 STAILQ_FOREACH_SAFE(cr, &sc->mem_regions, cr_link, cr_next) 772 chipc_free_region(sc, cr); 773 774 rman_fini(&sc->mem_rman); 775} 776 777/** 778 * Return the rman instance for a given resource @p type, if any. 779 * 780 * @param sc The chipc device state. 781 * @param type The resource type (e.g. SYS_RES_MEMORY, SYS_RES_IRQ, ...) 782 */ 783static struct rman * 784chipc_get_rman(struct chipc_softc *sc, int type) 785{ 786 switch (type) { 787 case SYS_RES_MEMORY: 788 return (&sc->mem_rman); 789 790 case SYS_RES_IRQ: 791 /* We delegate IRQ resource management to the parent bus */ 792 return (NULL); 793 794 default: 795 return (NULL); 796 }; 797} 798 799static struct resource * 800chipc_alloc_resource(device_t dev, device_t child, int type, 801 int *rid, rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 802{ 803 struct chipc_softc *sc; 804 struct chipc_region *cr; 805 struct resource_list_entry *rle; 806 struct resource *rv; 807 struct rman *rm; 808 int error; 809 bool passthrough, isdefault; 810 811 sc = device_get_softc(dev); 812 passthrough = (device_get_parent(child) != dev); 813 isdefault = RMAN_IS_DEFAULT_RANGE(start, end); 814 rle = NULL; 815 816 /* Fetch the resource manager, delegate request if necessary */ 817 rm = chipc_get_rman(sc, type); 818 if (rm == NULL) { 819 /* Requested resource type is delegated to our parent */ 820 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 821 start, end, count, flags); 822 return (rv); 823 } 824 825 /* Populate defaults */ 826 if (!passthrough && isdefault) { 827 /* Fetch the resource list entry. */ 828 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), 829 type, *rid); 830 if (rle == NULL) { 831 device_printf(dev, 832 "default resource %#x type %d for child %s " 833 "not found\n", *rid, type, 834 device_get_nameunit(child)); 835 return (NULL); 836 } 837 838 if (rle->res != NULL) { 839 device_printf(dev, 840 "resource entry %#x type %d for child %s is busy " 841 "[%d]\n", 842 *rid, type, device_get_nameunit(child), 843 rman_get_flags(rle->res)); 844 845 return (NULL); 846 } 847 848 start = rle->start; 849 end = rle->end; 850 count = ulmax(count, rle->count); 851 } 852 853 /* Locate a mapping region */ 854 if ((cr = chipc_find_region(sc, start, end)) == NULL) { 855 /* Resource requests outside our shared port regions can be 856 * delegated to our parent. */ 857 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 858 start, end, count, flags); 859 return (rv); 860 } 861 862 /* 863 * As a special case, children that map the complete ChipCommon register 864 * block are delegated to our parent. 865 * 866 * The rman API does not support sharing resources that are not 867 * identical in size; since we allocate subregions to various children, 868 * any children that need to map the entire register block (e.g. because 869 * they require access to discontiguous register ranges) must make the 870 * allocation through our parent, where we hold a compatible 871 * RF_SHAREABLE allocation. 872 */ 873 if (cr == sc->core_region && cr->cr_addr == start && 874 cr->cr_end == end && cr->cr_count == count) 875 { 876 rv = bus_generic_rl_alloc_resource(dev, child, type, rid, 877 start, end, count, flags); 878 return (rv); 879 } 880 881 /* Try to retain a region reference */ 882 if ((error = chipc_retain_region(sc, cr, RF_ALLOCATED))) 883 return (NULL); 884 885 /* Make our rman reservation */ 886 rv = rman_reserve_resource(rm, start, end, count, flags & ~RF_ACTIVE, 887 child); 888 if (rv == NULL) { 889 chipc_release_region(sc, cr, RF_ALLOCATED); 890 return (NULL); 891 } 892 893 rman_set_rid(rv, *rid); 894 895 /* Activate */ 896 if (flags & RF_ACTIVE) { 897 error = bus_activate_resource(child, type, *rid, rv); 898 if (error) { 899 device_printf(dev, 900 "failed to activate entry %#x type %d for " 901 "child %s: %d\n", 902 *rid, type, device_get_nameunit(child), error); 903 904 chipc_release_region(sc, cr, RF_ALLOCATED); 905 rman_release_resource(rv); 906 907 return (NULL); 908 } 909 } 910 911 /* Update child's resource list entry */ 912 if (rle != NULL) { 913 rle->res = rv; 914 rle->start = rman_get_start(rv); 915 rle->end = rman_get_end(rv); 916 rle->count = rman_get_size(rv); 917 } 918 919 return (rv); 920} 921 922static int 923chipc_release_resource(device_t dev, device_t child, int type, int rid, 924 struct resource *r) 925{ 926 struct chipc_softc *sc; 927 struct chipc_region *cr; 928 struct rman *rm; 929 struct resource_list_entry *rle; 930 int error; 931 932 sc = device_get_softc(dev); 933 934 /* Handled by parent bus? */ 935 rm = chipc_get_rman(sc, type); 936 if (rm == NULL || !rman_is_region_manager(r, rm)) { 937 return (bus_generic_rl_release_resource(dev, child, type, rid, 938 r)); 939 } 940 941 /* Locate the mapping region */ 942 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 943 if (cr == NULL) 944 return (EINVAL); 945 946 /* Deactivate resources */ 947 if (rman_get_flags(r) & RF_ACTIVE) { 948 error = BUS_DEACTIVATE_RESOURCE(dev, child, type, rid, r); 949 if (error) 950 return (error); 951 } 952 953 if ((error = rman_release_resource(r))) 954 return (error); 955 956 /* Drop allocation reference */ 957 chipc_release_region(sc, cr, RF_ALLOCATED); 958 959 /* Clear reference from the resource list entry if exists */ 960 rle = resource_list_find(BUS_GET_RESOURCE_LIST(dev, child), type, rid); 961 if (rle != NULL) 962 rle->res = NULL; 963 964 return (0); 965} 966 967static int 968chipc_adjust_resource(device_t dev, device_t child, int type, 969 struct resource *r, rman_res_t start, rman_res_t end) 970{ 971 struct chipc_softc *sc; 972 struct chipc_region *cr; 973 struct rman *rm; 974 975 sc = device_get_softc(dev); 976 977 /* Handled by parent bus? */ 978 rm = chipc_get_rman(sc, type); 979 if (rm == NULL || !rman_is_region_manager(r, rm)) { 980 return (bus_generic_adjust_resource(dev, child, type, r, start, 981 end)); 982 } 983 984 /* The range is limited to the existing region mapping */ 985 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 986 if (cr == NULL) 987 return (EINVAL); 988 989 if (end <= start) 990 return (EINVAL); 991 992 if (start < cr->cr_addr || end > cr->cr_end) 993 return (EINVAL); 994 995 /* Range falls within the existing region */ 996 return (rman_adjust_resource(r, start, end)); 997} 998 999/** 1000 * Retain an RF_ACTIVE reference to the region mapping @p r, and 1001 * configure @p r with its subregion values. 1002 * 1003 * @param sc Driver instance state. 1004 * @param child Requesting child device. 1005 * @param type resource type of @p r. 1006 * @param rid resource id of @p r 1007 * @param r resource to be activated. 1008 * @param req_direct If true, failure to allocate a direct bhnd resource 1009 * will be treated as an error. If false, the resource will not be marked 1010 * as RF_ACTIVE if bhnd direct resource allocation fails. 1011 */ 1012static int 1013chipc_try_activate_resource(struct chipc_softc *sc, device_t child, int type, 1014 int rid, struct resource *r, bool req_direct) 1015{ 1016 struct rman *rm; 1017 struct chipc_region *cr; 1018 bhnd_size_t cr_offset; 1019 rman_res_t r_start, r_end, r_size; 1020 int error; 1021 1022 rm = chipc_get_rman(sc, type); 1023 if (rm == NULL || !rman_is_region_manager(r, rm)) 1024 return (EINVAL); 1025 1026 r_start = rman_get_start(r); 1027 r_end = rman_get_end(r); 1028 r_size = rman_get_size(r); 1029 1030 /* Find the corresponding chipc region */ 1031 cr = chipc_find_region(sc, r_start, r_end); 1032 if (cr == NULL) 1033 return (EINVAL); 1034 1035 /* Calculate subregion offset within the chipc region */ 1036 cr_offset = r_start - cr->cr_addr; 1037 1038 /* Retain (and activate, if necessary) the chipc region */ 1039 if ((error = chipc_retain_region(sc, cr, RF_ACTIVE))) 1040 return (error); 1041 1042 /* Configure child resource with its subregion values. */ 1043 if (cr->cr_res->direct) { 1044 error = chipc_init_child_resource(r, cr->cr_res->res, 1045 cr_offset, r_size); 1046 if (error) 1047 goto cleanup; 1048 1049 /* Mark active */ 1050 if ((error = rman_activate_resource(r))) 1051 goto cleanup; 1052 } else if (req_direct) { 1053 error = ENOMEM; 1054 goto cleanup; 1055 } 1056 1057 return (0); 1058 1059cleanup: 1060 chipc_release_region(sc, cr, RF_ACTIVE); 1061 return (error); 1062} 1063 1064static int 1065chipc_activate_bhnd_resource(device_t dev, device_t child, int type, 1066 int rid, struct bhnd_resource *r) 1067{ 1068 struct chipc_softc *sc; 1069 struct rman *rm; 1070 int error; 1071 1072 sc = device_get_softc(dev); 1073 1074 /* Delegate non-locally managed resources to parent */ 1075 rm = chipc_get_rman(sc, type); 1076 if (rm == NULL || !rman_is_region_manager(r->res, rm)) { 1077 return (bhnd_bus_generic_activate_resource(dev, child, type, 1078 rid, r)); 1079 } 1080 1081 /* Try activating the chipc region resource */ 1082 error = chipc_try_activate_resource(sc, child, type, rid, r->res, 1083 false); 1084 if (error) 1085 return (error); 1086 1087 /* Mark the child resource as direct according to the returned resource 1088 * state */ 1089 if (rman_get_flags(r->res) & RF_ACTIVE) 1090 r->direct = true; 1091 1092 return (0); 1093} 1094 1095static int 1096chipc_activate_resource(device_t dev, device_t child, int type, int rid, 1097 struct resource *r) 1098{ 1099 struct chipc_softc *sc; 1100 struct rman *rm; 1101 1102 sc = device_get_softc(dev); 1103 1104 /* Delegate non-locally managed resources to parent */ 1105 rm = chipc_get_rman(sc, type); 1106 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1107 return (bus_generic_activate_resource(dev, child, type, rid, 1108 r)); 1109 } 1110 1111 /* Try activating the chipc region-based resource */ 1112 return (chipc_try_activate_resource(sc, child, type, rid, r, true)); 1113} 1114 1115/** 1116 * Default bhndb(4) implementation of BUS_DEACTIVATE_RESOURCE(). 1117 */ 1118static int 1119chipc_deactivate_resource(device_t dev, device_t child, int type, 1120 int rid, struct resource *r) 1121{ 1122 struct chipc_softc *sc; 1123 struct chipc_region *cr; 1124 struct rman *rm; 1125 int error; 1126 1127 sc = device_get_softc(dev); 1128 1129 /* Handled by parent bus? */ 1130 rm = chipc_get_rman(sc, type); 1131 if (rm == NULL || !rman_is_region_manager(r, rm)) { 1132 return (bus_generic_deactivate_resource(dev, child, type, rid, 1133 r)); 1134 } 1135 1136 /* Find the corresponding chipc region */ 1137 cr = chipc_find_region(sc, rman_get_start(r), rman_get_end(r)); 1138 if (cr == NULL) 1139 return (EINVAL); 1140 1141 /* Mark inactive */ 1142 if ((error = rman_deactivate_resource(r))) 1143 return (error); 1144 1145 /* Drop associated RF_ACTIVE reference */ 1146 chipc_release_region(sc, cr, RF_ACTIVE); 1147 1148 return (0); 1149} 1150 1151/** 1152 * Examine bus state and make a best effort determination of whether it's 1153 * likely safe to enable the muxed SPROM pins. 1154 * 1155 * On devices that do not use SPROM pin muxing, always returns true. 1156 * 1157 * @param sc chipc driver state. 1158 */ 1159static bool 1160chipc_should_enable_muxed_sprom(struct chipc_softc *sc) 1161{ 1162 device_t *devs; 1163 device_t hostb; 1164 device_t parent; 1165 int devcount; 1166 int error; 1167 bool result; 1168 1169 /* Nothing to do? */ 1170 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1171 return (true); 1172 1173 mtx_lock(&Giant); /* for newbus */ 1174 1175 parent = device_get_parent(sc->dev); 1176 hostb = bhnd_bus_find_hostb_device(parent); 1177 1178 if ((error = device_get_children(parent, &devs, &devcount))) { 1179 mtx_unlock(&Giant); 1180 return (false); 1181 } 1182 1183 /* Reject any active devices other than ChipCommon, or the 1184 * host bridge (if any). */ 1185 result = true; 1186 for (int i = 0; i < devcount; i++) { 1187 if (devs[i] == hostb || devs[i] == sc->dev) 1188 continue; 1189 1190 if (!device_is_attached(devs[i])) 1191 continue; 1192 1193 if (device_is_suspended(devs[i])) 1194 continue; 1195 1196 /* Active device; assume SPROM is busy */ 1197 result = false; 1198 break; 1199 } 1200 1201 free(devs, M_TEMP); 1202 mtx_unlock(&Giant); 1203 return (result); 1204} 1205 1206static int 1207chipc_enable_sprom(device_t dev) 1208{ 1209 struct chipc_softc *sc; 1210 int error; 1211 1212 sc = device_get_softc(dev); 1213 CHIPC_LOCK(sc); 1214 1215 /* Already enabled? */ 1216 if (sc->sprom_refcnt >= 1) { 1217 sc->sprom_refcnt++; 1218 CHIPC_UNLOCK(sc); 1219 1220 return (0); 1221 } 1222 1223 switch (sc->caps.nvram_src) { 1224 case BHND_NVRAM_SRC_SPROM: 1225 error = chipc_enable_sprom_pins(sc); 1226 break; 1227 case BHND_NVRAM_SRC_OTP: 1228 error = chipc_enable_otp_power(sc); 1229 break; 1230 default: 1231 error = 0; 1232 break; 1233 } 1234 1235 /* Bump the reference count */ 1236 if (error == 0) 1237 sc->sprom_refcnt++; 1238 1239 CHIPC_UNLOCK(sc); 1240 return (error); 1241} 1242 1243static void 1244chipc_disable_sprom(device_t dev) 1245{ 1246 struct chipc_softc *sc; 1247 1248 sc = device_get_softc(dev); 1249 CHIPC_LOCK(sc); 1250 1251 /* Check reference count, skip disable if in-use. */ 1252 KASSERT(sc->sprom_refcnt > 0, ("sprom refcnt overrelease")); 1253 sc->sprom_refcnt--; 1254 if (sc->sprom_refcnt > 0) { 1255 CHIPC_UNLOCK(sc); 1256 return; 1257 } 1258 1259 switch (sc->caps.nvram_src) { 1260 case BHND_NVRAM_SRC_SPROM: 1261 chipc_disable_sprom_pins(sc); 1262 break; 1263 case BHND_NVRAM_SRC_OTP: 1264 chipc_disable_otp_power(sc); 1265 break; 1266 default: 1267 break; 1268 } 1269 1270 1271 CHIPC_UNLOCK(sc); 1272} 1273 1274static int 1275chipc_enable_otp_power(struct chipc_softc *sc) 1276{ 1277 // TODO: Enable OTP resource via PMU, and wait up to 100 usec for 1278 // OTPS_READY to be set in `optstatus`. 1279 return (0); 1280} 1281 1282static void 1283chipc_disable_otp_power(struct chipc_softc *sc) 1284{ 1285 // TODO: Disable OTP resource via PMU 1286} 1287 1288/** 1289 * If required by this device, enable access to the SPROM. 1290 * 1291 * @param sc chipc driver state. 1292 */ 1293static int 1294chipc_enable_sprom_pins(struct chipc_softc *sc) 1295{ 1296 uint32_t cctrl; 1297 1298 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1299 KASSERT(sc->sprom_refcnt == 0, ("sprom pins already enabled")); 1300 1301 /* Nothing to do? */ 1302 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1303 return (0); 1304 1305 /* Check whether bus is busy */ 1306 if (!chipc_should_enable_muxed_sprom(sc)) 1307 return (EBUSY); 1308 1309 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1310 1311 /* 4331 devices */ 1312 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1313 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN; 1314 1315 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1316 cctrl &= ~CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1317 1318 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1319 cctrl &= ~CHIPC_CCTRL4331_EXTPA_EN2; 1320 1321 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1322 return (0); 1323 } 1324 1325 /* 4360 devices */ 1326 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1327 /* Unimplemented */ 1328 } 1329 1330 /* Refuse to proceed on unsupported devices with muxed SPROM pins */ 1331 device_printf(sc->dev, "muxed sprom lines on unrecognized device\n"); 1332 return (ENXIO); 1333} 1334 1335/** 1336 * If required by this device, revert any GPIO/pin configuration applied 1337 * to allow SPROM access. 1338 * 1339 * @param sc chipc driver state. 1340 */ 1341static void 1342chipc_disable_sprom_pins(struct chipc_softc *sc) 1343{ 1344 uint32_t cctrl; 1345 1346 /* Nothing to do? */ 1347 if (!CHIPC_QUIRK(sc, MUX_SPROM)) 1348 return; 1349 1350 CHIPC_LOCK_ASSERT(sc, MA_OWNED); 1351 KASSERT(sc->sprom_refcnt == 0, ("sprom pins in use")); 1352 1353 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1354 1355 /* 4331 devices */ 1356 if (CHIPC_QUIRK(sc, 4331_EXTPA_MUX_SPROM)) { 1357 cctrl |= CHIPC_CCTRL4331_EXTPA_EN; 1358 1359 if (CHIPC_QUIRK(sc, 4331_GPIO2_5_MUX_SPROM)) 1360 cctrl |= CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5; 1361 1362 if (CHIPC_QUIRK(sc, 4331_EXTPA2_MUX_SPROM)) 1363 cctrl |= CHIPC_CCTRL4331_EXTPA_EN2; 1364 1365 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1366 return; 1367 } 1368 1369 /* 4360 devices */ 1370 if (CHIPC_QUIRK(sc, 4360_FEM_MUX_SPROM)) { 1371 /* Unimplemented */ 1372 } 1373} 1374 1375static uint32_t 1376chipc_read_chipst(device_t dev) 1377{ 1378 struct chipc_softc *sc = device_get_softc(dev); 1379 return (bhnd_bus_read_4(sc->core, CHIPC_CHIPST)); 1380} 1381 1382static void 1383chipc_write_chipctrl(device_t dev, uint32_t value, uint32_t mask) 1384{ 1385 struct chipc_softc *sc; 1386 uint32_t cctrl; 1387 1388 sc = device_get_softc(dev); 1389 1390 CHIPC_LOCK(sc); 1391 1392 cctrl = bhnd_bus_read_4(sc->core, CHIPC_CHIPCTRL); 1393 cctrl = (cctrl & ~mask) | (value | mask); 1394 bhnd_bus_write_4(sc->core, CHIPC_CHIPCTRL, cctrl); 1395 1396 CHIPC_UNLOCK(sc); 1397} 1398 1399static struct chipc_caps * 1400chipc_get_caps(device_t dev) 1401{ 1402 struct chipc_softc *sc; 1403 1404 sc = device_get_softc(dev); 1405 return (&sc->caps); 1406} 1407 1408static device_method_t chipc_methods[] = { 1409 /* Device interface */ 1410 DEVMETHOD(device_probe, chipc_probe), 1411 DEVMETHOD(device_attach, chipc_attach), 1412 DEVMETHOD(device_detach, chipc_detach), 1413 DEVMETHOD(device_suspend, chipc_suspend), 1414 DEVMETHOD(device_resume, chipc_resume), 1415 1416 /* Bus interface */ 1417 DEVMETHOD(bus_probe_nomatch, chipc_probe_nomatch), 1418 DEVMETHOD(bus_print_child, chipc_print_child), 1419 DEVMETHOD(bus_child_pnpinfo_str, chipc_child_pnpinfo_str), 1420 DEVMETHOD(bus_child_location_str, chipc_child_location_str), 1421 1422 DEVMETHOD(bus_add_child, chipc_add_child), 1423 DEVMETHOD(bus_child_deleted, chipc_child_deleted), 1424 1425 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource), 1426 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource), 1427 DEVMETHOD(bus_delete_resource, bus_generic_rl_delete_resource), 1428 DEVMETHOD(bus_alloc_resource, chipc_alloc_resource), 1429 DEVMETHOD(bus_release_resource, chipc_release_resource), 1430 DEVMETHOD(bus_adjust_resource, chipc_adjust_resource), 1431 DEVMETHOD(bus_activate_resource, chipc_activate_resource), 1432 DEVMETHOD(bus_deactivate_resource, chipc_deactivate_resource), 1433 DEVMETHOD(bus_get_resource_list, chipc_get_resource_list), 1434 1435 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 1436 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 1437 DEVMETHOD(bus_config_intr, bus_generic_config_intr), 1438 DEVMETHOD(bus_bind_intr, bus_generic_bind_intr), 1439 DEVMETHOD(bus_describe_intr, bus_generic_describe_intr), 1440 1441 /* BHND bus inteface */ 1442 DEVMETHOD(bhnd_bus_activate_resource, chipc_activate_bhnd_resource), 1443 1444 /* ChipCommon interface */ 1445 DEVMETHOD(bhnd_chipc_read_chipst, chipc_read_chipst), 1446 DEVMETHOD(bhnd_chipc_write_chipctrl, chipc_write_chipctrl), 1447 DEVMETHOD(bhnd_chipc_enable_sprom, chipc_enable_sprom), 1448 DEVMETHOD(bhnd_chipc_disable_sprom, chipc_disable_sprom), 1449 DEVMETHOD(bhnd_chipc_get_caps, chipc_get_caps), 1450 1451 DEVMETHOD_END 1452}; 1453 1454DEFINE_CLASS_0(bhnd_chipc, bhnd_chipc_driver, chipc_methods, sizeof(struct chipc_softc)); 1455EARLY_DRIVER_MODULE(bhnd_chipc, bhnd, bhnd_chipc_driver, bhnd_chipc_devclass, 0, 0, 1456 BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE); 1457MODULE_DEPEND(bhnd_chipc, bhnd, 1, 1, 1); 1458MODULE_VERSION(bhnd_chipc, 1); 1459