1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 1998 - 2008 S��ren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD$"); 31 32#include <sys/param.h> 33#include <sys/module.h> 34#include <sys/systm.h> 35#include <sys/kernel.h> 36#include <sys/ata.h> 37#include <sys/bus.h> 38#include <sys/endian.h> 39#include <sys/malloc.h> 40#include <sys/lock.h> 41#include <sys/mutex.h> 42#include <sys/sema.h> 43#include <sys/taskqueue.h> 44#include <vm/uma.h> 45#include <machine/stdarg.h> 46#include <machine/resource.h> 47#include <machine/bus.h> 48#include <sys/rman.h> 49#include <dev/pci/pcivar.h> 50#include <dev/pci/pcireg.h> 51#include <dev/ata/ata-all.h> 52#include <dev/ata/ata-pci.h> 53#include <ata_if.h> 54 55/* local prototypes */ 56static int ata_ite_chipinit(device_t dev); 57static int ata_ite_ch_attach(device_t dev); 58static int ata_ite_821x_setmode(device_t dev, int target, int mode); 59static int ata_ite_8213_setmode(device_t dev, int target, int mode); 60 61/* 62 * Integrated Technology Express Inc. (ITE) chipset support functions 63 */ 64static int 65ata_ite_probe(device_t dev) 66{ 67 struct ata_pci_controller *ctlr = device_get_softc(dev); 68 static const struct ata_chip_id ids[] = 69 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" }, 70 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 71 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 72 { 0, 0, 0, 0, 0, 0}}; 73 74 if (pci_get_vendor(dev) != ATA_ITE_ID) 75 return ENXIO; 76 77 if (!(ctlr->chip = ata_match_chip(dev, ids))) 78 return ENXIO; 79 80 ata_set_desc(dev); 81 ctlr->chipinit = ata_ite_chipinit; 82 return (BUS_PROBE_LOW_PRIORITY); 83} 84 85static int 86ata_ite_chipinit(device_t dev) 87{ 88 struct ata_pci_controller *ctlr = device_get_softc(dev); 89 90 if (ata_setup_interrupt(dev, ata_generic_intr)) 91 return ENXIO; 92 93 if (ctlr->chip->chipid == ATA_IT8213F) { 94 /* the ITE 8213F only has one channel */ 95 ctlr->channels = 1; 96 97 ctlr->setmode = ata_ite_8213_setmode; 98 } 99 else { 100 /* set PCI mode and 66Mhz reference clock */ 101 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 102 103 /* set default active & recover timings */ 104 pci_write_config(dev, 0x54, 0x31, 1); 105 pci_write_config(dev, 0x56, 0x31, 1); 106 107 ctlr->setmode = ata_ite_821x_setmode; 108 /* No timing restrictions initially. */ 109 ctlr->chipset_data = NULL; 110 } 111 ctlr->ch_attach = ata_ite_ch_attach; 112 return (0); 113} 114 115static int 116ata_ite_ch_attach(device_t dev) 117{ 118 struct ata_channel *ch = device_get_softc(dev); 119 int error; 120 121 error = ata_pci_ch_attach(dev); 122 ch->flags |= ATA_CHECKS_CABLE; 123 ch->flags |= ATA_NO_ATAPI_DMA; 124 return (error); 125} 126 127static int 128ata_ite_821x_setmode(device_t dev, int target, int mode) 129{ 130 device_t parent = device_get_parent(dev); 131 struct ata_pci_controller *ctlr = device_get_softc(parent); 132 struct ata_channel *ch = device_get_softc(dev); 133 int devno = (ch->unit << 1) + target; 134 int piomode; 135 uint8_t *timings = (uint8_t*)(&ctlr->chipset_data); 136 static const uint8_t udmatiming[] = 137 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 138 static const uint8_t chtiming[] = 139 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 140 141 mode = min(mode, ctlr->chip->max_dma); 142 /* check the CBLID bits for 80 conductor cable detection */ 143 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 144 (pci_read_config(parent, 0x40, 2) & 145 (ch->unit ? (1<<3) : (1<<2)))) { 146 ata_print_cable(dev, "controller"); 147 mode = ATA_UDMA2; 148 } 149 if (mode >= ATA_UDMA0) { 150 /* enable UDMA mode */ 151 pci_write_config(parent, 0x50, 152 pci_read_config(parent, 0x50, 1) & 153 ~(1 << (devno + 3)), 1); 154 /* set UDMA timing */ 155 pci_write_config(parent, 156 0x56 + (ch->unit << 2) + target, 157 udmatiming[mode & ATA_MODE_MASK], 1); 158 piomode = ATA_PIO4; 159 } else { 160 /* disable UDMA mode */ 161 pci_write_config(parent, 0x50, 162 pci_read_config(parent, 0x50, 1) | 163 (1 << (devno + 3)), 1); 164 piomode = mode; 165 } 166 timings[devno] = chtiming[ata_mode2idx(piomode)]; 167 /* set active and recover timing (shared between master & slave) */ 168 pci_write_config(parent, 0x54 + (ch->unit << 2), 169 max(timings[ch->unit << 1], timings[(ch->unit << 1) + 1]), 1); 170 return (mode); 171} 172 173static int 174ata_ite_8213_setmode(device_t dev, int target, int mode) 175{ 176 device_t parent = device_get_parent(dev); 177 struct ata_pci_controller *ctlr = device_get_softc(parent); 178 int piomode; 179 u_int16_t reg40 = pci_read_config(parent, 0x40, 2); 180 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 181 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 182 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 183 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 184 u_int16_t mask40 = 0, new40 = 0; 185 u_int8_t mask44 = 0, new44 = 0; 186 static const uint8_t timings[] = 187 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 188 static const uint8_t utimings[] = 189 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 190 191 mode = min(mode, ctlr->chip->max_dma); 192 193 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 194 !(reg54 & (0x10 << target))) { 195 ata_print_cable(dev, "controller"); 196 mode = ATA_UDMA2; 197 } 198 /* Enable/disable UDMA and set timings. */ 199 if (mode >= ATA_UDMA0) { 200 pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2); 201 pci_write_config(parent, 0x4a, 202 (reg4a & ~(0x3 << (target << 2))) | 203 (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2); 204 piomode = ATA_PIO4; 205 } else { 206 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2); 207 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2); 208 piomode = mode; 209 } 210 /* Set UDMA reference clock (33/66/133MHz). */ 211 reg54 &= ~(0x1001 << target); 212 if (mode >= ATA_UDMA5) 213 reg54 |= (0x1000 << target); 214 else if (mode >= ATA_UDMA3) 215 reg54 |= (0x1 << target); 216 pci_write_config(parent, 0x54, reg54, 2); 217 /* Allow PIO/WDMA timing controls. */ 218 reg40 &= 0xff00; 219 reg40 |= 0x4033; 220 /* Set PIO/WDMA timings. */ 221 if (target == 0) { 222 reg40 |= (ata_atapi(dev, target) ? 0x04 : 0x00); 223 mask40 = 0x3300; 224 new40 = timings[ata_mode2idx(piomode)] << 8; 225 } 226 else { 227 reg40 |= (ata_atapi(dev, target) ? 0x40 : 0x00); 228 mask44 = 0x0f; 229 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 230 (timings[ata_mode2idx(piomode)] & 0x03); 231 } 232 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 233 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 234 return (mode); 235} 236 237ATA_DECLARE_DRIVER(ata_ite); 238