1/*- 2 * Core definitions and data structures shareable across OS platforms. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 * 6 * Copyright (c) 1994-2002 Justin T. Gibbs. 7 * Copyright (c) 2000-2002 Adaptec Inc. 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions, and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * substantially similar to the "NO WARRANTY" disclaimer below 18 * ("Disclaimer") and any redistribution must be conditioned upon 19 * including a substantially similar Disclaimer requirement for further 20 * binary redistribution. 21 * 3. Neither the names of the above-listed copyright holders nor the names 22 * of any contributors may be used to endorse or promote products derived 23 * from this software without specific prior written permission. 24 * 25 * Alternatively, this software may be distributed under the terms of the 26 * GNU General Public License ("GPL") version 2 as published by the Free 27 * Software Foundation. 28 * 29 * NO WARRANTY 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 31 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 32 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR 33 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 34 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 36 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 38 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING 39 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 40 * POSSIBILITY OF SUCH DAMAGES. 41 * 42 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#107 $ 43 * 44 * $FreeBSD$ 45 */ 46 47#ifndef _AIC79XX_H_ 48#define _AIC79XX_H_ 49 50/* Register Definitions */ 51#include "aic79xx_reg.h" 52 53/************************* Forward Declarations *******************************/ 54struct ahd_platform_data; 55struct scb_platform_data; 56 57/****************************** Useful Macros *********************************/ 58#ifndef MAX 59#define MAX(a,b) (((a) > (b)) ? (a) : (b)) 60#endif 61 62#ifndef MIN 63#define MIN(a,b) (((a) < (b)) ? (a) : (b)) 64#endif 65 66#ifndef TRUE 67#define TRUE 1 68#endif 69#ifndef FALSE 70#define FALSE 0 71#endif 72 73#define NUM_ELEMENTS(array) (sizeof(array) / sizeof(*array)) 74 75#define ALL_CHANNELS '\0' 76#define ALL_TARGETS_MASK 0xFFFF 77#define INITIATOR_WILDCARD (~0) 78#define SCB_LIST_NULL 0xFF00 79#define SCB_LIST_NULL_LE (aic_htole16(SCB_LIST_NULL)) 80#define QOUTFIFO_ENTRY_VALID 0x80 81#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL) 82 83#define SCSIID_TARGET(ahd, scsiid) \ 84 (((scsiid) & TID) >> TID_SHIFT) 85#define SCSIID_OUR_ID(scsiid) \ 86 ((scsiid) & OID) 87#define SCSIID_CHANNEL(ahd, scsiid) ('A') 88#define SCB_IS_SCSIBUS_B(ahd, scb) (0) 89#define SCB_GET_OUR_ID(scb) \ 90 SCSIID_OUR_ID((scb)->hscb->scsiid) 91#define SCB_GET_TARGET(ahd, scb) \ 92 SCSIID_TARGET((ahd), (scb)->hscb->scsiid) 93#define SCB_GET_CHANNEL(ahd, scb) \ 94 SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid) 95#define SCB_GET_LUN(scb) \ 96 ((scb)->hscb->lun) 97#define SCB_GET_TARGET_OFFSET(ahd, scb) \ 98 SCB_GET_TARGET(ahd, scb) 99#define SCB_GET_TARGET_MASK(ahd, scb) \ 100 (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb))) 101#ifdef AHD_DEBUG 102#define SCB_IS_SILENT(scb) \ 103 ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0 \ 104 && (((scb)->flags & SCB_SILENT) != 0)) 105#else 106#define SCB_IS_SILENT(scb) \ 107 (((scb)->flags & SCB_SILENT) != 0) 108#endif 109/* 110 * TCLs have the following format: TTTTLLLLLLLL 111 */ 112#define TCL_TARGET_OFFSET(tcl) \ 113 ((((tcl) >> 4) & TID) >> 4) 114#define TCL_LUN(tcl) \ 115 (tcl & (AHD_NUM_LUNS - 1)) 116#define BUILD_TCL(scsiid, lun) \ 117 ((lun) | (((scsiid) & TID) << 4)) 118#define BUILD_TCL_RAW(target, channel, lun) \ 119 ((lun) | ((target) << 8)) 120 121#define SCB_GET_TAG(scb) \ 122 aic_le16toh(scb->hscb->tag) 123 124#ifndef AHD_TARGET_MODE 125#undef AHD_TMODE_ENABLE 126#define AHD_TMODE_ENABLE 0 127#endif 128 129#define AHD_BUILD_COL_IDX(target, lun) \ 130 (((lun) << 4) | target) 131 132#define AHD_GET_SCB_COL_IDX(ahd, scb) \ 133 ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb)) 134 135#define AHD_SET_SCB_COL_IDX(scb, col_idx) \ 136do { \ 137 (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID; \ 138 (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1); \ 139} while (0) 140 141#define AHD_COPY_SCB_COL_IDX(dst, src) \ 142do { \ 143 dst->hscb->scsiid = src->hscb->scsiid; \ 144 dst->hscb->lun = src->hscb->lun; \ 145} while (0) 146 147#define AHD_NEVER_COL_IDX 0xFFFF 148 149/**************************** Driver Constants ********************************/ 150/* 151 * The maximum number of supported targets. 152 */ 153#define AHD_NUM_TARGETS 16 154 155/* 156 * The maximum number of supported luns. 157 * The identify message only supports 64 luns in non-packetized transfers. 158 * You can have 2^64 luns when information unit transfers are enabled, 159 * but until we see a need to support that many, we support 256. 160 */ 161#define AHD_NUM_LUNS_NONPKT 64 162#define AHD_NUM_LUNS 256 163 164/* 165 * The maximum transfer per S/G segment. 166 */ 167#define AHD_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */ 168 169/* 170 * The maximum amount of SCB storage in hardware on a controller. 171 * This value represents an upper bound. Due to software design, 172 * we may not be able to use this number. 173 */ 174#define AHD_SCB_MAX 512 175 176/* 177 * The maximum number of concurrent transactions supported per driver instance. 178 * Sequencer Control Blocks (SCBs) store per-transaction information. 179 */ 180#define AHD_MAX_QUEUE AHD_SCB_MAX 181 182/* 183 * Define the size of our QIN and QOUT FIFOs. They must be a power of 2 184 * in size and accommodate as many transactions as can be queued concurrently. 185 */ 186#define AHD_QIN_SIZE AHD_MAX_QUEUE 187#define AHD_QOUT_SIZE AHD_MAX_QUEUE 188 189#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1)) 190/* 191 * The maximum amount of SCB storage we allocate in host memory. 192 */ 193#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE 194 195/* 196 * Ring Buffer of incoming target commands. 197 * We allocate 256 to simplify the logic in the sequencer 198 * by using the natural wrap point of an 8bit counter. 199 */ 200#define AHD_TMODE_CMDS 256 201 202/* Reset line assertion time in us */ 203#define AHD_BUSRESET_DELAY 25 204 205/******************* Chip Characteristics/Operating Settings *****************/ 206extern uint32_t ahd_attach_to_HostRAID_controllers; 207 208/* 209 * Chip Type 210 * The chip order is from least sophisticated to most sophisticated. 211 */ 212typedef enum { 213 AHD_NONE = 0x0000, 214 AHD_CHIPID_MASK = 0x00FF, 215 AHD_AIC7901 = 0x0001, 216 AHD_AIC7902 = 0x0002, 217 AHD_AIC7901A = 0x0003, 218 AHD_PCI = 0x0100, /* Bus type PCI */ 219 AHD_PCIX = 0x0200, /* Bus type PCIX */ 220 AHD_BUS_MASK = 0x0F00 221} ahd_chip; 222 223/* 224 * Features available in each chip type. 225 */ 226typedef enum { 227 AHD_FENONE = 0x00000, 228 AHD_WIDE = 0x00001,/* Wide Channel */ 229 AHD_MULTI_FUNC = 0x00100,/* Multi-Function/Channel Device */ 230 AHD_TARGETMODE = 0x01000,/* Has tested target mode support */ 231 AHD_MULTIROLE = 0x02000,/* Space for two roles at a time */ 232 AHD_RTI = 0x04000,/* Retained Training Support */ 233 AHD_NEW_IOCELL_OPTS = 0x08000,/* More Signal knobs in the IOCELL */ 234 AHD_NEW_DFCNTRL_OPTS = 0x10000,/* SCSIENWRDIS bit */ 235 AHD_FAST_CDB_DELIVERY = 0x20000,/* CDB acks released to Output Sync */ 236 AHD_REMOVABLE = 0x00000,/* Hot-Swap supported - None so far*/ 237 AHD_AIC7901_FE = AHD_FENONE, 238 AHD_AIC7901A_FE = AHD_FENONE, 239 AHD_AIC7902_FE = AHD_MULTI_FUNC 240} ahd_feature; 241 242/* 243 * Bugs in the silicon that we work around in software. 244 */ 245typedef enum { 246 AHD_BUGNONE = 0x0000, 247 /* 248 * Rev A hardware fails to update LAST/CURR/NEXTSCB 249 * correctly in certain packetized selection cases. 250 */ 251 AHD_SENT_SCB_UPDATE_BUG = 0x0001, 252 /* The wrong SCB is accessed to check the abort pending bit. */ 253 AHD_ABORT_LQI_BUG = 0x0002, 254 /* Packetized bitbucket crosses packet boundaries. */ 255 AHD_PKT_BITBUCKET_BUG = 0x0004, 256 /* The selection timer runs twice as long as its setting. */ 257 AHD_LONG_SETIMO_BUG = 0x0008, 258 /* The Non-LQ CRC error status is delayed until phase change. */ 259 AHD_NLQICRC_DELAYED_BUG = 0x0010, 260 /* The chip must be reset for all outgoing bus resets. */ 261 AHD_SCSIRST_BUG = 0x0020, 262 /* Some PCIX fields must be saved and restored across chip reset. */ 263 AHD_PCIX_CHIPRST_BUG = 0x0040, 264 /* MMAPIO is not functional in PCI-X mode. */ 265 AHD_PCIX_MMAPIO_BUG = 0x0080, 266 /* Reads to SCBRAM fail to reset the discard timer. */ 267 AHD_PCIX_SCBRAM_RD_BUG = 0x0100, 268 /* Bug workarounds that can be disabled on non-PCIX busses. */ 269 AHD_PCIX_BUG_MASK = AHD_PCIX_CHIPRST_BUG 270 | AHD_PCIX_MMAPIO_BUG 271 | AHD_PCIX_SCBRAM_RD_BUG, 272 /* 273 * LQOSTOP0 status set even for forced selections with ATN 274 * to perform non-packetized message delivery. 275 */ 276 AHD_LQO_ATNO_BUG = 0x0200, 277 /* FIFO auto-flush does not always trigger. */ 278 AHD_AUTOFLUSH_BUG = 0x0400, 279 /* The CLRLQO registers are not self-clearing. */ 280 AHD_CLRLQO_AUTOCLR_BUG = 0x0800, 281 /* The PACKETIZED status bit refers to the previous connection. */ 282 AHD_PKTIZED_STATUS_BUG = 0x1000, 283 /* "Short Luns" are not placed into outgoing LQ packets correctly. */ 284 AHD_PKT_LUN_BUG = 0x2000, 285 /* 286 * Only the FIFO allocated to the non-packetized connection may 287 * be in use during a non-packetzied connection. 288 */ 289 AHD_NONPACKFIFO_BUG = 0x4000, 290 /* 291 * Writing to a DFF SCBPTR register may fail if concurent with 292 * a hardware write to the other DFF SCBPTR register. This is 293 * not currently a concern in our sequencer since all chips with 294 * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern 295 * occur in non-packetized connections. 296 */ 297 AHD_MDFF_WSCBPTR_BUG = 0x8000, 298 /* SGHADDR updates are slow. */ 299 AHD_REG_SLOW_SETTLE_BUG = 0x10000, 300 /* 301 * Changing the MODE_PTR coincident with an interrupt that 302 * switches to a different mode will cause the interrupt to 303 * be in the mode written outside of interrupt context. 304 */ 305 AHD_SET_MODE_BUG = 0x20000, 306 /* Non-packetized busfree revision does not work. */ 307 AHD_BUSFREEREV_BUG = 0x40000, 308 /* 309 * Paced transfers are indicated with a non-standard PPR 310 * option bit in the neg table, 160MHz is indicated by 311 * sync factor 0x7, and the offset if off by a factor of 2. 312 */ 313 AHD_PACED_NEGTABLE_BUG = 0x80000, 314 /* LQOOVERRUN false positives. */ 315 AHD_LQOOVERRUN_BUG = 0x100000, 316 /* 317 * Controller write to INTSTAT will lose to a host 318 * write to CLRINT. 319 */ 320 AHD_INTCOLLISION_BUG = 0x200000, 321 /* 322 * The GEM318 violates the SCSI spec by not waiting 323 * the mandated bus settle delay between phase changes 324 * in some situations. Some aic79xx chip revs. are more 325 * strict in this regard and will treat REQ assertions 326 * that fall within the bus settle delay window as 327 * glitches. This flag tells the firmware to tolerate 328 * early REQ assertions. 329 */ 330 AHD_EARLY_REQ_BUG = 0x400000, 331 /* 332 * The LED does not stay on long enough in packetized modes. 333 */ 334 AHD_FAINT_LED_BUG = 0x800000 335} ahd_bug; 336 337/* 338 * Configuration specific settings. 339 * The driver determines these settings by probing the 340 * chip/controller's configuration. 341 */ 342typedef enum { 343 AHD_FNONE = 0x00000, 344 AHD_BOOT_CHANNEL = 0x00001,/* We were set as the boot channel. */ 345 AHD_USEDEFAULTS = 0x00004,/* 346 * For cards without an seeprom 347 * or a BIOS to initialize the chip's 348 * SRAM, we use the default target 349 * settings. 350 */ 351 AHD_SEQUENCER_DEBUG = 0x00008, 352 AHD_RESET_BUS_A = 0x00010, 353 AHD_EXTENDED_TRANS_A = 0x00020, 354 AHD_TERM_ENB_A = 0x00040, 355 AHD_SPCHK_ENB_A = 0x00080, 356 AHD_STPWLEVEL_A = 0x00100, 357 AHD_INITIATORROLE = 0x00200,/* 358 * Allow initiator operations on 359 * this controller. 360 */ 361 AHD_TARGETROLE = 0x00400,/* 362 * Allow target operations on this 363 * controller. 364 */ 365 AHD_RESOURCE_SHORTAGE = 0x00800, 366 AHD_TQINFIFO_BLOCKED = 0x01000,/* Blocked waiting for ATIOs */ 367 AHD_INT50_SPEEDFLEX = 0x02000,/* 368 * Internal 50pin connector 369 * sits behind an aic3860 370 */ 371 AHD_BIOS_ENABLED = 0x04000, 372 AHD_ALL_INTERRUPTS = 0x08000, 373 AHD_39BIT_ADDRESSING = 0x10000,/* Use 39 bit addressing scheme. */ 374 AHD_64BIT_ADDRESSING = 0x20000,/* Use 64 bit addressing scheme. */ 375 AHD_CURRENT_SENSING = 0x40000, 376 AHD_SCB_CONFIG_USED = 0x80000,/* No SEEPROM but SCB had info. */ 377 AHD_HP_BOARD = 0x100000, 378 AHD_RESET_POLL_ACTIVE = 0x200000, 379 AHD_UPDATE_PEND_CMDS = 0x400000, 380 AHD_RUNNING_QOUTFIFO = 0x800000, 381 AHD_HAD_FIRST_SEL = 0x1000000, 382 AHD_SHUTDOWN_RECOVERY = 0x2000000, /* Terminate recovery thread. */ 383 AHD_HOSTRAID_BOARD = 0x4000000 384} ahd_flag; 385 386/************************* Hardware SCB Definition ***************************/ 387 388/* 389 * The driver keeps up to MAX_SCB scb structures per card in memory. The SCB 390 * consists of a "hardware SCB" mirroring the fields available on the card 391 * and additional information the kernel stores for each transaction. 392 * 393 * To minimize space utilization, a portion of the hardware scb stores 394 * different data during different portions of a SCSI transaction. 395 * As initialized by the host driver for the initiator role, this area 396 * contains the SCSI cdb (or a pointer to the cdb) to be executed. After 397 * the cdb has been presented to the target, this area serves to store 398 * residual transfer information and the SCSI status byte. 399 * For the target role, the contents of this area do not change, but 400 * still serve a different purpose than for the initiator role. See 401 * struct target_data for details. 402 */ 403 404/* 405 * Status information embedded in the shared poriton of 406 * an SCB after passing the cdb to the target. The kernel 407 * driver will only read this data for transactions that 408 * complete abnormally. 409 */ 410struct initiator_status { 411 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 412 uint32_t residual_sgptr; /* The next S/G for this transfer */ 413 uint8_t scsi_status; /* Standard SCSI status byte */ 414}; 415 416struct target_status { 417 uint32_t residual_datacnt; /* Residual in the current S/G seg */ 418 uint32_t residual_sgptr; /* The next S/G for this transfer */ 419 uint8_t scsi_status; /* SCSI status to give to initiator */ 420 uint8_t target_phases; /* Bitmap of phases to execute */ 421 uint8_t data_phase; /* Data-In or Data-Out */ 422 uint8_t initiator_tag; /* Initiator's transaction tag */ 423}; 424 425/* 426 * Initiator mode SCB shared data area. 427 * If the embedded CDB is 12 bytes or less, we embed 428 * the sense buffer address in the SCB. This allows 429 * us to retrieve sense information without interrupting 430 * the host in packetized mode. 431 */ 432typedef uint32_t sense_addr_t; 433#define MAX_CDB_LEN 16 434#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t)) 435union initiator_data { 436 struct { 437 uint64_t cdbptr; 438 uint8_t cdblen; 439 } cdb_from_host; 440 uint8_t cdb[MAX_CDB_LEN]; 441 struct { 442 uint8_t cdb[MAX_CDB_LEN_WITH_SENSE_ADDR]; 443 sense_addr_t sense_addr; 444 } cdb_plus_saddr; 445}; 446 447/* 448 * Target mode version of the shared data SCB segment. 449 */ 450struct target_data { 451 uint32_t spare[2]; 452 uint8_t scsi_status; /* SCSI status to give to initiator */ 453 uint8_t target_phases; /* Bitmap of phases to execute */ 454 uint8_t data_phase; /* Data-In or Data-Out */ 455 uint8_t initiator_tag; /* Initiator's transaction tag */ 456}; 457 458struct hardware_scb { 459/*0*/ union { 460 union initiator_data idata; 461 struct target_data tdata; 462 struct initiator_status istatus; 463 struct target_status tstatus; 464 } shared_data; 465/* 466 * A word about residuals. 467 * The scb is presented to the sequencer with the dataptr and datacnt 468 * fields initialized to the contents of the first S/G element to 469 * transfer. The sgptr field is initialized to the bus address for 470 * the S/G element that follows the first in the in core S/G array 471 * or'ed with the SG_FULL_RESID flag. Sgptr may point to an invalid 472 * S/G entry for this transfer (single S/G element transfer with the 473 * first elements address and length preloaded in the dataptr/datacnt 474 * fields). If no transfer is to occur, sgptr is set to SG_LIST_NULL. 475 * The SG_FULL_RESID flag ensures that the residual will be correctly 476 * noted even if no data transfers occur. Once the data phase is entered, 477 * the residual sgptr and datacnt are loaded from the sgptr and the 478 * datacnt fields. After each S/G element's dataptr and length are 479 * loaded into the hardware, the residual sgptr is advanced. After 480 * each S/G element is expired, its datacnt field is checked to see 481 * if the LAST_SEG flag is set. If so, SG_LIST_NULL is set in the 482 * residual sg ptr and the transfer is considered complete. If the 483 * sequencer determines that there is a residual in the transfer, or 484 * there is non-zero status, it will set the SG_STATUS_VALID flag in 485 * sgptr and dma the scb back into host memory. To sumarize: 486 * 487 * Sequencer: 488 * o A residual has occurred if SG_FULL_RESID is set in sgptr, 489 * or residual_sgptr does not have SG_LIST_NULL set. 490 * 491 * o We are transferring the last segment if residual_datacnt has 492 * the SG_LAST_SEG flag set. 493 * 494 * Host: 495 * o A residual can only have occurred if a completed scb has the 496 * SG_STATUS_VALID flag set. Inspection of the SCSI status field, 497 * the residual_datacnt, and the residual_sgptr field will tell 498 * for sure. 499 * 500 * o residual_sgptr and sgptr refer to the "next" sg entry 501 * and so may point beyond the last valid sg entry for the 502 * transfer. 503 */ 504#define SG_PTR_MASK 0xFFFFFFF8 505/*16*/ uint16_t tag; /* Reused by Sequencer. */ 506/*18*/ uint8_t control; /* See SCB_CONTROL in aic79xx.reg for details */ 507/*19*/ uint8_t scsiid; /* 508 * Selection out Id 509 * Our Id (bits 0-3) Their ID (bits 4-7) 510 */ 511/*20*/ uint8_t lun; 512/*21*/ uint8_t task_attribute; 513/*22*/ uint8_t cdb_len; 514/*23*/ uint8_t task_management; 515/*24*/ uint64_t dataptr; 516/*32*/ uint32_t datacnt; /* Byte 3 is spare. */ 517/*36*/ uint32_t sgptr; 518/*40*/ uint32_t hscb_busaddr; 519/*44*/ uint32_t next_hscb_busaddr; 520/********** Long lun field only downloaded for full 8 byte lun support ********/ 521/*48*/ uint8_t pkt_long_lun[8]; 522/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/ 523/*56*/ uint8_t spare[8]; 524}; 525 526/************************ Kernel SCB Definitions ******************************/ 527/* 528 * Some fields of the SCB are OS dependent. Here we collect the 529 * definitions for elements that all OS platforms need to include 530 * in there SCB definition. 531 */ 532 533/* 534 * Definition of a scatter/gather element as transferred to the controller. 535 * The aic7xxx chips only support a 24bit length. We use the top byte of 536 * the length to store additional address bits and a flag to indicate 537 * that a given segment terminates the transfer. This gives us an 538 * addressable range of 512GB on machines with 64bit PCI or with chips 539 * that can support dual address cycles on 32bit PCI busses. 540 */ 541struct ahd_dma_seg { 542 uint32_t addr; 543 uint32_t len; 544#define AHD_DMA_LAST_SEG 0x80000000 545#define AHD_SG_HIGH_ADDR_MASK 0x7F000000 546#define AHD_SG_LEN_MASK 0x00FFFFFF 547}; 548 549struct ahd_dma64_seg { 550 uint64_t addr; 551 uint32_t len; 552 uint32_t pad; 553}; 554 555struct map_node { 556 bus_dmamap_t dmamap; 557 bus_addr_t busaddr; 558 uint8_t *vaddr; 559 SLIST_ENTRY(map_node) links; 560}; 561 562/* 563 * The current state of this SCB. 564 */ 565typedef enum { 566 SCB_FLAG_NONE = 0x00000, 567 SCB_TRANSMISSION_ERROR = 0x00001,/* 568 * We detected a parity or CRC 569 * error that has effected the 570 * payload of the command. This 571 * flag is checked when normal 572 * status is returned to catch 573 * the case of a target not 574 * responding to our attempt 575 * to report the error. 576 */ 577 SCB_OTHERTCL_TIMEOUT = 0x00002,/* 578 * Another device was active 579 * during the first timeout for 580 * this SCB so we gave ourselves 581 * an additional timeout period 582 * in case it was hogging the 583 * bus. 584 */ 585 SCB_DEVICE_RESET = 0x00004, 586 SCB_SENSE = 0x00008, 587 SCB_CDB32_PTR = 0x00010, 588 SCB_RECOVERY_SCB = 0x00020, 589 SCB_AUTO_NEGOTIATE = 0x00040,/* Negotiate to achieve goal. */ 590 SCB_NEGOTIATE = 0x00080,/* Negotiation forced for command. */ 591 SCB_ABORT = 0x00100, 592 SCB_ACTIVE = 0x00200, 593 SCB_TARGET_IMMEDIATE = 0x00400, 594 SCB_PACKETIZED = 0x00800, 595 SCB_EXPECT_PPR_BUSFREE = 0x01000, 596 SCB_PKT_SENSE = 0x02000, 597 SCB_CMDPHASE_ABORT = 0x04000, 598 SCB_ON_COL_LIST = 0x08000, 599 SCB_SILENT = 0x10000,/* 600 * Be quiet about transmission type 601 * errors. They are expected and we 602 * don't want to upset the user. This 603 * flag is typically used during DV. 604 */ 605 SCB_TIMEDOUT = 0x20000/* 606 * SCB has timed out and is on the 607 * timedout list. 608 */ 609} scb_flag; 610 611struct scb { 612 struct hardware_scb *hscb; 613 union { 614 SLIST_ENTRY(scb) sle; 615 LIST_ENTRY(scb) le; 616 TAILQ_ENTRY(scb) tqe; 617 } links; 618 union { 619 SLIST_ENTRY(scb) sle; 620 LIST_ENTRY(scb) le; 621 TAILQ_ENTRY(scb) tqe; 622 } links2; 623#define pending_links links2.le 624#define collision_links links2.le 625 LIST_ENTRY(scb) timedout_links; 626 struct scb *col_scb; 627 aic_io_ctx_t io_ctx; 628 struct ahd_softc *ahd_softc; 629 scb_flag flags; 630#ifndef __linux__ 631 bus_dmamap_t dmamap; 632#endif 633 struct scb_platform_data *platform_data; 634 struct map_node *hscb_map; 635 struct map_node *sg_map; 636 struct map_node *sense_map; 637 void *sg_list; 638 uint8_t *sense_data; 639 bus_addr_t sg_list_busaddr; 640 bus_addr_t sense_busaddr; 641 u_int sg_count;/* How full ahd_dma_seg is */ 642#define AHD_MAX_LQ_CRC_ERRORS 5 643 u_int crc_retry_count; 644 aic_timer_t io_timer; 645}; 646 647TAILQ_HEAD(scb_tailq, scb); 648LIST_HEAD(scb_list, scb); 649 650struct scb_data { 651 /* 652 * TAILQ of lists of free SCBs grouped by device 653 * collision domains. 654 */ 655 struct scb_tailq free_scbs; 656 657 /* 658 * Per-device lists of SCBs whose tag ID would collide 659 * with an already active tag on the device. 660 */ 661 struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT]; 662 663 /* 664 * SCBs that will not collide with any active device. 665 */ 666 struct scb_list any_dev_free_scb_list; 667 668 /* 669 * Mapping from tag to SCB. 670 */ 671 struct scb *scbindex[AHD_SCB_MAX]; 672 673 u_int recovery_scbs; /* Transactions currently in recovery */ 674 675 /* 676 * "Bus" addresses of our data structures. 677 */ 678 bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */ 679 bus_dma_tag_t sg_dmat; /* dmat for our sg segments */ 680 bus_dma_tag_t sense_dmat; /* dmat for our sense buffers */ 681 682 SLIST_HEAD(, map_node) hscb_maps; 683 SLIST_HEAD(, map_node) sg_maps; 684 SLIST_HEAD(, map_node) sense_maps; 685 int scbs_left; /* unallocated scbs in head map_node */ 686 int sgs_left; /* unallocated sgs in head map_node */ 687 int sense_left; /* unallocated sense in head map_node */ 688 uint16_t numscbs; 689 uint16_t maxhscbs; /* Number of SCBs on the card */ 690 uint8_t init_level; /* 691 * How far we've initialized 692 * this structure. 693 */ 694}; 695 696/************************ Target Mode Definitions *****************************/ 697 698/* 699 * Connection desciptor for select-in requests in target mode. 700 */ 701struct target_cmd { 702 uint8_t scsiid; /* Our ID and the initiator's ID */ 703 uint8_t identify; /* Identify message */ 704 uint8_t bytes[22]; /* 705 * Bytes contains any additional message 706 * bytes terminated by 0xFF. The remainder 707 * is the cdb to execute. 708 */ 709 uint8_t cmd_valid; /* 710 * When a command is complete, the firmware 711 * will set cmd_valid to all bits set. 712 * After the host has seen the command, 713 * the bits are cleared. This allows us 714 * to just peek at host memory to determine 715 * if more work is complete. cmd_valid is on 716 * an 8 byte boundary to simplify setting 717 * it on aic7880 hardware which only has 718 * limited direct access to the DMA FIFO. 719 */ 720 uint8_t pad[7]; 721}; 722 723/* 724 * Number of events we can buffer up if we run out 725 * of immediate notify ccbs. 726 */ 727#define AHD_TMODE_EVENT_BUFFER_SIZE 8 728struct ahd_tmode_event { 729 uint8_t initiator_id; 730 uint8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */ 731#define EVENT_TYPE_BUS_RESET 0xFF 732 uint8_t event_arg; 733}; 734 735/* 736 * Per enabled lun target mode state. 737 * As this state is directly influenced by the host OS'es target mode 738 * environment, we let the OS module define it. Forward declare the 739 * structure here so we can store arrays of them, etc. in OS neutral 740 * data structures. 741 */ 742#ifdef AHD_TARGET_MODE 743struct ahd_tmode_lstate { 744 struct cam_path *path; 745 struct ccb_hdr_slist accept_tios; 746 struct ccb_hdr_slist immed_notifies; 747 struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE]; 748 uint8_t event_r_idx; 749 uint8_t event_w_idx; 750}; 751#else 752struct ahd_tmode_lstate; 753#endif 754 755/******************** Transfer Negotiation Datastructures *********************/ 756#define AHD_TRANS_CUR 0x01 /* Modify current neogtiation status */ 757#define AHD_TRANS_ACTIVE 0x03 /* Assume this target is on the bus */ 758#define AHD_TRANS_GOAL 0x04 /* Modify negotiation goal */ 759#define AHD_TRANS_USER 0x08 /* Modify user negotiation settings */ 760#define AHD_PERIOD_10MHz 0x19 761 762#define AHD_WIDTH_UNKNOWN 0xFF 763#define AHD_PERIOD_UNKNOWN 0xFF 764#define AHD_OFFSET_UNKNOWN 0xFF 765#define AHD_PPR_OPTS_UNKNOWN 0xFF 766 767/* 768 * Transfer Negotiation Information. 769 */ 770struct ahd_transinfo { 771 uint8_t protocol_version; /* SCSI Revision level */ 772 uint8_t transport_version; /* SPI Revision level */ 773 uint8_t width; /* Bus width */ 774 uint8_t period; /* Sync rate factor */ 775 uint8_t offset; /* Sync offset */ 776 uint8_t ppr_options; /* Parallel Protocol Request options */ 777}; 778 779/* 780 * Per-initiator current, goal and user transfer negotiation information. */ 781struct ahd_initiator_tinfo { 782 struct ahd_transinfo curr; 783 struct ahd_transinfo goal; 784 struct ahd_transinfo user; 785}; 786 787/* 788 * Per enabled target ID state. 789 * Pointers to lun target state as well as sync/wide negotiation information 790 * for each initiator<->target mapping. For the initiator role we pretend 791 * that we are the target and the targets are the initiators since the 792 * negotiation is the same regardless of role. 793 */ 794struct ahd_tmode_tstate { 795 struct ahd_tmode_lstate* enabled_luns[AHD_NUM_LUNS]; 796 struct ahd_initiator_tinfo transinfo[AHD_NUM_TARGETS]; 797 798 /* 799 * Per initiator state bitmasks. 800 */ 801 uint16_t auto_negotiate;/* Auto Negotiation Required */ 802 uint16_t discenable; /* Disconnection allowed */ 803 uint16_t tagenable; /* Tagged Queuing allowed */ 804}; 805 806/* 807 * Points of interest along the negotiated transfer scale. 808 */ 809#define AHD_SYNCRATE_160 0x8 810#define AHD_SYNCRATE_PACED 0x8 811#define AHD_SYNCRATE_DT 0x9 812#define AHD_SYNCRATE_ULTRA2 0xa 813#define AHD_SYNCRATE_ULTRA 0xc 814#define AHD_SYNCRATE_FAST 0x19 815#define AHD_SYNCRATE_MIN_DT AHD_SYNCRATE_FAST 816#define AHD_SYNCRATE_SYNC 0x32 817#define AHD_SYNCRATE_MIN 0x60 818#define AHD_SYNCRATE_ASYNC 0xFF 819#define AHD_SYNCRATE_MAX AHD_SYNCRATE_160 820 821/* Safe and valid period for async negotiations. */ 822#define AHD_ASYNC_XFER_PERIOD 0x44 823 824/* 825 * In RevA, the synctable uses a 120MHz rate for the period 826 * factor 8 and 160MHz for the period factor 7. The 120MHz 827 * rate never made it into the official SCSI spec, so we must 828 * compensate when setting the negotiation table for Rev A 829 * parts. 830 */ 831#define AHD_SYNCRATE_REVA_120 0x8 832#define AHD_SYNCRATE_REVA_160 0x7 833 834/***************************** Lookup Tables **********************************/ 835/* 836 * Phase -> name and message out response 837 * to parity errors in each phase table. 838 */ 839struct ahd_phase_table_entry { 840 uint8_t phase; 841 uint8_t mesg_out; /* Message response to parity errors */ 842 char *phasemsg; 843}; 844 845/************************** Serial EEPROM Format ******************************/ 846 847struct seeprom_config { 848/* 849 * Per SCSI ID Configuration Flags 850 */ 851 uint16_t device_flags[16]; /* words 0-15 */ 852#define CFXFER 0x003F /* synchronous transfer rate */ 853#define CFXFER_ASYNC 0x3F 854#define CFQAS 0x0040 /* Negotiate QAS */ 855#define CFPACKETIZED 0x0080 /* Negotiate Packetized Transfers */ 856#define CFSTART 0x0100 /* send start unit SCSI command */ 857#define CFINCBIOS 0x0200 /* include in BIOS scan */ 858#define CFDISC 0x0400 /* enable disconnection */ 859#define CFMULTILUNDEV 0x0800 /* Probe multiple luns in BIOS scan */ 860#define CFWIDEB 0x1000 /* wide bus device */ 861#define CFHOSTMANAGED 0x8000 /* Managed by a RAID controller */ 862 863/* 864 * BIOS Control Bits 865 */ 866 uint16_t bios_control; /* word 16 */ 867#define CFSUPREM 0x0001 /* support all removeable drives */ 868#define CFSUPREMB 0x0002 /* support removeable boot drives */ 869#define CFBIOSSTATE 0x000C /* BIOS Action State */ 870#define CFBS_DISABLED 0x00 871#define CFBS_ENABLED 0x04 872#define CFBS_DISABLED_SCAN 0x08 873#define CFENABLEDV 0x0010 /* Perform Domain Validation */ 874#define CFCTRL_A 0x0020 /* BIOS displays Ctrl-A message */ 875#define CFSPARITY 0x0040 /* SCSI parity */ 876#define CFEXTEND 0x0080 /* extended translation enabled */ 877#define CFBOOTCD 0x0100 /* Support Bootable CD-ROM */ 878#define CFMSG_LEVEL 0x0600 /* BIOS Message Level */ 879#define CFMSG_VERBOSE 0x0000 880#define CFMSG_SILENT 0x0200 881#define CFMSG_DIAG 0x0400 882#define CFRESETB 0x0800 /* reset SCSI bus at boot */ 883/* UNUSED 0xf000 */ 884 885/* 886 * Host Adapter Control Bits 887 */ 888 uint16_t adapter_control; /* word 17 */ 889#define CFAUTOTERM 0x0001 /* Perform Auto termination */ 890#define CFSTERM 0x0002 /* SCSI low byte termination */ 891#define CFWSTERM 0x0004 /* SCSI high byte termination */ 892#define CFSEAUTOTERM 0x0008 /* Ultra2 Perform secondary Auto Term*/ 893#define CFSELOWTERM 0x0010 /* Ultra2 secondary low term */ 894#define CFSEHIGHTERM 0x0020 /* Ultra2 secondary high term */ 895#define CFSTPWLEVEL 0x0040 /* Termination level control */ 896#define CFBIOSAUTOTERM 0x0080 /* Perform Auto termination */ 897#define CFTERM_MENU 0x0100 /* BIOS displays termination menu */ 898#define CFCLUSTERENB 0x8000 /* Cluster Enable */ 899 900/* 901 * Bus Release Time, Host Adapter ID 902 */ 903 uint16_t brtime_id; /* word 18 */ 904#define CFSCSIID 0x000f /* host adapter SCSI ID */ 905/* UNUSED 0x00f0 */ 906#define CFBRTIME 0xff00 /* bus release time/PCI Latency Time */ 907 908/* 909 * Maximum targets 910 */ 911 uint16_t max_targets; /* word 19 */ 912#define CFMAXTARG 0x00ff /* maximum targets */ 913#define CFBOOTLUN 0x0f00 /* Lun to boot from */ 914#define CFBOOTID 0xf000 /* Target to boot from */ 915 uint16_t res_1[10]; /* words 20-29 */ 916 uint16_t signature; /* BIOS Signature */ 917#define CFSIGNATURE 0x400 918 uint16_t checksum; /* word 31 */ 919}; 920 921/* 922 * Vital Product Data used during POST and by the BIOS. 923 */ 924struct vpd_config { 925 uint8_t bios_flags; 926#define VPDMASTERBIOS 0x0001 927#define VPDBOOTHOST 0x0002 928 uint8_t reserved_1[21]; 929 uint8_t resource_type; 930 uint8_t resource_len[2]; 931 uint8_t resource_data[8]; 932 uint8_t vpd_tag; 933 uint16_t vpd_len; 934 uint8_t vpd_keyword[2]; 935 uint8_t length; 936 uint8_t revision; 937 uint8_t device_flags; 938 uint8_t termnation_menus[2]; 939 uint8_t fifo_threshold; 940 uint8_t end_tag; 941 uint8_t vpd_checksum; 942 uint16_t default_target_flags; 943 uint16_t default_bios_flags; 944 uint16_t default_ctrl_flags; 945 uint8_t default_irq; 946 uint8_t pci_lattime; 947 uint8_t max_target; 948 uint8_t boot_lun; 949 uint16_t signature; 950 uint8_t reserved_2; 951 uint8_t checksum; 952 uint8_t reserved_3[4]; 953}; 954 955/****************************** Flexport Logic ********************************/ 956#define FLXADDR_TERMCTL 0x0 957#define FLX_TERMCTL_ENSECHIGH 0x8 958#define FLX_TERMCTL_ENSECLOW 0x4 959#define FLX_TERMCTL_ENPRIHIGH 0x2 960#define FLX_TERMCTL_ENPRILOW 0x1 961#define FLXADDR_ROMSTAT_CURSENSECTL 0x1 962#define FLX_ROMSTAT_SEECFG 0xF0 963#define FLX_ROMSTAT_EECFG 0x0F 964#define FLX_ROMSTAT_SEE_93C66 0x00 965#define FLX_ROMSTAT_SEE_NONE 0xF0 966#define FLX_ROMSTAT_EE_512x8 0x0 967#define FLX_ROMSTAT_EE_1MBx8 0x1 968#define FLX_ROMSTAT_EE_2MBx8 0x2 969#define FLX_ROMSTAT_EE_4MBx8 0x3 970#define FLX_ROMSTAT_EE_16MBx8 0x4 971#define CURSENSE_ENB 0x1 972#define FLXADDR_FLEXSTAT 0x2 973#define FLX_FSTAT_BUSY 0x1 974#define FLXADDR_CURRENT_STAT 0x4 975#define FLX_CSTAT_SEC_HIGH 0xC0 976#define FLX_CSTAT_SEC_LOW 0x30 977#define FLX_CSTAT_PRI_HIGH 0x0C 978#define FLX_CSTAT_PRI_LOW 0x03 979#define FLX_CSTAT_MASK 0x03 980#define FLX_CSTAT_SHIFT 2 981#define FLX_CSTAT_OKAY 0x0 982#define FLX_CSTAT_OVER 0x1 983#define FLX_CSTAT_UNDER 0x2 984#define FLX_CSTAT_INVALID 0x3 985 986int ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf, 987 u_int start_addr, u_int count, int bstream); 988 989int ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf, 990 u_int start_addr, u_int count); 991int ahd_wait_seeprom(struct ahd_softc *ahd); 992int ahd_verify_vpd_cksum(struct vpd_config *vpd); 993int ahd_verify_cksum(struct seeprom_config *sc); 994int ahd_acquire_seeprom(struct ahd_softc *ahd); 995void ahd_release_seeprom(struct ahd_softc *ahd); 996 997/**************************** Message Buffer *********************************/ 998typedef enum { 999 MSG_FLAG_NONE = 0x00, 1000 MSG_FLAG_EXPECT_PPR_BUSFREE = 0x01, 1001 MSG_FLAG_IU_REQ_CHANGED = 0x02, 1002 MSG_FLAG_EXPECT_IDE_BUSFREE = 0x04, 1003 MSG_FLAG_EXPECT_QASREJ_BUSFREE = 0x08, 1004 MSG_FLAG_PACKETIZED = 0x10 1005} ahd_msg_flags; 1006 1007typedef enum { 1008 MSG_TYPE_NONE = 0x00, 1009 MSG_TYPE_INITIATOR_MSGOUT = 0x01, 1010 MSG_TYPE_INITIATOR_MSGIN = 0x02, 1011 MSG_TYPE_TARGET_MSGOUT = 0x03, 1012 MSG_TYPE_TARGET_MSGIN = 0x04 1013} ahd_msg_type; 1014 1015typedef enum { 1016 MSGLOOP_IN_PROG, 1017 MSGLOOP_MSGCOMPLETE, 1018 MSGLOOP_TERMINATED 1019} msg_loop_stat; 1020 1021/*********************** Software Configuration Structure *********************/ 1022struct ahd_suspend_channel_state { 1023 uint8_t scsiseq; 1024 uint8_t sxfrctl0; 1025 uint8_t sxfrctl1; 1026 uint8_t simode0; 1027 uint8_t simode1; 1028 uint8_t seltimer; 1029 uint8_t seqctl; 1030}; 1031 1032struct ahd_suspend_state { 1033 struct ahd_suspend_channel_state channel[2]; 1034 uint8_t optionmode; 1035 uint8_t dscommand0; 1036 uint8_t dspcistatus; 1037 /* hsmailbox */ 1038 uint8_t crccontrol1; 1039 uint8_t scbbaddr; 1040 /* Host and sequencer SCB counts */ 1041 uint8_t dff_thrsh; 1042 uint8_t *scratch_ram; 1043 uint8_t *btt; 1044}; 1045 1046typedef void (*ahd_bus_intr_t)(struct ahd_softc *); 1047 1048typedef enum { 1049 AHD_MODE_DFF0, 1050 AHD_MODE_DFF1, 1051 AHD_MODE_CCHAN, 1052 AHD_MODE_SCSI, 1053 AHD_MODE_CFG, 1054 AHD_MODE_UNKNOWN 1055} ahd_mode; 1056 1057#define AHD_MK_MSK(x) (0x01 << (x)) 1058#define AHD_MODE_DFF0_MSK AHD_MK_MSK(AHD_MODE_DFF0) 1059#define AHD_MODE_DFF1_MSK AHD_MK_MSK(AHD_MODE_DFF1) 1060#define AHD_MODE_CCHAN_MSK AHD_MK_MSK(AHD_MODE_CCHAN) 1061#define AHD_MODE_SCSI_MSK AHD_MK_MSK(AHD_MODE_SCSI) 1062#define AHD_MODE_CFG_MSK AHD_MK_MSK(AHD_MODE_CFG) 1063#define AHD_MODE_UNKNOWN_MSK AHD_MK_MSK(AHD_MODE_UNKNOWN) 1064#define AHD_MODE_ANY_MSK (~0) 1065 1066typedef enum { 1067 AHD_SYSCTL_ROOT, 1068 AHD_SYSCTL_SUMMARY, 1069 AHD_SYSCTL_DEBUG, 1070 AHD_SYSCTL_NUMBER 1071} ahd_sysctl_types_t; 1072 1073typedef enum { 1074 AHD_ERRORS_CORRECTABLE, 1075 AHD_ERRORS_UNCORRECTABLE, 1076 AHD_ERRORS_FATAL, 1077 AHD_ERRORS_NUMBER 1078} ahd_sysctl_errors_t; 1079 1080#define AHD_CORRECTABLE_ERROR(sc) \ 1081 (((sc)->summerr[AHD_ERRORS_CORRECTABLE])++) 1082#define AHD_UNCORRECTABLE_ERROR(sc) \ 1083 (((sc)->summerr[AHD_ERRORS_UNCORRECTABLE])++) 1084#define AHD_FATAL_ERROR(sc) \ 1085 (((sc)->summerr[AHD_ERRORS_FATAL])++) 1086 1087typedef uint8_t ahd_mode_state; 1088 1089typedef void ahd_callback_t (void *); 1090 1091struct ahd_completion 1092{ 1093 uint16_t tag; 1094 uint8_t sg_status; 1095 uint8_t valid_tag; 1096}; 1097 1098#define AIC_SCB_DATA(softc) (&(softc)->scb_data) 1099 1100struct ahd_softc { 1101 bus_space_tag_t tags[2]; 1102 bus_space_handle_t bshs[2]; 1103#ifndef __linux__ 1104 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 1105#endif 1106 struct scb_data scb_data; 1107 1108 struct hardware_scb *next_queued_hscb; 1109 struct map_node *next_queued_hscb_map; 1110 1111 /* 1112 * SCBs that have been sent to the controller 1113 */ 1114 LIST_HEAD(, scb) pending_scbs; 1115 1116 /* 1117 * SCBs whose timeout routine has been called. 1118 */ 1119 LIST_HEAD(, scb) timedout_scbs; 1120 1121 /* 1122 * Current register window mode information. 1123 */ 1124 ahd_mode dst_mode; 1125 ahd_mode src_mode; 1126 1127 /* 1128 * Saved register window mode information 1129 * used for restore on next unpause. 1130 */ 1131 ahd_mode saved_dst_mode; 1132 ahd_mode saved_src_mode; 1133 1134 /* 1135 * Platform specific data. 1136 */ 1137 struct ahd_platform_data *platform_data; 1138 1139 /* 1140 * Platform specific device information. 1141 */ 1142 aic_dev_softc_t dev_softc; 1143 1144 /* 1145 * Bus specific device information. 1146 */ 1147 ahd_bus_intr_t bus_intr; 1148 1149 /* 1150 * Target mode related state kept on a per enabled lun basis. 1151 * Targets that are not enabled will have null entries. 1152 * As an initiator, we keep one target entry for our initiator 1153 * ID to store our sync/wide transfer settings. 1154 */ 1155 struct ahd_tmode_tstate *enabled_targets[AHD_NUM_TARGETS]; 1156 1157 /* 1158 * The black hole device responsible for handling requests for 1159 * disabled luns on enabled targets. 1160 */ 1161 struct ahd_tmode_lstate *black_hole; 1162 1163 /* 1164 * Device instance currently on the bus awaiting a continue TIO 1165 * for a command that was not given the disconnect priveledge. 1166 */ 1167 struct ahd_tmode_lstate *pending_device; 1168 1169 /* 1170 * Timer handles for timer driven callbacks. 1171 */ 1172 aic_timer_t reset_timer; 1173 aic_timer_t stat_timer; 1174 1175 /* 1176 * Statistics. 1177 */ 1178#define AHD_STAT_UPDATE_MS 250 1179#define AHD_STAT_BUCKETS 4 1180 u_int cmdcmplt_bucket; 1181 uint32_t cmdcmplt_counts[AHD_STAT_BUCKETS]; 1182 uint32_t cmdcmplt_total; 1183 1184 /* 1185 * Errors statistics and printouts. 1186 */ 1187 struct sysctl_ctx_list sysctl_ctx[AHD_SYSCTL_NUMBER]; 1188 struct sysctl_oid *sysctl_tree[AHD_SYSCTL_NUMBER]; 1189 u_int summerr[AHD_ERRORS_NUMBER]; 1190 1191 /* 1192 * Card characteristics 1193 */ 1194 ahd_chip chip; 1195 ahd_feature features; 1196 ahd_bug bugs; 1197 ahd_flag flags; 1198 struct seeprom_config *seep_config; 1199 1200 /* Command Queues */ 1201 struct ahd_completion *qoutfifo; 1202 uint16_t qoutfifonext; 1203 uint16_t qoutfifonext_valid_tag; 1204 uint16_t qinfifonext; 1205 uint16_t qinfifo[AHD_SCB_MAX]; 1206 1207 /* 1208 * Our qfreeze count. The sequencer compares 1209 * this value with its own counter to determine 1210 * whether to allow selections to occur. 1211 */ 1212 uint16_t qfreeze_cnt; 1213 1214 /* Values to store in the SEQCTL register for pause and unpause */ 1215 uint8_t unpause; 1216 uint8_t pause; 1217 1218 /* Critical Section Data */ 1219 struct cs *critical_sections; 1220 u_int num_critical_sections; 1221 1222 /* Buffer for handling packetized bitbucket. */ 1223 uint8_t *overrun_buf; 1224 1225 /* Links for chaining softcs */ 1226 TAILQ_ENTRY(ahd_softc) links; 1227 1228 /* Channel Names ('A', 'B', etc.) */ 1229 char channel; 1230 1231 /* Initiator Bus ID */ 1232 uint8_t our_id; 1233 1234 /* 1235 * Target incoming command FIFO. 1236 */ 1237 struct target_cmd *targetcmds; 1238 uint8_t tqinfifonext; 1239 1240 /* 1241 * Cached verson of the hs_mailbox so we can avoid 1242 * pausing the sequencer during mailbox updates. 1243 */ 1244 uint8_t hs_mailbox; 1245 1246 /* 1247 * Incoming and outgoing message handling. 1248 */ 1249 uint8_t send_msg_perror; 1250 ahd_msg_flags msg_flags; 1251 ahd_msg_type msg_type; 1252 uint8_t msgout_buf[12];/* Message we are sending */ 1253 uint8_t msgin_buf[12];/* Message we are receiving */ 1254 u_int msgout_len; /* Length of message to send */ 1255 u_int msgout_index; /* Current index in msgout */ 1256 u_int msgin_index; /* Current index in msgin */ 1257 1258 /* 1259 * Mapping information for data structures shared 1260 * between the sequencer and kernel. 1261 */ 1262 bus_dma_tag_t parent_dmat; 1263 bus_dma_tag_t shared_data_dmat; 1264 struct map_node shared_data_map; 1265 1266 /* Information saved through suspend/resume cycles */ 1267 struct ahd_suspend_state suspend_state; 1268 1269 /* Number of enabled target mode device on this card */ 1270 u_int enabled_luns; 1271 1272 /* Initialization level of this data structure */ 1273 u_int init_level; 1274 1275 /* PCI cacheline size. */ 1276 u_int pci_cachesize; 1277 1278 /* PCI-X capability offset. */ 1279 int pcix_ptr; 1280 1281 /* IO Cell Parameters */ 1282 uint8_t iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS]; 1283 1284 u_int stack_size; 1285 uint16_t *saved_stack; 1286 1287 /* Per-Unit descriptive information */ 1288 const char *description; 1289 const char *bus_description; 1290 char *name; 1291 int unit; 1292 1293 /* Selection Timer settings */ 1294 int seltime; 1295 1296 /* 1297 * Interrupt coalescing settings. 1298 */ 1299#define AHD_INT_COALESCING_TIMER_DEFAULT 250 /*us*/ 1300#define AHD_INT_COALESCING_MAXCMDS_DEFAULT 10 1301#define AHD_INT_COALESCING_MAXCMDS_MAX 127 1302#define AHD_INT_COALESCING_MINCMDS_DEFAULT 5 1303#define AHD_INT_COALESCING_MINCMDS_MAX 127 1304#define AHD_INT_COALESCING_THRESHOLD_DEFAULT 2000 1305#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT 1000 1306 u_int int_coalescing_timer; 1307 u_int int_coalescing_maxcmds; 1308 u_int int_coalescing_mincmds; 1309 u_int int_coalescing_threshold; 1310 u_int int_coalescing_stop_threshold; 1311 1312 uint16_t user_discenable;/* Disconnection allowed */ 1313 uint16_t user_tagenable;/* Tagged Queuing allowed */ 1314}; 1315 1316TAILQ_HEAD(ahd_softc_tailq, ahd_softc); 1317extern struct ahd_softc_tailq ahd_tailq; 1318 1319/*************************** IO Cell Configuration ****************************/ 1320#define AHD_PRECOMP_SLEW_INDEX \ 1321 (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0) 1322 1323#define AHD_AMPLITUDE_INDEX \ 1324 (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0) 1325 1326#define AHD_SET_SLEWRATE(ahd, new_slew) \ 1327do { \ 1328 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK; \ 1329 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1330 (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK); \ 1331} while (0) 1332 1333#define AHD_SET_PRECOMP(ahd, new_pcomp) \ 1334do { \ 1335 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK; \ 1336 (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |= \ 1337 (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK); \ 1338} while (0) 1339 1340#define AHD_SET_AMPLITUDE(ahd, new_amp) \ 1341do { \ 1342 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK; \ 1343 (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |= \ 1344 (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK); \ 1345} while (0) 1346 1347/************************ Active Device Information ***************************/ 1348typedef enum { 1349 ROLE_UNKNOWN, 1350 ROLE_INITIATOR, 1351 ROLE_TARGET 1352} role_t; 1353 1354struct ahd_devinfo { 1355 int our_scsiid; 1356 int target_offset; 1357 uint16_t target_mask; 1358 u_int target; 1359 u_int lun; 1360 char channel; 1361 role_t role; /* 1362 * Only guaranteed to be correct if not 1363 * in the busfree state. 1364 */ 1365}; 1366 1367/****************************** PCI Structures ********************************/ 1368#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* I/O BAR*/ 1369#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Memory BAR */ 1370#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Second I/O BAR */ 1371 1372typedef int (ahd_device_setup_t)(struct ahd_softc *); 1373 1374struct ahd_pci_identity { 1375 uint64_t full_id; 1376 uint64_t id_mask; 1377 char *name; 1378 ahd_device_setup_t *setup; 1379}; 1380extern struct ahd_pci_identity ahd_pci_ident_table []; 1381extern const u_int ahd_num_pci_devs; 1382 1383/*************************** Function Declarations ****************************/ 1384/******************************************************************************/ 1385void ahd_reset_cmds_pending(struct ahd_softc *ahd); 1386u_int ahd_find_busy_tcl(struct ahd_softc *ahd, u_int tcl); 1387void ahd_busy_tcl(struct ahd_softc *ahd, 1388 u_int tcl, u_int busyid); 1389static __inline void ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl); 1390static __inline void 1391ahd_unbusy_tcl(struct ahd_softc *ahd, u_int tcl) 1392{ 1393 ahd_busy_tcl(ahd, tcl, SCB_LIST_NULL); 1394} 1395 1396/***************************** PCI Front End *********************************/ 1397struct ahd_pci_identity *ahd_find_pci_device(aic_dev_softc_t); 1398int ahd_pci_config(struct ahd_softc *, 1399 struct ahd_pci_identity *); 1400int ahd_pci_test_register_access(struct ahd_softc *); 1401 1402/************************** SCB and SCB queue management **********************/ 1403int ahd_probe_scbs(struct ahd_softc *); 1404void ahd_qinfifo_requeue_tail(struct ahd_softc *ahd, 1405 struct scb *scb); 1406int ahd_match_scb(struct ahd_softc *ahd, struct scb *scb, 1407 int target, char channel, int lun, 1408 u_int tag, role_t role); 1409 1410/****************************** Initialization ********************************/ 1411struct ahd_softc *ahd_alloc(void *platform_arg, char *name); 1412int ahd_softc_init(struct ahd_softc *); 1413void ahd_controller_info(struct ahd_softc *ahd, char *buf); 1414int ahd_init(struct ahd_softc *ahd); 1415int ahd_default_config(struct ahd_softc *ahd); 1416int ahd_parse_vpddata(struct ahd_softc *ahd, 1417 struct vpd_config *vpd); 1418int ahd_parse_cfgdata(struct ahd_softc *ahd, 1419 struct seeprom_config *sc); 1420void ahd_intr_enable(struct ahd_softc *ahd, int enable); 1421void ahd_update_coalescing_values(struct ahd_softc *ahd, 1422 u_int timer, 1423 u_int maxcmds, 1424 u_int mincmds); 1425void ahd_enable_coalescing(struct ahd_softc *ahd, 1426 int enable); 1427void ahd_pause_and_flushwork(struct ahd_softc *ahd); 1428int ahd_suspend(struct ahd_softc *ahd); 1429int ahd_resume(struct ahd_softc *ahd); 1430void ahd_softc_insert(struct ahd_softc *); 1431void ahd_set_unit(struct ahd_softc *, int); 1432void ahd_set_name(struct ahd_softc *, char *); 1433struct scb *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx); 1434void ahd_free_scb(struct ahd_softc *ahd, struct scb *scb); 1435int ahd_alloc_scbs(struct ahd_softc *ahd); 1436void ahd_free(struct ahd_softc *ahd); 1437int ahd_reset(struct ahd_softc *ahd, int reinit); 1438void ahd_shutdown(void *arg); 1439int ahd_write_flexport(struct ahd_softc *ahd, 1440 u_int addr, u_int value); 1441int ahd_read_flexport(struct ahd_softc *ahd, u_int addr, 1442 uint8_t *value); 1443int ahd_wait_flexport(struct ahd_softc *ahd); 1444 1445/*************************** Interrupt Services *******************************/ 1446void ahd_pci_intr(struct ahd_softc *ahd); 1447void ahd_clear_intstat(struct ahd_softc *ahd); 1448void ahd_flush_qoutfifo(struct ahd_softc *ahd); 1449void ahd_run_qoutfifo(struct ahd_softc *ahd); 1450#ifdef AHD_TARGET_MODE 1451void ahd_run_tqinfifo(struct ahd_softc *ahd, int paused); 1452#endif 1453void ahd_handle_hwerrint(struct ahd_softc *ahd); 1454void ahd_handle_seqint(struct ahd_softc *ahd, u_int intstat); 1455void ahd_handle_scsiint(struct ahd_softc *ahd, 1456 u_int intstat); 1457void ahd_clear_critical_section(struct ahd_softc *ahd); 1458 1459/***************************** Error Recovery *********************************/ 1460typedef enum { 1461 SEARCH_COMPLETE, 1462 SEARCH_COUNT, 1463 SEARCH_REMOVE, 1464 SEARCH_PRINT 1465} ahd_search_action; 1466void ahd_done_with_status(struct ahd_softc *ahd, 1467 struct scb *scb, uint32_t status); 1468int ahd_search_qinfifo(struct ahd_softc *ahd, int target, 1469 char channel, int lun, u_int tag, 1470 role_t role, uint32_t status, 1471 ahd_search_action action); 1472int ahd_search_disc_list(struct ahd_softc *ahd, int target, 1473 char channel, int lun, u_int tag, 1474 int stop_on_first, int remove, 1475 int save_state); 1476void ahd_freeze_devq(struct ahd_softc *ahd, struct scb *scb); 1477int ahd_reset_channel(struct ahd_softc *ahd, char channel, 1478 int initiate_reset); 1479int ahd_abort_scbs(struct ahd_softc *ahd, int target, 1480 char channel, int lun, u_int tag, 1481 role_t role, uint32_t status); 1482void ahd_restart(struct ahd_softc *ahd); 1483void ahd_clear_fifo(struct ahd_softc *ahd, u_int fifo); 1484void ahd_handle_scb_status(struct ahd_softc *ahd, 1485 struct scb *scb); 1486void ahd_handle_scsi_status(struct ahd_softc *ahd, 1487 struct scb *scb); 1488void ahd_calc_residual(struct ahd_softc *ahd, 1489 struct scb *scb); 1490void ahd_timeout(struct scb *scb); 1491void ahd_recover_commands(struct ahd_softc *ahd); 1492/*************************** Utility Functions ********************************/ 1493struct ahd_phase_table_entry* 1494 ahd_lookup_phase_entry(int phase); 1495void ahd_compile_devinfo(struct ahd_devinfo *devinfo, 1496 u_int our_id, u_int target, 1497 u_int lun, char channel, 1498 role_t role); 1499/************************** Transfer Negotiation ******************************/ 1500void ahd_find_syncrate(struct ahd_softc *ahd, u_int *period, 1501 u_int *ppr_options, u_int maxsync); 1502void ahd_validate_offset(struct ahd_softc *ahd, 1503 struct ahd_initiator_tinfo *tinfo, 1504 u_int period, u_int *offset, 1505 int wide, role_t role); 1506void ahd_validate_width(struct ahd_softc *ahd, 1507 struct ahd_initiator_tinfo *tinfo, 1508 u_int *bus_width, 1509 role_t role); 1510/* 1511 * Negotiation types. These are used to qualify if we should renegotiate 1512 * even if our goal and current transport parameters are identical. 1513 */ 1514typedef enum { 1515 AHD_NEG_TO_GOAL, /* Renegotiate only if goal and curr differ. */ 1516 AHD_NEG_IF_NON_ASYNC, /* Renegotiate so long as goal is non-async. */ 1517 AHD_NEG_ALWAYS /* Renegotiat even if goal is async. */ 1518} ahd_neg_type; 1519int ahd_update_neg_request(struct ahd_softc*, 1520 struct ahd_devinfo*, 1521 struct ahd_tmode_tstate*, 1522 struct ahd_initiator_tinfo*, 1523 ahd_neg_type); 1524void ahd_set_width(struct ahd_softc *ahd, 1525 struct ahd_devinfo *devinfo, 1526 u_int width, u_int type, int paused); 1527void ahd_set_syncrate(struct ahd_softc *ahd, 1528 struct ahd_devinfo *devinfo, 1529 u_int period, u_int offset, 1530 u_int ppr_options, 1531 u_int type, int paused); 1532typedef enum { 1533 AHD_QUEUE_NONE, 1534 AHD_QUEUE_BASIC, 1535 AHD_QUEUE_TAGGED 1536} ahd_queue_alg; 1537 1538void ahd_set_tags(struct ahd_softc *ahd, 1539 struct ahd_devinfo *devinfo, 1540 ahd_queue_alg alg); 1541 1542/**************************** Target Mode *************************************/ 1543#ifdef AHD_TARGET_MODE 1544void ahd_send_lstate_events(struct ahd_softc *, 1545 struct ahd_tmode_lstate *); 1546void ahd_handle_en_lun(struct ahd_softc *ahd, 1547 struct cam_sim *sim, union ccb *ccb); 1548cam_status ahd_find_tmode_devs(struct ahd_softc *ahd, 1549 struct cam_sim *sim, union ccb *ccb, 1550 struct ahd_tmode_tstate **tstate, 1551 struct ahd_tmode_lstate **lstate, 1552 int notfound_failure); 1553#ifndef AHD_TMODE_ENABLE 1554#define AHD_TMODE_ENABLE 0 1555#endif 1556#endif 1557/******************************* Debug ***************************************/ 1558#ifdef AHD_DEBUG 1559extern uint32_t ahd_debug; 1560#define AHD_SHOW_MISC 0x00001 1561#define AHD_SHOW_SENSE 0x00002 1562#define AHD_SHOW_RECOVERY 0x00004 1563#define AHD_DUMP_SEEPROM 0x00008 1564#define AHD_SHOW_TERMCTL 0x00010 1565#define AHD_SHOW_MEMORY 0x00020 1566#define AHD_SHOW_MESSAGES 0x00040 1567#define AHD_SHOW_MODEPTR 0x00080 1568#define AHD_SHOW_SELTO 0x00100 1569#define AHD_SHOW_FIFOS 0x00200 1570#define AHD_SHOW_QFULL 0x00400 1571#define AHD_SHOW_DV 0x00800 1572#define AHD_SHOW_MASKED_ERRORS 0x01000 1573#define AHD_SHOW_QUEUE 0x02000 1574#define AHD_SHOW_TQIN 0x04000 1575#define AHD_SHOW_SG 0x08000 1576#define AHD_SHOW_INT_COALESCING 0x10000 1577#define AHD_DEBUG_SEQUENCER 0x20000 1578#endif 1579void ahd_print_scb(struct scb *scb); 1580void ahd_print_devinfo(struct ahd_softc *ahd, 1581 struct ahd_devinfo *devinfo); 1582void ahd_dump_sglist(struct scb *scb); 1583void ahd_dump_all_cards_state(void); 1584void ahd_dump_card_state(struct ahd_softc *ahd); 1585int ahd_print_register(ahd_reg_parse_entry_t *table, 1586 u_int num_entries, 1587 const char *name, 1588 u_int address, 1589 u_int value, 1590 u_int *cur_column, 1591 u_int wrap_point); 1592void ahd_dump_scbs(struct ahd_softc *ahd); 1593#endif /* _AIC79XX_H_ */ 1594