1/*-
2 * Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 *
30 * $FreeBSD$
31 */
32
33#ifndef	_ARM64_CORESIGHT_CORESIGHT_H_
34#define	_ARM64_CORESIGHT_CORESIGHT_H_
35
36#include <dev/ofw/openfirm.h>
37
38#define	CORESIGHT_ITCTRL	0xf00
39#define	CORESIGHT_CLAIMSET	0xfa0
40#define	CORESIGHT_CLAIMCLR	0xfa4
41#define	CORESIGHT_LAR		0xfb0
42#define	 CORESIGHT_UNLOCK	0xc5acce55
43#define	CORESIGHT_LSR		0xfb4
44#define	CORESIGHT_AUTHSTATUS	0xfb8
45#define	CORESIGHT_DEVID		0xfc8
46#define	CORESIGHT_DEVTYPE	0xfcc
47
48enum cs_dev_type {
49	CORESIGHT_ETMV4,
50	CORESIGHT_TMC,
51	CORESIGHT_DYNAMIC_REPLICATOR,
52	CORESIGHT_FUNNEL,
53	CORESIGHT_CPU_DEBUG,
54};
55
56struct coresight_device {
57	TAILQ_ENTRY(coresight_device) link;
58	device_t dev;
59	phandle_t node;
60	enum cs_dev_type dev_type;
61	struct coresight_platform_data *pdata;
62};
63
64struct endpoint {
65	TAILQ_ENTRY(endpoint) link;
66	phandle_t my_node;
67	phandle_t their_node;
68	phandle_t dev_node;
69	boolean_t slave;
70	int reg;
71	struct coresight_device *cs_dev;
72	LIST_ENTRY(endpoint) endplink;
73};
74
75struct coresight_platform_data {
76	int cpu;
77	int in_ports;
78	int out_ports;
79	struct mtx mtx_lock;
80	TAILQ_HEAD(endpoint_list, endpoint) endpoints;
81};
82
83struct coresight_desc {
84	struct coresight_platform_data *pdata;
85	device_t dev;
86	enum cs_dev_type dev_type;
87};
88
89TAILQ_HEAD(coresight_device_list, coresight_device);
90
91#define	ETM_N_COMPRATOR		16
92
93struct etm_state {
94	uint32_t trace_id;
95};
96
97struct etr_state {
98	boolean_t started;
99	uint32_t cycle;
100	uint32_t offset;
101	uint32_t low;
102	uint32_t high;
103	uint32_t bufsize;
104	uint32_t flags;
105#define	ETR_FLAG_ALLOCATE	(1 << 0)
106#define	ETR_FLAG_RELEASE	(1 << 1)
107};
108
109struct coresight_event {
110	LIST_HEAD(, endpoint) endplist;
111
112	uint64_t addr[ETM_N_COMPRATOR];
113	uint32_t naddr;
114	uint8_t excp_level;
115	enum cs_dev_type src;
116	enum cs_dev_type sink;
117
118	struct etr_state etr;
119	struct etm_state etm;
120};
121
122struct etm_config {
123	uint64_t addr[ETM_N_COMPRATOR];
124	uint32_t naddr;
125	uint8_t excp_level;
126};
127
128struct coresight_platform_data * coresight_get_platform_data(device_t dev);
129struct endpoint * coresight_get_output_endpoint(struct coresight_platform_data *pdata);
130struct coresight_device * coresight_get_output_device(struct endpoint *endp, struct endpoint **);
131int coresight_register(struct coresight_desc *desc);
132int coresight_init_event(int cpu, struct coresight_event *event);
133void coresight_enable(int cpu, struct coresight_event *event);
134void coresight_disable(int cpu, struct coresight_event *event);
135void coresight_read(int cpu, struct coresight_event *event);
136
137#endif /* !_ARM64_CORESIGHT_CORESIGHT_H_ */
138