1/*-
2 * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
3 * Copyright (c) 2015 Hiroki Mori
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $FreeBSD$
28 */
29
30#ifndef	_ARM_RALINK_RT1310REG_H
31#define	_ARM_RALINK_RT1310REG_H
32
33/*
34 * Interrupt controller
35 */
36
37#define	RT_INTC_SCR0			0x00
38#define	RT_INTC_SVR0			0x80
39#define	RT_INTC_ISR			0x104
40#define	RT_INTC_IPR			0x108
41#define	RT_INTC_IMR			0x10c
42#define	RT_INTC_IECR			0x114
43#define	RT_INTC_ICCR			0x118
44
45#define	RT_INTC_TRIG_LOW_LVL		(0)
46#define	RT_INTC_TRIG_HIGH_LVL		(1)
47#define	RT_INTC_TRIG_NEG_EDGE		(2)
48#define	RT_INTC_TRIG_POS_EDGE		(3)
49
50#define	RT_INTC_TRIG_SHIF		6
51
52/*
53 * Timer 0|1|2|3.
54 */
55
56#define	RT_TIMER_LOAD			0x00
57#define	RT_TIMER_VALUE			0x04
58#define	RT_TIMER_CONTROL		0x08
59
60#define	RT_TIMER_CTRL_INTCTL		(1 << 1)
61#define	RT_TIMER_CTRL_INTCLR		(1 << 2)
62#define	RT_TIMER_CTRL_INTMASK		(1 << 3)
63#define	RT_TIMER_CTRL_DIV16		(3 << 4)
64#define	RT_TIMER_CTRL_DIV256		(7 << 4)
65#define	RT_TIMER_CTRL_PERIODCAL		(1 << 7)
66#define	RT_TIMER_CTRL_ENABLE		(1 << 8)
67
68#define	RT_TIMER_INTERVAL		(5000*150)
69
70/*
71 * GPIO
72 */
73
74#define	RT_GPIO_PORTA	(0)
75#define	RT_GPIO_PORTB	(1)
76
77#define	RT_GPIO_OFF_PADR	(0x0)
78#define	RT_GPIO_OFF_PADIR	(0x4)
79#define	RT_GPIO_OFF_PBDR	(0x8)
80#define	RT_GPIO_OFF_PBDIR	(0xC)
81
82#endif	/* _ARM_RALINK_RT1310REG_H */
83