1/*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD$");
29
30/*
31 * SoC misc configuration and indentification driver.
32 */
33#include <sys/param.h>
34#include <sys/systm.h>
35#include <sys/bus.h>
36#include <sys/clock.h>
37#include <sys/kernel.h>
38#include <sys/limits.h>
39#include <sys/lock.h>
40#include <sys/mutex.h>
41#include <sys/module.h>
42#include <sys/resource.h>
43
44#include <machine/bus.h>
45#include <machine/resource.h>
46#include <sys/rman.h>
47
48#include <dev/ofw/ofw_bus.h>
49#include <dev/ofw/ofw_bus_subr.h>
50
51#include <arm/nvidia/tegra_efuse.h>
52
53#define	PMC_STRAPPING_OPT_A	0  	/* 0x464 */
54
55#define	PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT	4
56#define	PMC_STRAPPING_OPT_A_RAM_CODE_MASK_LONG	\
57	(0xf << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
58#define	PMC_STRAPPING_OPT_A_RAM_CODE_MASK_SHORT	\
59	(0x3 << PMC_STRAPPING_OPT_A_RAM_CODE_SHIFT)
60
61
62#define	ABP_RD4(_sc, _r)	bus_read_4((_sc)->abp_misc_res, (_r))
63#define	STR_RD4(_sc, _r)	bus_read_4((_sc)->strap_opt_res, (_r))
64
65static struct ofw_compat_data compat_data[] = {
66	{"nvidia,tegra124-apbmisc",	1},
67	{NULL,				0}
68};
69
70struct tegra_abpmisc_softc {
71	device_t		dev;
72
73	struct resource		*abp_misc_res;
74	struct resource		*strap_opt_res;
75};
76
77static struct tegra_abpmisc_softc *dev_sc;
78
79static void
80tegra_abpmisc_read_revision(struct tegra_abpmisc_softc *sc)
81{
82	uint32_t id, chip_id, minor_rev;
83	int rev;
84
85	id = ABP_RD4(sc, 4);
86	chip_id = (id >> 8) & 0xff;
87	minor_rev = (id >> 16) & 0xf;
88
89	switch (minor_rev) {
90	case 1:
91		rev = TEGRA_REVISION_A01;
92		break;
93	case 2:
94		rev = TEGRA_REVISION_A02;
95		break;
96	case 3:
97		rev = TEGRA_REVISION_A03;
98		break;
99	case 4:
100		rev = TEGRA_REVISION_A04;
101		break;
102	default:
103		rev = TEGRA_REVISION_UNKNOWN;
104	}
105
106	tegra_sku_info.chip_id = chip_id;
107	tegra_sku_info.revision = rev;
108}
109
110static int
111tegra_abpmisc_probe(device_t dev)
112{
113	if (!ofw_bus_status_okay(dev))
114		return (ENXIO);
115
116	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
117		return (ENXIO);
118
119	return (BUS_PROBE_DEFAULT);
120}
121
122static int
123tegra_abpmisc_attach(device_t dev)
124{
125	int rid;
126	struct tegra_abpmisc_softc *sc;
127
128	sc = device_get_softc(dev);
129	sc->dev = dev;
130
131	rid = 0;
132	sc->abp_misc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
133	    RF_ACTIVE | RF_SHAREABLE);
134	if (sc->abp_misc_res == NULL) {
135		device_printf(dev, "Cannot map ABP misc registers.\n");
136		goto fail;
137	}
138
139	rid = 1;
140	sc->strap_opt_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
141	    RF_ACTIVE);
142	if (sc->strap_opt_res == NULL) {
143		device_printf(dev, "Cannot map strapping options registers.\n");
144		goto fail;
145	}
146
147	tegra_abpmisc_read_revision(sc);
148
149	/* XXX - Hack - address collision with pinmux. */
150	if (sc->abp_misc_res != NULL) {
151		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->abp_misc_res);
152		sc->abp_misc_res = NULL;
153	}
154
155	dev_sc = sc;
156	return (bus_generic_attach(dev));
157
158fail:
159	if (sc->abp_misc_res != NULL)
160		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->abp_misc_res);
161	if (sc->strap_opt_res != NULL)
162		bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->strap_opt_res);
163
164	return (ENXIO);
165}
166
167static int
168tegra_abpmisc_detach(device_t dev)
169{
170	struct tegra_abpmisc_softc *sc;
171
172	sc = device_get_softc(dev);
173	if (sc->abp_misc_res != NULL)
174		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->abp_misc_res);
175	if (sc->strap_opt_res != NULL)
176		bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->strap_opt_res);
177	return (bus_generic_detach(dev));
178}
179
180static device_method_t tegra_abpmisc_methods[] = {
181	/* Device interface */
182	DEVMETHOD(device_probe,		tegra_abpmisc_probe),
183	DEVMETHOD(device_attach,	tegra_abpmisc_attach),
184	DEVMETHOD(device_detach,	tegra_abpmisc_detach),
185
186	DEVMETHOD_END
187};
188
189static devclass_t tegra_abpmisc_devclass;
190static DEFINE_CLASS_0(abpmisc, tegra_abpmisc_driver, tegra_abpmisc_methods,
191    sizeof(struct tegra_abpmisc_softc));
192EARLY_DRIVER_MODULE(tegra_abpmisc, simplebus, tegra_abpmisc_driver,
193    tegra_abpmisc_devclass, NULL, NULL, BUS_PASS_TIMER);
194