1/*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2006 Benno Rice.
5 * Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
6 * All rights reserved.
7 *
8 * Adapted and extended to Marvell SoCs by Semihalf.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 *    notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 *    notice, this list of conditions and the following disclaimer in the
17 *    documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 *
30 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_icu.c, rev 1
31 */
32
33#include <sys/cdefs.h>
34__FBSDID("$FreeBSD$");
35
36#include <sys/param.h>
37#include <sys/systm.h>
38#include <sys/bus.h>
39#include <sys/kernel.h>
40#include <sys/ktr.h>
41#include <sys/module.h>
42#include <sys/rman.h>
43#include <machine/bus.h>
44#include <machine/intr.h>
45
46#include <dev/ofw/ofw_bus.h>
47#include <dev/ofw/ofw_bus_subr.h>
48
49#include <arm/mv/mvreg.h>
50#include <arm/mv/mvvar.h>
51
52struct mv_ic_softc {
53	struct resource	*	ic_res[1];
54	bus_space_tag_t		ic_bst;
55	bus_space_handle_t	ic_bsh;
56	int			ic_high_regs;
57	int			ic_error_regs;
58};
59
60static struct resource_spec mv_ic_spec[] = {
61	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
62	{ -1, 0 }
63};
64
65static struct mv_ic_softc *mv_ic_sc = NULL;
66
67static int	mv_ic_probe(device_t);
68static int	mv_ic_attach(device_t);
69
70uint32_t	mv_ic_get_cause(void);
71uint32_t	mv_ic_get_mask(void);
72void		mv_ic_set_mask(uint32_t);
73uint32_t	mv_ic_get_cause_hi(void);
74uint32_t	mv_ic_get_mask_hi(void);
75void		mv_ic_set_mask_hi(uint32_t);
76uint32_t	mv_ic_get_cause_error(void);
77uint32_t	mv_ic_get_mask_error(void);
78void		mv_ic_set_mask_error(uint32_t);
79static void	arm_mask_irq_all(void);
80
81static int
82mv_ic_probe(device_t dev)
83{
84
85	if (!ofw_bus_status_okay(dev))
86		return (ENXIO);
87
88	if (!ofw_bus_is_compatible(dev, "mrvl,pic"))
89		return (ENXIO);
90
91	device_set_desc(dev, "Marvell Integrated Interrupt Controller");
92	return (0);
93}
94
95static int
96mv_ic_attach(device_t dev)
97{
98	struct mv_ic_softc *sc;
99	uint32_t dev_id, rev_id;
100	int error;
101
102	sc = (struct mv_ic_softc *)device_get_softc(dev);
103
104	if (mv_ic_sc != NULL)
105		return (ENXIO);
106	mv_ic_sc = sc;
107
108	soc_id(&dev_id, &rev_id);
109
110	sc->ic_high_regs = 0;
111	sc->ic_error_regs = 0;
112
113	if (dev_id == MV_DEV_88F6281 ||
114	    dev_id == MV_DEV_88F6282 ||
115	    dev_id == MV_DEV_MV78100 ||
116	    dev_id == MV_DEV_MV78100_Z0)
117		sc->ic_high_regs = 1;
118
119	if (dev_id == MV_DEV_MV78100 || dev_id == MV_DEV_MV78100_Z0)
120		sc->ic_error_regs = 1;
121
122	error = bus_alloc_resources(dev, mv_ic_spec, sc->ic_res);
123	if (error) {
124		device_printf(dev, "could not allocate resources\n");
125		return (ENXIO);
126	}
127
128	sc->ic_bst = rman_get_bustag(sc->ic_res[0]);
129	sc->ic_bsh = rman_get_bushandle(sc->ic_res[0]);
130
131	/* Mask all interrupts */
132	arm_mask_irq_all();
133
134	return (0);
135}
136
137static device_method_t mv_ic_methods[] = {
138	DEVMETHOD(device_probe,		mv_ic_probe),
139	DEVMETHOD(device_attach,	mv_ic_attach),
140	{ 0, 0 }
141};
142
143static driver_t mv_ic_driver = {
144	"ic",
145	mv_ic_methods,
146	sizeof(struct mv_ic_softc),
147};
148
149static devclass_t mv_ic_devclass;
150
151DRIVER_MODULE(ic, simplebus, mv_ic_driver, mv_ic_devclass, 0, 0);
152
153int
154arm_get_next_irq(int last)
155{
156	u_int filt, irq;
157	int next;
158
159	filt = ~((last >= 0) ? (2 << last) - 1 : 0);
160	irq = mv_ic_get_cause() & mv_ic_get_mask();
161	if (irq & filt) {
162		next = ffs(irq & filt) - 1;
163		goto out;
164	}
165	if (mv_ic_sc->ic_high_regs) {
166		filt = ~((last >= 32) ? (2 << (last - 32)) - 1 : 0);
167		irq = mv_ic_get_cause_hi() & mv_ic_get_mask_hi();
168		if (irq & filt) {
169			next = ffs(irq & filt) + 31;
170			goto out;
171		}
172	}
173	if (mv_ic_sc->ic_error_regs) {
174		filt = ~((last >= 64) ? (2 << (last - 64)) - 1 : 0);
175		irq = mv_ic_get_cause_error() & mv_ic_get_mask_error();
176		if (irq & filt) {
177			next = ffs(irq & filt) + 63;
178			goto out;
179		}
180	}
181	next = -1;
182
183 out:
184	CTR3(KTR_INTR, "%s: last=%d, next=%d", __func__, last, next);
185	return (next);
186}
187
188static void
189arm_mask_irq_all(void)
190{
191
192	mv_ic_set_mask(0);
193
194	if (mv_ic_sc->ic_high_regs)
195		mv_ic_set_mask_hi(0);
196
197	if (mv_ic_sc->ic_error_regs)
198		mv_ic_set_mask_error(0);
199}
200
201void
202arm_mask_irq(uintptr_t nb)
203{
204	uint32_t	mr;
205
206	if (nb < 32) {
207		mr = mv_ic_get_mask();
208		mr &= ~(1 << nb);
209		mv_ic_set_mask(mr);
210
211	} else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
212		mr = mv_ic_get_mask_hi();
213		mr &= ~(1 << (nb - 32));
214		mv_ic_set_mask_hi(mr);
215
216	} else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
217		mr = mv_ic_get_mask_error();
218		mr &= ~(1 << (nb - 64));
219		mv_ic_set_mask_error(mr);
220	}
221}
222
223void
224arm_unmask_irq(uintptr_t nb)
225{
226	uint32_t	mr;
227
228	if (nb < 32) {
229		mr = mv_ic_get_mask();
230		mr |= (1 << nb);
231		mv_ic_set_mask(mr);
232
233	} else if ((nb < 64) && mv_ic_sc->ic_high_regs) {
234		mr = mv_ic_get_mask_hi();
235		mr |= (1 << (nb - 32));
236		mv_ic_set_mask_hi(mr);
237
238	} else if ((nb < 96) && mv_ic_sc->ic_error_regs) {
239		mr = mv_ic_get_mask_error();
240		mr |= (1 << (nb - 64));
241		mv_ic_set_mask_error(mr);
242	}
243}
244
245void
246mv_ic_set_mask(uint32_t val)
247{
248
249	bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
250	    IRQ_MASK, val);
251}
252
253uint32_t
254mv_ic_get_mask(void)
255{
256
257	return (bus_space_read_4(mv_ic_sc->ic_bst,
258	    mv_ic_sc->ic_bsh, IRQ_MASK));
259}
260
261uint32_t
262mv_ic_get_cause(void)
263{
264
265	return (bus_space_read_4(mv_ic_sc->ic_bst,
266	    mv_ic_sc->ic_bsh, IRQ_CAUSE));
267}
268
269void
270mv_ic_set_mask_hi(uint32_t val)
271{
272
273	bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
274	    IRQ_MASK_HI, val);
275}
276
277uint32_t
278mv_ic_get_mask_hi(void)
279{
280
281	return (bus_space_read_4(mv_ic_sc->ic_bst,
282	    mv_ic_sc->ic_bsh, IRQ_MASK_HI));
283}
284
285uint32_t
286mv_ic_get_cause_hi(void)
287{
288
289	return (bus_space_read_4(mv_ic_sc->ic_bst,
290	    mv_ic_sc->ic_bsh, IRQ_CAUSE_HI));
291}
292
293void
294mv_ic_set_mask_error(uint32_t val)
295{
296
297	bus_space_write_4(mv_ic_sc->ic_bst, mv_ic_sc->ic_bsh,
298	    IRQ_MASK_ERROR, val);
299}
300
301uint32_t
302mv_ic_get_mask_error(void)
303{
304
305	return (bus_space_read_4(mv_ic_sc->ic_bst,
306	    mv_ic_sc->ic_bsh, IRQ_MASK_ERROR));
307}
308
309uint32_t
310mv_ic_get_cause_error(void)
311{
312
313	return (bus_space_read_4(mv_ic_sc->ic_bst,
314	    mv_ic_sc->ic_bsh, IRQ_CAUSE_ERROR));
315}
316