1/*-
2 * Copyright (c) 2015 Semihalf.
3 * Copyright (c) 2015 Stormshield.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD$");
30
31#include <sys/param.h>
32#include <sys/sysctl.h>
33#include <sys/systm.h>
34#include <sys/bus.h>
35
36#include <machine/fdt.h>
37
38#include <arm/mv/mvwin.h>
39#include <arm/mv/mvreg.h>
40#include <arm/mv/mvvar.h>
41
42int armada38x_open_bootrom_win(void);
43int armada38x_scu_enable(void);
44int armada38x_win_set_iosync_barrier(void);
45int armada38x_mbus_optimization(void);
46static uint64_t get_sar_value_armada38x(void);
47
48static int hw_clockrate;
49SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
50    &hw_clockrate, 0, "CPU instruction clock rate");
51
52static uint64_t
53get_sar_value_armada38x(void)
54{
55	uint32_t sar_low, sar_high;
56
57	sar_high = 0;
58	sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
59	    SAMPLE_AT_RESET_ARMADA38X);
60	return (((uint64_t)sar_high << 32) | sar_low);
61}
62
63uint32_t
64get_tclk_armada38x(void)
65{
66	uint32_t sar;
67
68	/*
69	 * On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
70	 * Current setting is read from Sample At Reset register.
71	 */
72	sar = (uint32_t)get_sar_value_armada38x();
73	sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X;
74	if (sar == 0)
75		return (TCLK_250MHZ);
76	else
77		return (TCLK_200MHZ);
78}
79
80uint32_t
81get_cpu_freq_armada38x(void)
82{
83	uint32_t sar;
84
85	static const uint32_t cpu_frequencies[] = {
86		0, 0, 0, 0,
87		1066, 0, 0, 0,
88		1332, 0, 0, 0,
89		1600, 0, 0, 0,
90		1866, 0, 0, 2000
91	};
92
93	sar = (uint32_t)get_sar_value_armada38x();
94	sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
95	if (sar >= nitems(cpu_frequencies))
96		return (0);
97
98	hw_clockrate = cpu_frequencies[sar];
99
100	return (hw_clockrate * 1000 * 1000);
101}
102
103int
104armada38x_win_set_iosync_barrier(void)
105{
106	bus_space_handle_t vaddr_iowind;
107	int rv;
108
109	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
110	    MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
111	if (rv != 0)
112		return (rv);
113
114	/* Set Sync Barrier flags for all Mbus internal units */
115	bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL,
116	    MV_SYNC_BARRIER_CTRL_ALL);
117
118	bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0,
119	    MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE);
120	bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);
121
122	return (rv);
123}
124
125int
126armada38x_open_bootrom_win(void)
127{
128	bus_space_handle_t vaddr_iowind;
129	uint32_t val;
130	int rv;
131
132	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
133	    MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
134	if (rv != 0)
135		return (rv);
136
137	val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT;
138	val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT;
139	val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT;
140	/* Enable window and Sync Barrier */
141	val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT;
142	val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT;
143
144	/* Configure IO Window Control Register */
145	bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET,
146	    val);
147	/* Configure IO Window Base Register */
148	bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET,
149	    MV_BOOTROM_MEM_ADDR);
150
151	bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN,
152	    BUS_SPACE_BARRIER_WRITE);
153	bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);
154
155	return (rv);
156}
157
158int
159armada38x_mbus_optimization(void)
160{
161	bus_space_handle_t vaddr_iowind;
162	int rv;
163
164	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE,
165	    MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind);
166	if (rv != 0)
167		return (rv);
168
169	/*
170	 * MBUS Units Priority Control Register - Prioritize XOR,
171	 * PCIe and GbEs (ID=4,6,3,7,8) DRAM access
172	 * GbE is High and others are Medium.
173	 */
174	bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180);
175
176	/*
177	 * Fabric Units Priority Control Register -
178	 * Prioritize CPUs requests.
179	 */
180	bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A);
181
182	/*
183	 * MBUS Units Prefetch Control Register -
184	 * Pre-fetch enable for all IO masters.
185	 */
186	bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF);
187
188	/*
189	 * Fabric Units Prefetch Control Register -
190	 * Enable the CPUs Instruction and Data prefetch.
191	 */
192	bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303);
193
194	bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN,
195	    BUS_SPACE_BARRIER_WRITE);
196
197	bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN);
198
199	return (rv);
200}
201
202int
203armada38x_scu_enable(void)
204{
205	bus_space_handle_t vaddr_scu;
206	int rv;
207	uint32_t val;
208
209	rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
210	    MV_SCU_REGS_LEN, 0, &vaddr_scu);
211	if (rv != 0)
212		return (rv);
213
214	/* Enable SCU */
215	val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL);
216	if (!(val & MV_SCU_ENABLE)) {
217		/* Enable SCU Speculative linefills to L2 */
218		val |= MV_SCU_SL_L2_ENABLE;
219
220		bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0,
221		    val | MV_SCU_ENABLE);
222	}
223
224	bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
225	return (0);
226}
227