1/* $NetBSD: disassem.c,v 1.14 2003/03/27 16:58:36 mycroft Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1996 Mark Brinicombe. 7 * Copyright (c) 1996 Brini. 8 * 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by Brini. 22 * 4. The name of the company nor the name of the author may be used to 23 * endorse or promote products derived from this software without specific 24 * prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 27 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 28 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 32 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * RiscBSD kernel project 39 * 40 * db_disasm.c 41 * 42 * Kernel disassembler 43 * 44 * Created : 10/02/96 45 * 46 * Structured after the sparc/sparc/db_disasm.c by David S. Miller & 47 * Paul Kranenburg 48 * 49 * This code is not complete. Not all instructions are disassembled. 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD$"); 54#include <sys/param.h> 55 56 57#include <sys/systm.h> 58#include <machine/disassem.h> 59#include <machine/armreg.h> 60#include <ddb/ddb.h> 61 62/* 63 * General instruction format 64 * 65 * insn[cc][mod] [operands] 66 * 67 * Those fields with an uppercase format code indicate that the field 68 * follows directly after the instruction before the separator i.e. 69 * they modify the instruction rather than just being an operand to 70 * the instruction. The only exception is the writeback flag which 71 * follows a operand. 72 * 73 * 74 * 2 - print Operand 2 of a data processing instruction 75 * d - destination register (bits 12-15) 76 * n - n register (bits 16-19) 77 * s - s register (bits 8-11) 78 * o - indirect register rn (bits 16-19) (used by swap) 79 * m - m register (bits 0-3) 80 * a - address operand of ldr/str instruction 81 * l - register list for ldm/stm instruction 82 * f - 1st fp operand (register) (bits 12-14) 83 * g - 2nd fp operand (register) (bits 16-18) 84 * h - 3rd fp operand (register/immediate) (bits 0-4) 85 * b - branch address 86 * t - thumb branch address (bits 24, 0-23) 87 * k - breakpoint comment (bits 0-3, 8-19) 88 * X - block transfer type 89 * Y - block transfer type (r13 base) 90 * c - comment field bits(0-23) 91 * p - saved or current status register 92 * F - PSR transfer fields 93 * D - destination-is-r15 (P) flag on TST, TEQ, CMP, CMN 94 * L - co-processor transfer size 95 * S - set status flag 96 * P - fp precision 97 * Q - fp precision (for ldf/stf) 98 * R - fp rounding 99 * v - co-processor data transfer registers + addressing mode 100 * W - writeback flag 101 * x - instruction in hex 102 * # - co-processor number 103 * y - co-processor data processing registers 104 * z - co-processor register transfer registers 105 */ 106 107struct arm32_insn { 108 u_int mask; 109 u_int pattern; 110 char* name; 111 char* format; 112}; 113 114static const struct arm32_insn arm32_i[] = { 115 { 0x0fffffff, 0x0ff00000, "imb", "c" }, /* Before swi */ 116 { 0x0fffffff, 0x0ff00001, "imbrange", "c" }, /* Before swi */ 117 { 0x0f000000, 0x0f000000, "swi", "c" }, 118 { 0xfe000000, 0xfa000000, "blx", "t" }, /* Before b and bl */ 119 { 0x0f000000, 0x0a000000, "b", "b" }, 120 { 0x0f000000, 0x0b000000, "bl", "b" }, 121 { 0x0fe000f0, 0x00000090, "mul", "Snms" }, 122 { 0x0fe000f0, 0x00200090, "mla", "Snmsd" }, 123 { 0x0fe000f0, 0x00800090, "umull", "Sdnms" }, 124 { 0x0fe000f0, 0x00c00090, "smull", "Sdnms" }, 125 { 0x0fe000f0, 0x00a00090, "umlal", "Sdnms" }, 126 { 0x0fe000f0, 0x00e00090, "smlal", "Sdnms" }, 127 { 0x0d700000, 0x04200000, "strt", "daW" }, 128 { 0x0d700000, 0x04300000, "ldrt", "daW" }, 129 { 0x0d700000, 0x04600000, "strbt", "daW" }, 130 { 0x0d700000, 0x04700000, "ldrbt", "daW" }, 131 { 0x0c500000, 0x04000000, "str", "daW" }, 132 { 0x0c500000, 0x04100000, "ldr", "daW" }, 133 { 0x0c500000, 0x04400000, "strb", "daW" }, 134 { 0x0c500000, 0x04500000, "ldrb", "daW" }, 135#if __ARM_ARCH >= 6 136 { 0x0fff0ff0, 0x06bf0fb0, "rev16", "dm" }, 137 { 0xffffffff, 0xf57ff01f, "clrex", "c" }, 138 { 0x0ff00ff0, 0x01800f90, "strex", "dmo" }, 139 { 0x0ff00fff, 0x01900f9f, "ldrex", "do" }, 140 { 0x0ff00ff0, 0x01a00f90, "strexd", "dmo" }, 141 { 0x0ff00fff, 0x01b00f9f, "ldrexd", "do" }, 142 { 0x0ff00ff0, 0x01c00f90, "strexb", "dmo" }, 143 { 0x0ff00fff, 0x01d00f9f, "ldrexb", "do" }, 144 { 0x0ff00ff0, 0x01e00f90, "strexh", "dmo" }, 145 { 0x0ff00fff, 0x01f00f9f, "ldrexh", "do" }, 146#endif 147 { 0x0e1f0000, 0x080d0000, "stm", "YnWl" },/* separate out r13 base */ 148 { 0x0e1f0000, 0x081d0000, "ldm", "YnWl" },/* separate out r13 base */ 149 { 0x0e100000, 0x08000000, "stm", "XnWl" }, 150 { 0x0e100000, 0x08100000, "ldm", "XnWl" }, 151 { 0x0e1000f0, 0x00100090, "ldrb", "de" }, 152 { 0x0e1000f0, 0x00000090, "strb", "de" }, 153 { 0x0e1000f0, 0x001000d0, "ldrsb", "de" }, 154 { 0x0e1000f0, 0x001000b0, "ldrh", "de" }, 155 { 0x0e1000f0, 0x000000b0, "strh", "de" }, 156 { 0x0e1000f0, 0x001000f0, "ldrsh", "de" }, 157 { 0x0f200090, 0x00200090, "und", "x" }, /* Before data processing */ 158 { 0x0e1000d0, 0x000000d0, "und", "x" }, /* Before data processing */ 159 { 0x0ff00ff0, 0x01000090, "swp", "dmo" }, 160 { 0x0ff00ff0, 0x01400090, "swpb", "dmo" }, 161 { 0x0fbf0fff, 0x010f0000, "mrs", "dp" }, /* Before data processing */ 162 { 0x0fb0fff0, 0x0120f000, "msr", "pFm" },/* Before data processing */ 163 { 0x0fb0f000, 0x0320f000, "msr", "pF2" },/* Before data processing */ 164 { 0x0ffffff0, 0x012fff10, "bx", "m" }, 165 { 0x0fff0ff0, 0x016f0f10, "clz", "dm" }, 166 { 0x0ffffff0, 0x012fff30, "blx", "m" }, 167 { 0xfff000f0, 0xe1200070, "bkpt", "k" }, 168 { 0x0de00000, 0x00000000, "and", "Sdn2" }, 169 { 0x0de00000, 0x00200000, "eor", "Sdn2" }, 170 { 0x0de00000, 0x00400000, "sub", "Sdn2" }, 171 { 0x0de00000, 0x00600000, "rsb", "Sdn2" }, 172 { 0x0de00000, 0x00800000, "add", "Sdn2" }, 173 { 0x0de00000, 0x00a00000, "adc", "Sdn2" }, 174 { 0x0de00000, 0x00c00000, "sbc", "Sdn2" }, 175 { 0x0de00000, 0x00e00000, "rsc", "Sdn2" }, 176 { 0x0df00000, 0x01100000, "tst", "Dn2" }, 177 { 0x0df00000, 0x01300000, "teq", "Dn2" }, 178 { 0x0de00000, 0x01400000, "cmp", "Dn2" }, 179 { 0x0de00000, 0x01600000, "cmn", "Dn2" }, 180 { 0x0de00000, 0x01800000, "orr", "Sdn2" }, 181 { 0x0de00000, 0x01a00000, "mov", "Sd2" }, 182 { 0x0de00000, 0x01c00000, "bic", "Sdn2" }, 183 { 0x0de00000, 0x01e00000, "mvn", "Sd2" }, 184 { 0x0ff08f10, 0x0e000100, "adf", "PRfgh" }, 185 { 0x0ff08f10, 0x0e100100, "muf", "PRfgh" }, 186 { 0x0ff08f10, 0x0e200100, "suf", "PRfgh" }, 187 { 0x0ff08f10, 0x0e300100, "rsf", "PRfgh" }, 188 { 0x0ff08f10, 0x0e400100, "dvf", "PRfgh" }, 189 { 0x0ff08f10, 0x0e500100, "rdf", "PRfgh" }, 190 { 0x0ff08f10, 0x0e600100, "pow", "PRfgh" }, 191 { 0x0ff08f10, 0x0e700100, "rpw", "PRfgh" }, 192 { 0x0ff08f10, 0x0e800100, "rmf", "PRfgh" }, 193 { 0x0ff08f10, 0x0e900100, "fml", "PRfgh" }, 194 { 0x0ff08f10, 0x0ea00100, "fdv", "PRfgh" }, 195 { 0x0ff08f10, 0x0eb00100, "frd", "PRfgh" }, 196 { 0x0ff08f10, 0x0ec00100, "pol", "PRfgh" }, 197 { 0x0f008f10, 0x0e000100, "fpbop", "PRfgh" }, 198 { 0x0ff08f10, 0x0e008100, "mvf", "PRfh" }, 199 { 0x0ff08f10, 0x0e108100, "mnf", "PRfh" }, 200 { 0x0ff08f10, 0x0e208100, "abs", "PRfh" }, 201 { 0x0ff08f10, 0x0e308100, "rnd", "PRfh" }, 202 { 0x0ff08f10, 0x0e408100, "sqt", "PRfh" }, 203 { 0x0ff08f10, 0x0e508100, "log", "PRfh" }, 204 { 0x0ff08f10, 0x0e608100, "lgn", "PRfh" }, 205 { 0x0ff08f10, 0x0e708100, "exp", "PRfh" }, 206 { 0x0ff08f10, 0x0e808100, "sin", "PRfh" }, 207 { 0x0ff08f10, 0x0e908100, "cos", "PRfh" }, 208 { 0x0ff08f10, 0x0ea08100, "tan", "PRfh" }, 209 { 0x0ff08f10, 0x0eb08100, "asn", "PRfh" }, 210 { 0x0ff08f10, 0x0ec08100, "acs", "PRfh" }, 211 { 0x0ff08f10, 0x0ed08100, "atn", "PRfh" }, 212 { 0x0f008f10, 0x0e008100, "fpuop", "PRfh" }, 213 { 0x0e100f00, 0x0c000100, "stf", "QLv" }, 214 { 0x0e100f00, 0x0c100100, "ldf", "QLv" }, 215 { 0x0ff00f10, 0x0e000110, "flt", "PRgd" }, 216 { 0x0ff00f10, 0x0e100110, "fix", "PRdh" }, 217 { 0x0ff00f10, 0x0e200110, "wfs", "d" }, 218 { 0x0ff00f10, 0x0e300110, "rfs", "d" }, 219 { 0x0ff00f10, 0x0e400110, "wfc", "d" }, 220 { 0x0ff00f10, 0x0e500110, "rfc", "d" }, 221 { 0x0ff0ff10, 0x0e90f110, "cmf", "PRgh" }, 222 { 0x0ff0ff10, 0x0eb0f110, "cnf", "PRgh" }, 223 { 0x0ff0ff10, 0x0ed0f110, "cmfe", "PRgh" }, 224 { 0x0ff0ff10, 0x0ef0f110, "cnfe", "PRgh" }, 225 { 0xff100010, 0xfe000010, "mcr2", "#z" }, 226 { 0x0f100010, 0x0e000010, "mcr", "#z" }, 227 { 0xff100010, 0xfe100010, "mrc2", "#z" }, 228 { 0x0f100010, 0x0e100010, "mrc", "#z" }, 229 { 0xff000010, 0xfe000000, "cdp2", "#y" }, 230 { 0x0f000010, 0x0e000000, "cdp", "#y" }, 231 { 0xfe100090, 0xfc100000, "ldc2", "L#v" }, 232 { 0x0e100090, 0x0c100000, "ldc", "L#v" }, 233 { 0xfe100090, 0xfc000000, "stc2", "L#v" }, 234 { 0x0e100090, 0x0c000000, "stc", "L#v" }, 235 { 0x00000000, 0x00000000, NULL, NULL } 236}; 237 238static char const arm32_insn_conditions[][4] = { 239 "eq", "ne", "cs", "cc", 240 "mi", "pl", "vs", "vc", 241 "hi", "ls", "ge", "lt", 242 "gt", "le", "", "nv" 243}; 244 245static char const insn_block_transfers[][4] = { 246 "da", "ia", "db", "ib" 247}; 248 249static char const insn_stack_block_transfers[][4] = { 250 "ed", "ea", "fd", "fa" 251}; 252 253static char const op_shifts[][4] = { 254 "lsl", "lsr", "asr", "ror" 255}; 256 257static char const insn_fpa_rounding[][2] = { 258 "", "p", "m", "z" 259}; 260 261static char const insn_fpa_precision[][2] = { 262 "s", "d", "e", "p" 263}; 264 265static char const insn_fpaconstants[][8] = { 266 "0.0", "1.0", "2.0", "3.0", 267 "4.0", "5.0", "0.5", "10.0" 268}; 269 270#define insn_condition(x) arm32_insn_conditions[(x >> 28) & 0x0f] 271#define insn_blktrans(x) insn_block_transfers[(x >> 23) & 3] 272#define insn_stkblktrans(x) insn_stack_block_transfers[(x >> 23) & 3] 273#define op2_shift(x) op_shifts[(x >> 5) & 3] 274#define insn_fparnd(x) insn_fpa_rounding[(x >> 5) & 0x03] 275#define insn_fpaprec(x) insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1] 276#define insn_fpaprect(x) insn_fpa_precision[(((x >> 21) & 2)|(x >> 15)) & 1] 277#define insn_fpaimm(x) insn_fpaconstants[x & 0x07] 278 279/* Local prototypes */ 280static void disasm_register_shift(const disasm_interface_t *di, u_int insn); 281static void disasm_print_reglist(const disasm_interface_t *di, u_int insn); 282static void disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, 283 u_int loc); 284static void disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, 285 u_int loc); 286static void disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, 287 u_int loc); 288static u_int disassemble_readword(u_int address); 289static void disassemble_printaddr(u_int address); 290 291vm_offset_t 292disasm(const disasm_interface_t *di, vm_offset_t loc, int altfmt) 293{ 294 const struct arm32_insn *i_ptr = arm32_i; 295 296 u_int insn; 297 int matchp; 298 int branch; 299 char* f_ptr; 300 int fmt; 301 302 fmt = 0; 303 matchp = 0; 304 insn = di->di_readword(loc); 305 306/* di->di_printf("loc=%08x insn=%08x : ", loc, insn);*/ 307 308 while (i_ptr->name) { 309 if ((insn & i_ptr->mask) == i_ptr->pattern) { 310 matchp = 1; 311 break; 312 } 313 i_ptr++; 314 } 315 316 if (!matchp) { 317 di->di_printf("und%s\t%08x\n", insn_condition(insn), insn); 318 return(loc + INSN_SIZE); 319 } 320 321 /* If instruction forces condition code, don't print it. */ 322 if ((i_ptr->mask & 0xf0000000) == 0xf0000000) 323 di->di_printf("%s", i_ptr->name); 324 else 325 di->di_printf("%s%s", i_ptr->name, insn_condition(insn)); 326 327 f_ptr = i_ptr->format; 328 329 /* Insert tab if there are no instruction modifiers */ 330 331 if (*(f_ptr) < 'A' || *(f_ptr) > 'Z') { 332 ++fmt; 333 di->di_printf("\t"); 334 } 335 336 while (*f_ptr) { 337 switch (*f_ptr) { 338 /* 2 - print Operand 2 of a data processing instruction */ 339 case '2': 340 if (insn & 0x02000000) { 341 int rotate= ((insn >> 7) & 0x1e); 342 343 di->di_printf("#0x%08x", 344 (insn & 0xff) << (32 - rotate) | 345 (insn & 0xff) >> rotate); 346 } else { 347 disasm_register_shift(di, insn); 348 } 349 break; 350 /* d - destination register (bits 12-15) */ 351 case 'd': 352 di->di_printf("r%d", ((insn >> 12) & 0x0f)); 353 break; 354 /* D - insert 'p' if Rd is R15 */ 355 case 'D': 356 if (((insn >> 12) & 0x0f) == 15) 357 di->di_printf("p"); 358 break; 359 /* n - n register (bits 16-19) */ 360 case 'n': 361 di->di_printf("r%d", ((insn >> 16) & 0x0f)); 362 break; 363 /* s - s register (bits 8-11) */ 364 case 's': 365 di->di_printf("r%d", ((insn >> 8) & 0x0f)); 366 break; 367 /* o - indirect register rn (bits 16-19) (used by swap) */ 368 case 'o': 369 di->di_printf("[r%d]", ((insn >> 16) & 0x0f)); 370 break; 371 /* m - m register (bits 0-4) */ 372 case 'm': 373 di->di_printf("r%d", ((insn >> 0) & 0x0f)); 374 break; 375 /* a - address operand of ldr/str instruction */ 376 case 'a': 377 disasm_insn_ldrstr(di, insn, loc); 378 break; 379 /* e - address operand of ldrh/strh instruction */ 380 case 'e': 381 disasm_insn_ldrhstrh(di, insn, loc); 382 break; 383 /* l - register list for ldm/stm instruction */ 384 case 'l': 385 disasm_print_reglist(di, insn); 386 break; 387 /* f - 1st fp operand (register) (bits 12-14) */ 388 case 'f': 389 di->di_printf("f%d", (insn >> 12) & 7); 390 break; 391 /* g - 2nd fp operand (register) (bits 16-18) */ 392 case 'g': 393 di->di_printf("f%d", (insn >> 16) & 7); 394 break; 395 /* h - 3rd fp operand (register/immediate) (bits 0-4) */ 396 case 'h': 397 if (insn & (1 << 3)) 398 di->di_printf("#%s", insn_fpaimm(insn)); 399 else 400 di->di_printf("f%d", insn & 7); 401 break; 402 /* b - branch address */ 403 case 'b': 404 branch = ((insn << 2) & 0x03ffffff); 405 if (branch & 0x02000000) 406 branch |= 0xfc000000; 407 di->di_printaddr(loc + 8 + branch); 408 break; 409 /* t - blx address */ 410 case 't': 411 branch = ((insn << 2) & 0x03ffffff) | 412 (insn >> 23 & 0x00000002); 413 if (branch & 0x02000000) 414 branch |= 0xfc000000; 415 di->di_printaddr(loc + 8 + branch); 416 break; 417 /* X - block transfer type */ 418 case 'X': 419 di->di_printf("%s", insn_blktrans(insn)); 420 break; 421 /* Y - block transfer type (r13 base) */ 422 case 'Y': 423 di->di_printf("%s", insn_stkblktrans(insn)); 424 break; 425 /* c - comment field bits(0-23) */ 426 case 'c': 427 di->di_printf("0x%08x", (insn & 0x00ffffff)); 428 break; 429 /* k - breakpoint comment (bits 0-3, 8-19) */ 430 case 'k': 431 di->di_printf("0x%04x", 432 (insn & 0x000fff00) >> 4 | (insn & 0x0000000f)); 433 break; 434 /* p - saved or current status register */ 435 case 'p': 436 if (insn & 0x00400000) 437 di->di_printf("spsr"); 438 else 439 di->di_printf("cpsr"); 440 break; 441 /* F - PSR transfer fields */ 442 case 'F': 443 di->di_printf("_"); 444 if (insn & (1 << 16)) 445 di->di_printf("c"); 446 if (insn & (1 << 17)) 447 di->di_printf("x"); 448 if (insn & (1 << 18)) 449 di->di_printf("s"); 450 if (insn & (1 << 19)) 451 di->di_printf("f"); 452 break; 453 /* B - byte transfer flag */ 454 case 'B': 455 if (insn & 0x00400000) 456 di->di_printf("b"); 457 break; 458 /* L - co-processor transfer size */ 459 case 'L': 460 if (insn & (1 << 22)) 461 di->di_printf("l"); 462 break; 463 /* S - set status flag */ 464 case 'S': 465 if (insn & 0x00100000) 466 di->di_printf("s"); 467 break; 468 /* P - fp precision */ 469 case 'P': 470 di->di_printf("%s", insn_fpaprec(insn)); 471 break; 472 /* Q - fp precision (for ldf/stf) */ 473 case 'Q': 474 break; 475 /* R - fp rounding */ 476 case 'R': 477 di->di_printf("%s", insn_fparnd(insn)); 478 break; 479 /* W - writeback flag */ 480 case 'W': 481 if (insn & (1 << 21)) 482 di->di_printf("!"); 483 break; 484 /* # - co-processor number */ 485 case '#': 486 di->di_printf("p%d", (insn >> 8) & 0x0f); 487 break; 488 /* v - co-processor data transfer registers+addressing mode */ 489 case 'v': 490 disasm_insn_ldcstc(di, insn, loc); 491 break; 492 /* x - instruction in hex */ 493 case 'x': 494 di->di_printf("0x%08x", insn); 495 break; 496 /* y - co-processor data processing registers */ 497 case 'y': 498 di->di_printf("%d, ", (insn >> 20) & 0x0f); 499 500 di->di_printf("c%d, c%d, c%d", (insn >> 12) & 0x0f, 501 (insn >> 16) & 0x0f, insn & 0x0f); 502 503 di->di_printf(", %d", (insn >> 5) & 0x07); 504 break; 505 /* z - co-processor register transfer registers */ 506 case 'z': 507 di->di_printf("%d, ", (insn >> 21) & 0x07); 508 di->di_printf("r%d, c%d, c%d, %d", 509 (insn >> 12) & 0x0f, (insn >> 16) & 0x0f, 510 insn & 0x0f, (insn >> 5) & 0x07); 511 512/* if (((insn >> 5) & 0x07) != 0) 513 di->di_printf(", %d", (insn >> 5) & 0x07);*/ 514 break; 515 default: 516 di->di_printf("[%c - unknown]", *f_ptr); 517 break; 518 } 519 if (*(f_ptr+1) >= 'A' && *(f_ptr+1) <= 'Z') 520 ++f_ptr; 521 else if (*(++f_ptr)) { 522 ++fmt; 523 if (fmt == 1) 524 di->di_printf("\t"); 525 else 526 di->di_printf(", "); 527 } 528 } 529 530 di->di_printf("\n"); 531 532 return(loc + INSN_SIZE); 533} 534 535 536static void 537disasm_register_shift(const disasm_interface_t *di, u_int insn) 538{ 539 di->di_printf("r%d", (insn & 0x0f)); 540 if ((insn & 0x00000ff0) == 0) 541 ; 542 else if ((insn & 0x00000ff0) == 0x00000060) 543 di->di_printf(", rrx"); 544 else { 545 if (insn & 0x10) 546 di->di_printf(", %s r%d", op2_shift(insn), 547 (insn >> 8) & 0x0f); 548 else 549 di->di_printf(", %s #%d", op2_shift(insn), 550 (insn >> 7) & 0x1f); 551 } 552} 553 554 555static void 556disasm_print_reglist(const disasm_interface_t *di, u_int insn) 557{ 558 int loop; 559 int start; 560 int comma; 561 562 di->di_printf("{"); 563 start = -1; 564 comma = 0; 565 566 for (loop = 0; loop < 17; ++loop) { 567 if (start != -1) { 568 if (loop == 16 || !(insn & (1 << loop))) { 569 if (comma) 570 di->di_printf(", "); 571 else 572 comma = 1; 573 if (start == loop - 1) 574 di->di_printf("r%d", start); 575 else 576 di->di_printf("r%d-r%d", start, loop - 1); 577 start = -1; 578 } 579 } else { 580 if (insn & (1 << loop)) 581 start = loop; 582 } 583 } 584 di->di_printf("}"); 585 586 if (insn & (1 << 22)) 587 di->di_printf("^"); 588} 589 590static void 591disasm_insn_ldrstr(const disasm_interface_t *di, u_int insn, u_int loc) 592{ 593 int offset; 594 595 offset = insn & 0xfff; 596 if ((insn & 0x032f0000) == 0x010f0000) { 597 /* rA = pc, immediate index */ 598 if (insn & 0x00800000) 599 loc += offset; 600 else 601 loc -= offset; 602 di->di_printaddr(loc + 8); 603 } else { 604 di->di_printf("[r%d", (insn >> 16) & 0x0f); 605 if ((insn & 0x03000fff) != 0x01000000) { 606 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 607 if (!(insn & 0x00800000)) 608 di->di_printf("-"); 609 if (insn & (1 << 25)) 610 disasm_register_shift(di, insn); 611 else 612 di->di_printf("#0x%03x", offset); 613 } 614 if (insn & (1 << 24)) 615 di->di_printf("]"); 616 } 617} 618 619static void 620disasm_insn_ldrhstrh(const disasm_interface_t *di, u_int insn, u_int loc) 621{ 622 int offset; 623 624 offset = ((insn & 0xf00) >> 4) | (insn & 0xf); 625 if ((insn & 0x004f0000) == 0x004f0000) { 626 /* rA = pc, immediate index */ 627 if (insn & 0x00800000) 628 loc += offset; 629 else 630 loc -= offset; 631 di->di_printaddr(loc + 8); 632 } else { 633 di->di_printf("[r%d", (insn >> 16) & 0x0f); 634 if ((insn & 0x01400f0f) != 0x01400000) { 635 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 636 if (!(insn & 0x00800000)) 637 di->di_printf("-"); 638 if (insn & (1 << 22)) 639 di->di_printf("#0x%02x", offset); 640 else 641 di->di_printf("r%d", (insn & 0x0f)); 642 } 643 if (insn & (1 << 24)) 644 di->di_printf("]"); 645 } 646} 647 648static void 649disasm_insn_ldcstc(const disasm_interface_t *di, u_int insn, u_int loc) 650{ 651 if (((insn >> 8) & 0xf) == 1) 652 di->di_printf("f%d, ", (insn >> 12) & 0x07); 653 else 654 di->di_printf("c%d, ", (insn >> 12) & 0x0f); 655 656 di->di_printf("[r%d", (insn >> 16) & 0x0f); 657 658 di->di_printf("%s, ", (insn & (1 << 24)) ? "" : "]"); 659 660 if (!(insn & (1 << 23))) 661 di->di_printf("-"); 662 663 di->di_printf("#0x%03x", (insn & 0xff) << 2); 664 665 if (insn & (1 << 24)) 666 di->di_printf("]"); 667 668 if (insn & (1 << 21)) 669 di->di_printf("!"); 670} 671 672static u_int 673disassemble_readword(u_int address) 674{ 675 return(*((u_int *)address)); 676} 677 678static void 679disassemble_printaddr(u_int address) 680{ 681 printf("0x%08x", address); 682} 683 684static const disasm_interface_t disassemble_di = { 685 disassemble_readword, disassemble_printaddr, db_printf 686}; 687 688void 689disassemble(u_int address) 690{ 691 692 (void)disasm(&disassemble_di, address, 0); 693} 694 695/* End of disassem.c */ 696