1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2019 Emmanuel Vadot <manu@freebsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/kernel.h> 38#include <sys/module.h> 39#include <machine/bus.h> 40 41#include <dev/fdt/simplebus.h> 42 43#include <dev/ofw/ofw_bus.h> 44#include <dev/ofw/ofw_bus_subr.h> 45 46#include <dev/extres/clk/clk_div.h> 47#include <dev/extres/clk/clk_fixed.h> 48#include <dev/extres/clk/clk_mux.h> 49 50#include <arm/allwinner/clkng/aw_ccung.h> 51 52#include <gnu/dts/include/dt-bindings/clock/sun50i-h6-r-ccu.h> 53#include <gnu/dts/include/dt-bindings/reset/sun50i-h6-r-ccu.h> 54 55/* Non-exported clocks */ 56#define CLK_R_AHB 1 57#define CLK_R_APB2 3 58 59static struct aw_ccung_reset ccu_sun50i_h6_r_resets[] = { 60 CCU_RESET(RST_R_APB1_TIMER, 0x11c, 16) 61 CCU_RESET(RST_R_APB1_TWD, 0x12c, 16) 62 CCU_RESET(RST_R_APB1_PWM, 0x13c, 16) 63 CCU_RESET(RST_R_APB2_UART, 0x18c, 16) 64 CCU_RESET(RST_R_APB2_I2C, 0x19c, 16) 65 CCU_RESET(RST_R_APB1_IR, 0x1cc, 16) 66 CCU_RESET(RST_R_APB1_W1, 0x1ec, 16) 67}; 68 69static struct aw_ccung_gate ccu_sun50i_h6_r_gates[] = { 70 CCU_GATE(CLK_R_APB1_TIMER, "r_apb1-timer", "r_apb1", 0x11c, 0) 71 CCU_GATE(CLK_R_APB1_TWD, "r_apb1-twd", "r_apb1", 0x12c, 0) 72 CCU_GATE(CLK_R_APB1_PWM, "r_apb1-pwm", "r_apb1", 0x13c, 0) 73 CCU_GATE(CLK_R_APB2_UART, "r_apb1-uart", "r_apb2", 0x18c, 0) 74 CCU_GATE(CLK_R_APB2_I2C, "r_apb1-i2c", "r_apb2", 0x19c, 0) 75 CCU_GATE(CLK_R_APB1_IR, "r_apb1-ir", "r_apb1", 0x1cc, 0) 76 CCU_GATE(CLK_R_APB1_W1, "r_apb1-w1", "r_apb1", 0x1ec, 0) 77}; 78 79static const char *ar100_parents[] = {"osc24M", "osc32k", "pll_periph0", "iosc"}; 80PREDIV_CLK(ar100_clk, CLK_AR100, /* id */ 81 "ar100", ar100_parents, /* name, parents */ 82 0x00, /* offset */ 83 16, 2, /* mux */ 84 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 85 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 86 16, 2, 2); /* prediv condition */ 87 88static const char *r_ahb_parents[] = {"ar100"}; 89FIXED_CLK(r_ahb_clk, 90 CLK_R_AHB, /* id */ 91 "r_ahb", /* name */ 92 r_ahb_parents, /* parent */ 93 0, /* freq */ 94 1, /* mult */ 95 1, /* div */ 96 0); /* flags */ 97 98static const char *r_apb1_parents[] = {"r_ahb"}; 99DIV_CLK(r_apb1_clk, 100 CLK_R_APB1, /* id */ 101 "r_apb1", r_apb1_parents, /* name, parents */ 102 0x0c, /* offset */ 103 0, 2, /* shift, width */ 104 0, NULL); /* flags, div table */ 105 106static const char *r_apb2_parents[] = {"osc24M", "osc32k", "pll_periph0", "iosc"}; 107PREDIV_CLK(r_apb2_clk, CLK_R_APB2, /* id */ 108 "r_apb2", r_apb2_parents, /* name, parents */ 109 0x10, /* offset */ 110 16, 2, /* mux */ 111 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* div */ 112 8, 5, 0, AW_CLK_FACTOR_HAS_COND, /* prediv */ 113 16, 2, 2); /* prediv condition */ 114 115static struct aw_ccung_clk clks[] = { 116 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &ar100_clk}, 117 { .type = AW_CLK_FIXED, .clk.fixed = &r_ahb_clk}, 118 { .type = AW_CLK_DIV, .clk.div = &r_apb1_clk}, 119 { .type = AW_CLK_PREDIV_MUX, .clk.prediv_mux = &r_apb2_clk}, 120}; 121 122static struct ofw_compat_data compat_data[] = { 123 { "allwinner,sun50i-h6-r-ccu", 1 }, 124 { NULL, 0}, 125}; 126 127static int 128ccu_sun50i_h6_r_probe(device_t dev) 129{ 130 131 if (!ofw_bus_status_okay(dev)) 132 return (ENXIO); 133 134 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 135 return (ENXIO); 136 137 device_set_desc(dev, "Allwinner SUN50I_H6_R Clock Control Unit NG"); 138 return (BUS_PROBE_DEFAULT); 139} 140 141static int 142ccu_sun50i_h6_r_attach(device_t dev) 143{ 144 struct aw_ccung_softc *sc; 145 146 sc = device_get_softc(dev); 147 148 sc->resets = ccu_sun50i_h6_r_resets; 149 sc->nresets = nitems(ccu_sun50i_h6_r_resets); 150 sc->gates = ccu_sun50i_h6_r_gates; 151 sc->ngates = nitems(ccu_sun50i_h6_r_gates); 152 sc->clks = clks; 153 sc->nclks = nitems(clks); 154 155 return (aw_ccung_attach(dev)); 156} 157 158static device_method_t ccu_sun50i_h6_r_methods[] = { 159 /* Device interface */ 160 DEVMETHOD(device_probe, ccu_sun50i_h6_r_probe), 161 DEVMETHOD(device_attach, ccu_sun50i_h6_r_attach), 162 163 DEVMETHOD_END 164}; 165 166static devclass_t ccu_sun50i_h6_r_devclass; 167 168DEFINE_CLASS_1(ccu_sun50i_h6_r, ccu_sun50i_h6_r_driver, ccu_sun50i_h6_r_methods, 169 sizeof(struct aw_ccung_softc), aw_ccung_driver); 170 171EARLY_DRIVER_MODULE(ccu_sun50i_h6_r, simplebus, ccu_sun50i_h6_r_driver, 172 ccu_sun50i_h6_r_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 173