1/*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Kyle Evans <kevans@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD$"); 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/rman.h> 37#include <sys/kernel.h> 38#include <sys/module.h> 39#include <machine/bus.h> 40 41#include <dev/fdt/simplebus.h> 42 43#include <dev/ofw/ofw_bus.h> 44#include <dev/ofw/ofw_bus_subr.h> 45 46#include <dev/extres/clk/clk_div.h> 47#include <dev/extres/clk/clk_fixed.h> 48#include <dev/extres/clk/clk_mux.h> 49 50#include <arm/allwinner/clkng/aw_ccung.h> 51 52#include <gnu/dts/include/dt-bindings/clock/sun4i-a10-ccu.h> 53#include <gnu/dts/include/dt-bindings/clock/sun7i-a20-ccu.h> 54#include <gnu/dts/include/dt-bindings/reset/sun4i-a10-ccu.h> 55 56/* Non-exported resets */ 57/* Non-exported clocks */ 58#define CLK_PLL_CORE 2 59#define CLK_AXI 3 60#define CLK_AHB 4 61#define CLK_APB0 5 62#define CLK_APB1 6 63#define CLK_PLL_VIDEO0 8 64#define CLK_PLL_DDR 12 65#define CLK_PLL_DDR_OTHER 13 66#define CLK_PLL6 14 67#define CLK_PLL_PERIPH 15 68#define CLK_PLL_SATA 16 69#define CLK_PLL_VIDEO1 17 70 71/* Non-exported fixed clocks */ 72 73static struct aw_ccung_reset a10_ccu_resets[] = { 74 CCU_RESET(RST_USB_PHY0, 0xcc, 0) 75 CCU_RESET(RST_USB_PHY1, 0xcc, 1) 76 CCU_RESET(RST_USB_PHY2, 0xcc, 2) 77 78 CCU_RESET(RST_GPS, 0xd0, 0) 79 80 CCU_RESET(RST_DE_BE0, 0x104, 30) 81 CCU_RESET(RST_DE_BE1, 0x108, 30) 82 CCU_RESET(RST_DE_FE0, 0x10c, 30) 83 CCU_RESET(RST_DE_FE1, 0x110, 30) 84 CCU_RESET(RST_DE_MP, 0x114, 30) 85 86 CCU_RESET(RST_TVE0, 0x118, 29) 87 CCU_RESET(RST_TCON0, 0x118, 30) 88 89 CCU_RESET(RST_TVE1, 0x11c, 29) 90 CCU_RESET(RST_TCON1, 0x11c, 30) 91 92 CCU_RESET(RST_CSI0, 0x134, 30) 93 CCU_RESET(RST_CSI1, 0x138, 30) 94 95 CCU_RESET(RST_VE, 0x13c, 0) 96 97 CCU_RESET(RST_ACE, 0x148, 16) 98 99 CCU_RESET(RST_LVDS, 0x14c, 0) 100 101 CCU_RESET(RST_GPU, 0x154, 30) 102 103 CCU_RESET(RST_HDMI_H, 0x170, 0) 104 CCU_RESET(RST_HDMI_SYS, 0x170, 1) 105 CCU_RESET(RST_HDMI_AUDIO_DMA, 0x170, 2) 106}; 107 108static struct aw_ccung_gate a10_ccu_gates[] = { 109 CCU_GATE(CLK_HOSC, "hosc", "osc24M", 0x50, 0) 110 111 CCU_GATE(CLK_AHB_OTG, "ahb-otg", "ahb", 0x60, 0) 112 CCU_GATE(CLK_AHB_EHCI0, "ahb-ehci0", "ahb", 0x60, 1) 113 CCU_GATE(CLK_AHB_OHCI0, "ahb-ohci0", "ahb", 0x60, 2) 114 CCU_GATE(CLK_AHB_EHCI1, "ahb-ehci1", "ahb", 0x60, 3) 115 CCU_GATE(CLK_AHB_OHCI1, "ahb-ohci1", "ahb", 0x60, 4) 116 CCU_GATE(CLK_AHB_SS, "ahb-ss", "ahb", 0x60, 5) 117 CCU_GATE(CLK_AHB_DMA, "ahb-dma", "ahb", 0x60, 6) 118 CCU_GATE(CLK_AHB_BIST, "ahb-bist", "ahb", 0x60, 7) 119 CCU_GATE(CLK_AHB_MMC0, "ahb-mmc0", "ahb", 0x60, 8) 120 CCU_GATE(CLK_AHB_MMC1, "ahb-mmc1", "ahb", 0x60, 9) 121 CCU_GATE(CLK_AHB_MMC2, "ahb-mmc2", "ahb", 0x60, 10) 122 CCU_GATE(CLK_AHB_MMC3, "ahb-mmc3", "ahb", 0x60, 11) 123 CCU_GATE(CLK_AHB_MS, "ahb-ms", "ahb", 0x60, 12) 124 CCU_GATE(CLK_AHB_NAND, "ahb-nand", "ahb", 0x60, 13) 125 CCU_GATE(CLK_AHB_SDRAM, "ahb-sdram", "ahb", 0x60, 14) 126 CCU_GATE(CLK_AHB_ACE, "ahb-ace", "ahb", 0x60, 16) 127 CCU_GATE(CLK_AHB_EMAC, "ahb-emac", "ahb", 0x60, 17) 128 CCU_GATE(CLK_AHB_TS, "ahb-ts", "ahb", 0x60, 18) 129 CCU_GATE(CLK_AHB_SPI0, "ahb-spi0", "ahb", 0x60, 20) 130 CCU_GATE(CLK_AHB_SPI1, "ahb-spi1", "ahb", 0x60, 21) 131 CCU_GATE(CLK_AHB_SPI2, "ahb-spi2", "ahb", 0x60, 22) 132 CCU_GATE(CLK_AHB_SPI3, "ahb-spi3", "ahb", 0x60, 23) 133 CCU_GATE(CLK_AHB_SATA, "ahb-sata", "ahb", 0x60, 25) 134 135 CCU_GATE(CLK_AHB_VE, "ahb-ve", "ahb", 0x64, 0) 136 CCU_GATE(CLK_AHB_TVD, "ahb-tvd", "ahb", 0x64, 1) 137 CCU_GATE(CLK_AHB_TVE0, "ahb-tve0", "ahb", 0x64, 2) 138 CCU_GATE(CLK_AHB_TVE1, "ahb-tve1", "ahb", 0x64, 3) 139 CCU_GATE(CLK_AHB_LCD0, "ahb-lcd0", "ahb", 0x64, 4) 140 CCU_GATE(CLK_AHB_LCD1, "ahb-lcd1", "ahb", 0x64, 5) 141 CCU_GATE(CLK_AHB_CSI0, "ahb-csi0", "ahb", 0x64, 8) 142 CCU_GATE(CLK_AHB_CSI1, "ahb-csi1", "ahb", 0x64, 9) 143 CCU_GATE(CLK_AHB_HDMI1, "ahb-hdmi1", "ahb", 0x64, 10) 144 CCU_GATE(CLK_AHB_HDMI0, "ahb-hdmi0", "ahb", 0x64, 11) 145 CCU_GATE(CLK_AHB_DE_BE0, "ahb-de_be0", "ahb", 0x64, 12) 146 CCU_GATE(CLK_AHB_DE_BE1, "ahb-de_be1", "ahb", 0x64, 13) 147 CCU_GATE(CLK_AHB_DE_FE0, "ahb-de_fe0", "ahb", 0x64, 14) 148 CCU_GATE(CLK_AHB_DE_FE1, "ahb-de_fe1", "ahb", 0x64, 15) 149 CCU_GATE(CLK_AHB_GMAC, "ahb-gmac", "ahb", 0x64, 17) 150 CCU_GATE(CLK_AHB_MP, "ahb-mp", "ahb", 0x64, 18) 151 CCU_GATE(CLK_AHB_GPU, "ahb-gpu", "ahb", 0x64, 20) 152 153 CCU_GATE(CLK_APB0_CODEC, "apb0-codec", "apb0", 0x68, 0) 154 CCU_GATE(CLK_APB0_SPDIF, "apb0-spdif", "apb0", 0x68, 1) 155 CCU_GATE(CLK_APB0_AC97, "apb0-ac97", "apb0", 0x68, 2) 156 CCU_GATE(CLK_APB0_I2S0, "apb0-i2s0", "apb0", 0x68, 3) 157 CCU_GATE(CLK_APB0_I2S1, "apb0-i2s1", "apb0", 0x68, 4) 158 CCU_GATE(CLK_APB0_PIO, "apb0-pi0", "apb0", 0x68, 5) 159 CCU_GATE(CLK_APB0_IR0, "apb0-ir0", "apb0", 0x68, 6) 160 CCU_GATE(CLK_APB0_IR1, "apb0-ir1", "apb0", 0x68, 7) 161 CCU_GATE(CLK_APB0_I2S2, "apb0-i2s2", "apb0",0x68, 8) 162 CCU_GATE(CLK_APB0_KEYPAD, "apb0-keypad", "apb0", 0x68, 10) 163 164 CCU_GATE(CLK_APB1_I2C0, "apb1-i2c0", "apb1", 0x6c, 0) 165 CCU_GATE(CLK_APB1_I2C1, "apb1-i2c1", "apb1",0x6c, 1) 166 CCU_GATE(CLK_APB1_I2C2, "apb1-i2c2", "apb1",0x6c, 2) 167 CCU_GATE(CLK_APB1_I2C3, "apb1-i2c3", "apb1",0x6c, 3) 168 CCU_GATE(CLK_APB1_CAN, "apb1-can", "apb1",0x6c, 4) 169 CCU_GATE(CLK_APB1_SCR, "apb1-scr", "apb1",0x6c, 5) 170 CCU_GATE(CLK_APB1_PS20, "apb1-ps20", "apb1",0x6c, 6) 171 CCU_GATE(CLK_APB1_PS21, "apb1-ps21", "apb1",0x6c, 7) 172 CCU_GATE(CLK_APB1_I2C4, "apb1-i2c4", "apb1", 0x6c, 15) 173 CCU_GATE(CLK_APB1_UART0, "apb1-uart0", "apb1",0x6c, 16) 174 CCU_GATE(CLK_APB1_UART1, "apb1-uart1", "apb1",0x6c, 17) 175 CCU_GATE(CLK_APB1_UART2, "apb1-uart2", "apb1",0x6c, 18) 176 CCU_GATE(CLK_APB1_UART3, "apb1-uart3", "apb1",0x6c, 19) 177 CCU_GATE(CLK_APB1_UART4, "apb1-uart4", "apb1",0x6c, 20) 178 CCU_GATE(CLK_APB1_UART5, "apb1-uart5", "apb1",0x6c, 21) 179 CCU_GATE(CLK_APB1_UART6, "apb1-uart6", "apb1",0x6c, 22) 180 CCU_GATE(CLK_APB1_UART7, "apb1-uart7", "apb1",0x6c, 23) 181 182 CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "ahb", 0xcc, 6) 183 CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "ahb", 0xcc, 7) 184 CCU_GATE(CLK_USB_PHY, "usb-phy", "ahb", 0xcc, 8) 185 186 CCU_GATE(CLK_DRAM_VE, "dram-ve", "pll_ddr", 0x100, 0) 187 CCU_GATE(CLK_DRAM_CSI0, "dram-csi0", "pll_ddr", 0x100, 1) 188 CCU_GATE(CLK_DRAM_CSI1, "dram-csi1", "pll_ddr", 0x100, 2) 189 CCU_GATE(CLK_DRAM_TS, "dram-ts", "pll_ddr", 0x100, 3) 190 CCU_GATE(CLK_DRAM_TVD, "dram-tvd", "pll_ddr", 0x100, 4) 191 CCU_GATE(CLK_DRAM_TVE0, "dram-tve0", "pll_ddr", 0x100, 5) 192 CCU_GATE(CLK_DRAM_TVE1, "dram-tve1", "pll_ddr", 0x100, 6) 193 CCU_GATE(CLK_DRAM_OUT, "dram-out", "pll_ddr", 0x100, 15) 194 CCU_GATE(CLK_DRAM_DE_FE1, "dram-de_fe1", "pll_ddr", 0x100, 24) 195 CCU_GATE(CLK_DRAM_DE_FE0, "dram-de_fe0", "pll_ddr", 0x100, 25) 196 CCU_GATE(CLK_DRAM_DE_BE0, "dram-de_be0", "pll_ddr", 0x100, 26) 197 CCU_GATE(CLK_DRAM_DE_BE1, "dram-de_be1", "pll_ddr", 0x100, 27) 198 CCU_GATE(CLK_DRAM_MP, "dram-de_mp", "pll_ddr", 0x100, 28) 199 CCU_GATE(CLK_DRAM_ACE, "dram-ace", "pll_ddr", 0x100, 29) 200}; 201 202static const char *pll_parents[] = {"osc24M"}; 203NKMP_CLK(pll_core_clk, 204 CLK_PLL_CORE, /* id */ 205 "pll_core", pll_parents, /* name, parents */ 206 0x00, /* offset */ 207 8, 5, 0, AW_CLK_FACTOR_ZERO_IS_ONE, /* n factor */ 208 4, 2, 0, 0, /* k factor */ 209 0, 2, 0, 0, /* m factor */ 210 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 211 31, /* gate */ 212 0, 0, /* lock */ 213 AW_CLK_HAS_GATE); /* flags */ 214 215FRAC_CLK(pll_video0_clk, 216 CLK_PLL_VIDEO0, /* id */ 217 "pll_video0", pll_parents, /* name, parents */ 218 0x10, /* offset */ 219 0, 7, 0, 0, /* n factor */ 220 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 221 31, 0, 0, /* gate, lock, lock retries */ 222 AW_CLK_HAS_GATE, /* flags */ 223 270000000, 297000000, /* freq0, freq1 */ 224 15, 14, /* mode sel, freq sel */ 225 27000000, 381000000); /* min freq, max freq */ 226static const char *pll_video0_2x_parents[] = {"pll_video0"}; 227FIXED_CLK(pll_video0_2x_clk, 228 CLK_PLL_VIDEO0_2X, /* id */ 229 "pll_video0-2x", pll_video0_2x_parents, /* name, parents */ 230 0, /* freq */ 231 2, /* mult */ 232 1, /* div */ 233 0); /* flags */ 234 235FRAC_CLK(pll_video1_clk, 236 CLK_PLL_VIDEO1, /* id */ 237 "pll_video1", pll_parents, /* name, parents */ 238 0x30, /* offset */ 239 0, 7, 0, 0, /* n factor */ 240 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 241 31, 0, 0, /* gate, lock, lock retries */ 242 AW_CLK_HAS_GATE, /* flags */ 243 270000000, 297000000, /* freq0, freq1 */ 244 15, 14, /* mode sel, freq sel */ 245 27000000, 381000000); /* min freq, max freq */ 246static const char *pll_video1_2x_parents[] = {"pll_video1"}; 247FIXED_CLK(pll_video1_2x_clk, 248 CLK_PLL_VIDEO1_2X, /* id */ 249 "pll_video1-2x", pll_video1_2x_parents, /* name, parents */ 250 0, /* freq */ 251 2, /* mult */ 252 1, /* div */ 253 0); /* flags */ 254 255static const char *cpu_parents[] = {"osc32k", "osc24M", "pll_core", "pll_periph"}; 256static const char *axi_parents[] = {"cpu"}; 257static const char *ahb_parents[] = {"axi", "pll_periph", "pll6"}; 258static const char *apb0_parents[] = {"ahb"}; 259static const char *apb1_parents[] = {"osc24M", "pll_periph", "osc32k"}; 260MUX_CLK(cpu_clk, 261 CLK_CPU, /* id */ 262 "cpu", cpu_parents, /* name, parents */ 263 0x54, 16, 2); /* offset, shift, width */ 264NM_CLK(axi_clk, 265 CLK_AXI, /* id */ 266 "axi", axi_parents, /* name, parents */ 267 0x54, /* offset */ 268 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 269 0, 2, 0, 0, /* m factor */ 270 0, 0, /* mux */ 271 0, /* gate */ 272 0); /* flags */ 273NM_CLK(ahb_clk, 274 CLK_AHB, /* id */ 275 "ahb", ahb_parents, /* name, parents */ 276 0x54, /* offset */ 277 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 278 4, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* m factor */ 279 6, 2, /* mux */ 280 0, /* gate */ 281 AW_CLK_HAS_MUX); /* flags */ 282NM_CLK(apb0_clk, 283 CLK_APB0, /* id */ 284 "apb0", apb0_parents, /* name, parents */ 285 0x54, /* offset */ 286 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 287 8, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO | 288 AW_CLK_FACTOR_ZERO_IS_ONE, /* m factor */ 289 0, 0, /* mux */ 290 0, /* gate */ 291 0); /* flags */ 292 293NM_CLK(apb1_clk, 294 CLK_APB1, /* id */ 295 "apb1", apb1_parents, /* name, parents */ 296 0x58, /* offset */ 297 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 298 0, 5, 0, 0, /* m factor */ 299 24, 2, /* mux */ 300 0, /* gate */ 301 AW_CLK_HAS_MUX); /* flags */ 302 303 304NKMP_CLK(pll_ddr_other_clk, 305 CLK_PLL_DDR_OTHER, /* id */ 306 "pll_ddr_other", pll_parents, /* name, parents */ 307 0x20, /* offset */ 308 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 309 4, 2, 0, 0, /* k factor */ 310 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 311 2, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* p factor */ 312 31, /* gate */ 313 0, 0, /* lock */ 314 AW_CLK_HAS_GATE); /* flags */ 315NKMP_CLK(pll_ddr_clk, 316 CLK_PLL_DDR, /* id */ 317 "pll_ddr", pll_parents, /* name, parents */ 318 0x20, /* offset */ 319 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 320 4, 2, 0, 0, /* k factor */ 321 0, 2, 0, 0, /* m factor */ 322 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 323 31, /* gate */ 324 0, 0, /* lock */ 325 AW_CLK_HAS_GATE); /* flags */ 326 327NKMP_CLK(pll6_clk, 328 CLK_PLL6, /* id */ 329 "pll6", pll_parents, /* name, parents */ 330 0x28, /* offset */ 331 8, 5, 0, AW_CLK_FACTOR_ZERO_BASED, /* n factor */ 332 4, 2, 0, 0, /* k factor */ 333 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 334 0, 0, 1, AW_CLK_FACTOR_FIXED, /* p factor (fake) */ 335 31, /* gate */ 336 0, 0, /* lock */ 337 AW_CLK_HAS_GATE); /* flags */ 338 339static const char *pll6_parents[] = {"pll6"}; 340FIXED_CLK(pll_periph_clk, 341 CLK_PLL_PERIPH, /* id */ 342 "pll_periph", pll6_parents, /* name, parents */ 343 0, /* freq */ 344 1, /* mult */ 345 2, /* div */ 346 0); /* flags */ 347NKMP_CLK(pll_periph_sata_clk, 348 CLK_PLL_SATA, /* id */ 349 "pll_periph_sata", pll6_parents, /* name, parents */ 350 0x28, /* offset */ 351 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 352 0, 0, 1, AW_CLK_FACTOR_FIXED, /* k factor (fake) */ 353 0, 2, 0, 0, /* m factor */ 354 0, 0, 6, AW_CLK_FACTOR_FIXED, /* p factor (fake, 6) */ 355 14, /* gate */ 356 0, 0, /* lock */ 357 AW_CLK_HAS_GATE); /* flags */ 358 359static const char *mod_parents[] = {"osc24M", "pll_periph", "pll_ddr_other"}; 360NM_CLK(nand_clk, 361 CLK_NAND, /* id */ 362 "nand", mod_parents, /* name, parents */ 363 0x80, /* offset */ 364 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 365 0, 4, 0, 0, /* m factor */ 366 24, 2, /* mux */ 367 31, /* gate */ 368 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 369 370NM_CLK(ms_clk, 371 CLK_MS, /* id */ 372 "ms", mod_parents, /* name, parents */ 373 0x84, /* offset */ 374 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 375 0, 4, 0, 0, /* m factor */ 376 24, 2, /* mux */ 377 31, /* gate */ 378 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 379 380NM_CLK(mmc0_clk, 381 CLK_MMC0, /* id */ 382 "mmc0", mod_parents, /* name, parents */ 383 0x88, /* offset */ 384 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 385 0, 4, 0, 0, /* m factor */ 386 24, 2, /* mux */ 387 31, /* gate */ 388 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 389 AW_CLK_REPARENT); /* flags */ 390 391NM_CLK(mmc1_clk, 392 CLK_MMC1, /* id */ 393 "mmc1", mod_parents, /* name, parents */ 394 0x8c, /* offset */ 395 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 396 0, 4, 0, 0, /* m factor */ 397 24, 2, /* mux */ 398 31, /* gate */ 399 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 400 AW_CLK_REPARENT); /* flags */ 401 402NM_CLK(mmc2_clk, 403 CLK_MMC2, /* id */ 404 "mmc2", mod_parents, /* name, parents */ 405 0x90, /* offset */ 406 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 407 0, 4, 0, 0, /* m factor */ 408 24, 2, /* mux */ 409 31, /* gate */ 410 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 411 AW_CLK_REPARENT); /* flags */ 412 413NM_CLK(mmc3_clk, 414 CLK_MMC3, /* id */ 415 "mmc3", mod_parents, /* name, parents */ 416 0x94, /* offset */ 417 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 418 0, 4, 0, 0, /* m factor */ 419 24, 2, /* mux */ 420 31, /* gate */ 421 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE | 422 AW_CLK_REPARENT); /* flags */ 423 424NM_CLK(ts_clk, 425 CLK_TS, /* id */ 426 "ts", mod_parents, /* name, parents */ 427 0x94, /* offset */ 428 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 429 0, 4, 0, 0, /* m factor */ 430 24, 2, /* mux */ 431 31, /* gate */ 432 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 433 434NM_CLK(ss_clk, 435 CLK_SS, /* id */ 436 "ss", mod_parents, /* name, parents */ 437 0x9c, /* offset */ 438 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 439 0, 4, 0, 0, /* m factor */ 440 24, 2, /* mux */ 441 31, /* gate */ 442 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 443 444NM_CLK(spi0_clk, 445 CLK_SPI0, /* id */ 446 "spi0", mod_parents, /* name, parents */ 447 0xa0, /* offset */ 448 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 449 0, 4, 0, 0, /* m factor */ 450 24, 2, /* mux */ 451 31, /* gate */ 452 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 453 454NM_CLK(spi1_clk, 455 CLK_SPI1, /* id */ 456 "spi1", mod_parents, /* name, parents */ 457 0xa4, /* offset */ 458 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 459 0, 4, 0, 0, /* m factor */ 460 24, 2, /* mux */ 461 31, /* gate */ 462 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 463 464NM_CLK(spi2_clk, 465 CLK_SPI2, /* id */ 466 "spi2", mod_parents, /* name, parents */ 467 0xa8, /* offset */ 468 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 469 0, 4, 0, 0, /* m factor */ 470 24, 2, /* mux */ 471 31, /* gate */ 472 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 473 474/* MISSING CLK_PATA */ 475 476NM_CLK(ir0_clk, 477 CLK_IR0, /* id */ 478 "ir0", mod_parents, /* name, parents */ 479 0xb0, /* offset */ 480 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 481 0, 4, 0, 0, /* m factor */ 482 24, 2, /* mux */ 483 31, /* gate */ 484 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 485 486NM_CLK(ir1_clk, 487 CLK_IR1, /* id */ 488 "ir1", mod_parents, /* name, parents */ 489 0xb4, /* offset */ 490 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 491 0, 4, 0, 0, /* m factor */ 492 24, 2, /* mux */ 493 31, /* gate */ 494 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 495 496/* MISSING CLK_I2S0, CLK_AC97, CLK_SPDIF */ 497 498static const char *keypad_parents[] = {"osc24M", "osc24M", "osc32k"}; 499NM_CLK(keypad_clk, 500 CLK_KEYPAD, /* id */ 501 "keypad", keypad_parents, /* name, parents */ 502 0xc4, /* offset */ 503 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 504 0, 5, 0, 0, /* m factor */ 505 24, 2, /* mux */ 506 31, /* gate */ 507 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 508 509static const char *sata_parents[] = {"pll_periph_sata", "osc32k"}; 510NM_CLK(sata_clk, 511 CLK_SATA, /* id */ 512 "sata", sata_parents, /* name, parents */ 513 0xc8, /* offset */ 514 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 515 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ 516 24, 1, /* mux */ 517 31, /* gate */ 518 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 519 520NM_CLK(spi3_clk, 521 CLK_SPI3, /* id */ 522 "spi3", mod_parents, /* name, parents */ 523 0xd4, /* offset */ 524 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 525 0, 4, 0, 0, /* m factor */ 526 24, 2, /* mux */ 527 31, /* gate */ 528 AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ 529 530/* MISSING CLK_I2S1, CLK_I2S2, DE Clocks */ 531 532static struct aw_ccung_clk a10_ccu_clks[] = { 533 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_core_clk}, 534 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_other_clk}, 535 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_ddr_clk}, 536 { .type = AW_CLK_NKMP, .clk.nkmp = &pll6_clk}, 537 { .type = AW_CLK_NKMP, .clk.nkmp = &pll_periph_sata_clk}, 538 { .type = AW_CLK_NM, .clk.nm = &axi_clk}, 539 { .type = AW_CLK_NM, .clk.nm = &ahb_clk}, 540 { .type = AW_CLK_NM, .clk.nm = &apb0_clk}, 541 { .type = AW_CLK_NM, .clk.nm = &apb1_clk}, 542 { .type = AW_CLK_FRAC, .clk.frac = &pll_video0_clk}, 543 { .type = AW_CLK_FRAC, .clk.frac = &pll_video1_clk}, 544 { .type = AW_CLK_NM, .clk.nm = &nand_clk}, 545 { .type = AW_CLK_NM, .clk.nm = &ms_clk}, 546 { .type = AW_CLK_NM, .clk.nm = &mmc0_clk}, 547 { .type = AW_CLK_NM, .clk.nm = &mmc1_clk}, 548 { .type = AW_CLK_NM, .clk.nm = &mmc2_clk}, 549 { .type = AW_CLK_NM, .clk.nm = &mmc3_clk}, 550 { .type = AW_CLK_NM, .clk.nm = &ts_clk}, 551 { .type = AW_CLK_NM, .clk.nm = &ss_clk}, 552 { .type = AW_CLK_NM, .clk.nm = &spi0_clk}, 553 { .type = AW_CLK_NM, .clk.nm = &spi1_clk}, 554 { .type = AW_CLK_NM, .clk.nm = &spi2_clk}, 555 { .type = AW_CLK_NM, .clk.nm = &ir0_clk}, 556 { .type = AW_CLK_NM, .clk.nm = &ir1_clk}, 557 { .type = AW_CLK_NM, .clk.nm = &keypad_clk}, 558 { .type = AW_CLK_NM, .clk.nm = &sata_clk}, 559 { .type = AW_CLK_NM, .clk.nm = &spi3_clk}, 560 { .type = AW_CLK_MUX, .clk.mux = &cpu_clk}, 561 { .type = AW_CLK_FIXED, .clk.fixed = &pll_periph_clk}, 562 { .type = AW_CLK_FIXED, .clk.fixed = &pll_video0_2x_clk}, 563 { .type = AW_CLK_FIXED, .clk.fixed = &pll_video1_2x_clk}, 564}; 565 566static struct aw_clk_init a10_init_clks[] = { 567}; 568 569static struct ofw_compat_data compat_data[] = { 570#if defined(SOC_ALLWINNER_A10) 571 { "allwinner,sun4i-a10-ccu", 1 }, 572#endif 573#if defined(SOC_ALLWINNER_A20) 574 { "allwinner,sun7i-a20-ccu", 1 }, 575#endif 576 { NULL, 0}, 577}; 578 579static int 580ccu_a10_probe(device_t dev) 581{ 582 583 if (!ofw_bus_status_okay(dev)) 584 return (ENXIO); 585 586 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 587 return (ENXIO); 588 589 device_set_desc(dev, "Allwinner A10/A20 Clock Control Unit NG"); 590 return (BUS_PROBE_DEFAULT); 591} 592 593static int 594ccu_a10_attach(device_t dev) 595{ 596 struct aw_ccung_softc *sc; 597 598 sc = device_get_softc(dev); 599 600 sc->resets = a10_ccu_resets; 601 sc->nresets = nitems(a10_ccu_resets); 602 sc->gates = a10_ccu_gates; 603 sc->ngates = nitems(a10_ccu_gates); 604 sc->clks = a10_ccu_clks; 605 sc->nclks = nitems(a10_ccu_clks); 606 sc->clk_init = a10_init_clks; 607 sc->n_clk_init = nitems(a10_init_clks); 608 609 return (aw_ccung_attach(dev)); 610} 611 612static device_method_t ccu_a10ng_methods[] = { 613 /* Device interface */ 614 DEVMETHOD(device_probe, ccu_a10_probe), 615 DEVMETHOD(device_attach, ccu_a10_attach), 616 617 DEVMETHOD_END 618}; 619 620static devclass_t ccu_a10ng_devclass; 621 622DEFINE_CLASS_1(ccu_a10ng, ccu_a10ng_driver, ccu_a10ng_methods, 623 sizeof(struct aw_ccung_softc), aw_ccung_driver); 624 625EARLY_DRIVER_MODULE(ccu_a10ng, simplebus, ccu_a10ng_driver, 626 ccu_a10ng_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE); 627